drivers/net/wireless/marvell/mwifiex/pcie.h

   1 /* @file mwifiex_pcie.h
   2  *
   3  * @brief This file contains definitions for PCI-E interface.
   4  * driver.
   5  *
   6  * Copyright (C) 2011-2014, Marvell International Ltd.
   7  *
   8  * This software file (the "File") is distributed by Marvell International
   9  * Ltd. under the terms of the GNU General Public License Version 2, June 1991
  10  * (the "License").  You may use, redistribute and/or modify this File in
  11  * accordance with the terms and conditions of the License, a copy of which
  12  * is available by writing to the Free Software Foundation, Inc.,
  13  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  14  * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  15  *
  16  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
  19  * this warranty disclaimer.
  20  */
  21
  22 #ifndef _MWIFIEX_PCIE_H
  23 #define _MWIFIEX_PCIE_H
  24
  25 #include    <linux/pci.h>
  26 #include    <linux/interrupt.h>
  27
  28 #include    "decl.h"
  29 #include    "main.h"
  30
  31 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
  32 #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin"
  33 #define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin"
  34 #define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin"
  35 #define PCIE8997_DEFAULT_FW_NAME "mrvl/pcieuart8997_combo_v2.bin"
  36 #define PCIEUART8997_FW_NAME_Z "mrvl/pcieuart8997_combo.bin"
  37 #define PCIEUART8997_FW_NAME_V2 "mrvl/pcieuart8997_combo_v2.bin"
  38 #define PCIEUSB8997_FW_NAME_Z "mrvl/pcieusb8997_combo.bin"
  39 #define PCIEUSB8997_FW_NAME_V2 "mrvl/pcieusb8997_combo_v2.bin"
  40
  41 #define PCIE_VENDOR_ID_MARVELL              (0x11ab)
  42 #define PCIE_VENDOR_ID_V2_MARVELL           (0x1b4b)
  43 #define PCIE_DEVICE_ID_MARVELL_88W8766P         (0x2b30)
  44 #define PCIE_DEVICE_ID_MARVELL_88W8897          (0x2b38)
  45 #define PCIE_DEVICE_ID_MARVELL_88W8997          (0x2b42)
  46
  47 #define PCIE8897_A0     0x1100
  48 #define PCIE8897_B0     0x1200
  49 #define PCIE8997_Z      0x0
  50 #define PCIE8997_V2     0x471
  51 #define CHIP_VER_PCIEUSB        0x2
  52
  53 /* Constants for Buffer Descriptor (BD) rings */
  54 #define MWIFIEX_MAX_TXRX_BD                     0x20
  55 #define MWIFIEX_TXBD_MASK                       0x3F
  56 #define MWIFIEX_RXBD_MASK                       0x3F
  57
  58 #define MWIFIEX_MAX_EVT_BD                      0x08
  59 #define MWIFIEX_EVTBD_MASK                      0x0f
  60
  61 /* PCIE INTERNAL REGISTERS */
  62 #define PCIE_SCRATCH_0_REG                              0xC10
  63 #define PCIE_SCRATCH_1_REG                              0xC14
  64 #define PCIE_CPU_INT_EVENT                              0xC18
  65 #define PCIE_CPU_INT_STATUS                             0xC1C
  66 #define PCIE_HOST_INT_STATUS                            0xC30
  67 #define PCIE_HOST_INT_MASK                              0xC34
  68 #define PCIE_HOST_INT_STATUS_MASK                       0xC3C
  69 #define PCIE_SCRATCH_2_REG                              0xC40
  70 #define PCIE_SCRATCH_3_REG                              0xC44
  71 #define PCIE_SCRATCH_4_REG                              0xCD0
  72 #define PCIE_SCRATCH_5_REG                              0xCD4
  73 #define PCIE_SCRATCH_6_REG                              0xCD8
  74 #define PCIE_SCRATCH_7_REG                              0xCDC
  75 #define PCIE_SCRATCH_8_REG                              0xCE0
  76 #define PCIE_SCRATCH_9_REG                              0xCE4
  77 #define PCIE_SCRATCH_10_REG                             0xCE8
  78 #define PCIE_SCRATCH_11_REG                             0xCEC
  79 #define PCIE_SCRATCH_12_REG                             0xCF0
  80 #define PCIE_SCRATCH_13_REG                             0xCF8
  81 #define PCIE_SCRATCH_14_REG                             0xCFC
  82 #define PCIE_RD_DATA_PTR_Q0_Q1                          0xC08C
  83 #define PCIE_WR_DATA_PTR_Q0_Q1                          0xC05C
  84
  85 #define CPU_INTR_DNLD_RDY                               BIT(0)
  86 #define CPU_INTR_DOOR_BELL                              BIT(1)
  87 #define CPU_INTR_SLEEP_CFM_DONE                 BIT(2)
  88 #define CPU_INTR_RESET                                  BIT(3)
  89 #define CPU_INTR_EVENT_DONE                             BIT(5)
  90
  91 #define HOST_INTR_DNLD_DONE                             BIT(0)
  92 #define HOST_INTR_UPLD_RDY                              BIT(1)
  93 #define HOST_INTR_CMD_DONE                              BIT(2)
  94 #define HOST_INTR_EVENT_RDY                             BIT(3)
  95 #define HOST_INTR_MASK                                  (HOST_INTR_DNLD_DONE | \
  96                                                          HOST_INTR_UPLD_RDY  | \
  97                                                          HOST_INTR_CMD_DONE  | \
  98                                                          HOST_INTR_EVENT_RDY)
  99
 100 #define MWIFIEX_BD_FLAG_ROLLOVER_IND                    BIT(7)
 101 #define MWIFIEX_BD_FLAG_FIRST_DESC                      BIT(0)
 102 #define MWIFIEX_BD_FLAG_LAST_DESC                       BIT(1)
 103 #define MWIFIEX_BD_FLAG_SOP                             BIT(0)
 104 #define MWIFIEX_BD_FLAG_EOP                             BIT(1)
 105 #define MWIFIEX_BD_FLAG_XS_SOP                          BIT(2)
 106 #define MWIFIEX_BD_FLAG_XS_EOP                          BIT(3)
 107 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND                BIT(7)
 108 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND                 BIT(10)
 109 #define MWIFIEX_BD_FLAG_TX_START_PTR                    BIT(16)
 110 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND                 BIT(26)
 111
 112 /* Max retry number of command write */
 113 #define MAX_WRITE_IOMEM_RETRY                           2
 114 /* Define PCIE block size for firmware download */
 115 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD         256
 116 /* FW awake cookie after FW ready */
 117 #define FW_AWAKE_COOKIE                                         (0xAA55AA55)
 118 #define MWIFIEX_DEF_SLEEP_COOKIE                        0xBEEFBEEF
 119 #define MWIFIEX_MAX_DELAY_COUNT                         100
 120
 121 struct mwifiex_pcie_card_reg {
 122         u16 cmd_addr_lo;
 123         u16 cmd_addr_hi;
 124         u16 fw_status;
 125         u16 cmd_size;
 126         u16 cmdrsp_addr_lo;
 127         u16 cmdrsp_addr_hi;
 128         u16 tx_rdptr;
 129         u16 tx_wrptr;
 130         u16 rx_rdptr;
 131         u16 rx_wrptr;
 132         u16 evt_rdptr;
 133         u16 evt_wrptr;
 134         u16 drv_rdy;
 135         u16 tx_start_ptr;
 136         u32 tx_mask;
 137         u32 tx_wrap_mask;
 138         u32 rx_mask;
 139         u32 rx_wrap_mask;
 140         u32 tx_rollover_ind;
 141         u32 rx_rollover_ind;
 142         u32 evt_rollover_ind;
 143         u8 ring_flag_sop;
 144         u8 ring_flag_eop;
 145         u8 ring_flag_xs_sop;
 146         u8 ring_flag_xs_eop;
 147         u32 ring_tx_start_ptr;
 148         u8 pfu_enabled;
 149         u8 sleep_cookie;
 150         u16 fw_dump_ctrl;
 151         u16 fw_dump_start;
 152         u16 fw_dump_end;
 153         u8 fw_dump_host_ready;
 154         u8 fw_dump_read_done;
 155         u8 msix_support;
 156 };
 157
 158 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
 159         .cmd_addr_lo = PCIE_SCRATCH_0_REG,
 160         .cmd_addr_hi = PCIE_SCRATCH_1_REG,
 161         .cmd_size = PCIE_SCRATCH_2_REG,
 162         .fw_status = PCIE_SCRATCH_3_REG,
 163         .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
 164         .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
 165         .tx_rdptr = PCIE_SCRATCH_6_REG,
 166         .tx_wrptr = PCIE_SCRATCH_7_REG,
 167         .rx_rdptr = PCIE_SCRATCH_8_REG,
 168         .rx_wrptr = PCIE_SCRATCH_9_REG,
 169         .evt_rdptr = PCIE_SCRATCH_10_REG,
 170         .evt_wrptr = PCIE_SCRATCH_11_REG,
 171         .drv_rdy = PCIE_SCRATCH_12_REG,
 172         .tx_start_ptr = 0,
 173         .tx_mask = MWIFIEX_TXBD_MASK,
 174         .tx_wrap_mask = 0,
 175         .rx_mask = MWIFIEX_RXBD_MASK,
 176         .rx_wrap_mask = 0,
 177         .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
 178         .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
 179         .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
 180         .ring_flag_sop = 0,
 181         .ring_flag_eop = 0,
 182         .ring_flag_xs_sop = 0,
 183         .ring_flag_xs_eop = 0,
 184         .ring_tx_start_ptr = 0,
 185         .pfu_enabled = 0,
 186         .sleep_cookie = 1,
 187         .msix_support = 0,
 188 };
 189
 190 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
 191         .cmd_addr_lo = PCIE_SCRATCH_0_REG,
 192         .cmd_addr_hi = PCIE_SCRATCH_1_REG,
 193         .cmd_size = PCIE_SCRATCH_2_REG,
 194         .fw_status = PCIE_SCRATCH_3_REG,
 195         .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
 196         .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
 197         .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
 198         .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
 199         .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
 200         .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
 201         .evt_rdptr = PCIE_SCRATCH_10_REG,
 202         .evt_wrptr = PCIE_SCRATCH_11_REG,
 203         .drv_rdy = PCIE_SCRATCH_12_REG,
 204         .tx_start_ptr = 16,
 205         .tx_mask = 0x03FF0000,
 206         .tx_wrap_mask = 0x07FF0000,
 207         .rx_mask = 0x000003FF,
 208         .rx_wrap_mask = 0x000007FF,
 209         .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
 210         .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
 211         .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
 212         .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
 213         .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
 214         .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
 215         .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
 216         .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
 217         .pfu_enabled = 1,
 218         .sleep_cookie = 0,
 219         .fw_dump_ctrl = 0xcf4,
 220         .fw_dump_start = 0xcf8,
 221         .fw_dump_end = 0xcff,
 222         .fw_dump_host_ready = 0xee,
 223         .fw_dump_read_done = 0xfe,
 224         .msix_support = 0,
 225 };
 226
 227 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
 228         .cmd_addr_lo = PCIE_SCRATCH_0_REG,
 229         .cmd_addr_hi = PCIE_SCRATCH_1_REG,
 230         .cmd_size = PCIE_SCRATCH_2_REG,
 231         .fw_status = PCIE_SCRATCH_3_REG,
 232         .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
 233         .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
 234         .tx_rdptr = 0xC1A4,
 235         .tx_wrptr = 0xC174,
 236         .rx_rdptr = 0xC174,
 237         .rx_wrptr = 0xC1A4,
 238         .evt_rdptr = PCIE_SCRATCH_10_REG,
 239         .evt_wrptr = PCIE_SCRATCH_11_REG,
 240         .drv_rdy = PCIE_SCRATCH_12_REG,
 241         .tx_start_ptr = 16,
 242         .tx_mask = 0x0FFF0000,
 243         .tx_wrap_mask = 0x1FFF0000,
 244         .rx_mask = 0x00000FFF,
 245         .rx_wrap_mask = 0x00001FFF,
 246         .tx_rollover_ind = BIT(28),
 247         .rx_rollover_ind = BIT(12),
 248         .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
 249         .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
 250         .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
 251         .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
 252         .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
 253         .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
 254         .pfu_enabled = 1,
 255         .sleep_cookie = 0,
 256         .fw_dump_ctrl = 0xcf4,
 257         .fw_dump_start = 0xcf8,
 258         .fw_dump_end = 0xcff,
 259         .fw_dump_host_ready = 0xcc,
 260         .fw_dump_read_done = 0xdd,
 261         .msix_support = 1,
 262 };
 263
 264 static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
 265         {"ITCM", NULL, 0, 0xF0},
 266         {"DTCM", NULL, 0, 0xF1},
 267         {"SQRAM", NULL, 0, 0xF2},
 268         {"IRAM", NULL, 0, 0xF3},
 269         {"APU", NULL, 0, 0xF4},
 270         {"CIU", NULL, 0, 0xF5},
 271         {"ICU", NULL, 0, 0xF6},
 272         {"MAC", NULL, 0, 0xF7},
 273 };
 274
 275 static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
 276         {"DUMP", NULL, 0, 0xDD},
 277 };
 278
 279 struct mwifiex_pcie_device {
 280         const struct mwifiex_pcie_card_reg *reg;
 281         u16 blksz_fw_dl;
 282         u16 tx_buf_size;
 283         bool can_dump_fw;
 284         struct memory_type_mapping *mem_type_mapping_tbl;
 285         u8 num_mem_types;
 286         bool can_ext_scan;
 287 };
 288
 289 static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
 290         .reg            = &mwifiex_reg_8766,
 291         .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
 292         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
 293         .can_dump_fw = false,
 294         .can_ext_scan = true,
 295 };
 296
 297 static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
 298         .reg            = &mwifiex_reg_8897,
 299         .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
 300         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
 301         .can_dump_fw = true,
 302         .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
 303         .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
 304         .can_ext_scan = true,
 305 };
 306
 307 static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
 308         .reg            = &mwifiex_reg_8997,
 309         .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
 310         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
 311         .can_dump_fw = true,
 312         .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
 313         .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
 314         .can_ext_scan = true,
 315 };
 316
 317 struct mwifiex_evt_buf_desc {
 318         u64 paddr;
 319         u16 len;
 320         u16 flags;
 321 } __packed;
 322
 323 struct mwifiex_pcie_buf_desc {
 324         u64 paddr;
 325         u16 len;
 326         u16 flags;
 327 } __packed;
 328
 329 struct mwifiex_pfu_buf_desc {
 330         u16 flags;
 331         u16 offset;
 332         u16 frag_len;
 333         u16 len;
 334         u64 paddr;
 335         u32 reserved;
 336 } __packed;
 337
 338 #define MWIFIEX_NUM_MSIX_VECTORS   4
 339
 340 struct mwifiex_msix_context {
 341         struct pci_dev *dev;
 342         u16 msg_id;
 343 };
 344
 345 struct pcie_service_card {
 346         struct pci_dev *dev;
 347         struct mwifiex_adapter *adapter;
 348         struct mwifiex_pcie_device pcie;
 349
 350         u8 txbd_flush;
 351         u32 txbd_wrptr;
 352         u32 txbd_rdptr;
 353         u32 txbd_ring_size;
 354         u8 *txbd_ring_vbase;
 355         dma_addr_t txbd_ring_pbase;
 356         void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
 357         struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
 358
 359         u32 rxbd_wrptr;
 360         u32 rxbd_rdptr;
 361         u32 rxbd_ring_size;
 362         u8 *rxbd_ring_vbase;
 363         dma_addr_t rxbd_ring_pbase;
 364         void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
 365         struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
 366
 367         u32 evtbd_wrptr;
 368         u32 evtbd_rdptr;
 369         u32 evtbd_ring_size;
 370         u8 *evtbd_ring_vbase;
 371         dma_addr_t evtbd_ring_pbase;
 372         void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
 373         struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
 374
 375         struct sk_buff *cmd_buf;
 376         struct sk_buff *cmdrsp_buf;
 377         u8 *sleep_cookie_vbase;
 378         dma_addr_t sleep_cookie_pbase;
 379         void __iomem *pci_mmap;
 380         void __iomem *pci_mmap1;
 381         int msi_enable;
 382         int msix_enable;
 383 #ifdef CONFIG_PCI
 384         struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
 385 #endif
 386         struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
 387         struct mwifiex_msix_context share_irq_ctx;
 388 };
 389
 390 static inline int
 391 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
 392 {
 393         const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
 394
 395         switch (card->dev->device) {
 396         case PCIE_DEVICE_ID_MARVELL_88W8766P:
 397                 if (((card->txbd_wrptr & reg->tx_mask) ==
 398                      (rdptr & reg->tx_mask)) &&
 399                     ((card->txbd_wrptr & reg->tx_rollover_ind) !=
 400                      (rdptr & reg->tx_rollover_ind)))
 401                         return 1;
 402                 break;
 403         case PCIE_DEVICE_ID_MARVELL_88W8897:
 404         case PCIE_DEVICE_ID_MARVELL_88W8997:
 405                 if (((card->txbd_wrptr & reg->tx_mask) ==
 406                      (rdptr & reg->tx_mask)) &&
 407                     ((card->txbd_wrptr & reg->tx_rollover_ind) ==
 408                         (rdptr & reg->tx_rollover_ind)))
 409                         return 1;
 410                 break;
 411         }
 412
 413         return 0;
 414 }
 415
 416 static inline int
 417 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
 418 {
 419         const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
 420
 421         switch (card->dev->device) {
 422         case PCIE_DEVICE_ID_MARVELL_88W8766P:
 423                 if (((card->txbd_wrptr & reg->tx_mask) !=
 424                      (card->txbd_rdptr & reg->tx_mask)) ||
 425                     ((card->txbd_wrptr & reg->tx_rollover_ind) !=
 426                      (card->txbd_rdptr & reg->tx_rollover_ind)))
 427                         return 1;
 428                 break;
 429         case PCIE_DEVICE_ID_MARVELL_88W8897:
 430         case PCIE_DEVICE_ID_MARVELL_88W8997:
 431                 if (((card->txbd_wrptr & reg->tx_mask) !=
 432                      (card->txbd_rdptr & reg->tx_mask)) ||
 433                     ((card->txbd_wrptr & reg->tx_rollover_ind) ==
 434                      (card->txbd_rdptr & reg->tx_rollover_ind)))
 435                         return 1;
 436                 break;
 437         }
 438
 439         return 0;
 440 }
 441
 442 #endif /* _MWIFIEX_PCIE_H */