arch/sh/mm/tlb-sh4.c

   1 /*
   2  * arch/sh/mm/tlb-sh4.c
   3  *
   4  * SH-4 specific TLB operations
   5  *
   6  * Copyright (C) 1999  Niibe Yutaka
   7  * Copyright (C) 2002 - 2007 Paul Mundt
   8  *
   9  * Released under the terms of the GNU GPL v2.0.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/io.h>
  14 #include <asm/system.h>
  15 #include <asm/mmu_context.h>
  16 #include <asm/cacheflush.h>
  17
  18 void update_mmu_cache(struct vm_area_struct * vma,
  19                       unsigned long address, pte_t pte)
  20 {
  21         unsigned long flags;
  22         unsigned long pteval;
  23         unsigned long vpn;
  24
  25         /* Ptrace may call this routine. */
  26         if (vma && current->active_mm != vma->vm_mm)
  27                 return;
  28
  29 #ifndef CONFIG_CACHE_OFF
  30         {
  31                 unsigned long pfn = pte_pfn(pte);
  32
  33                 if (pfn_valid(pfn)) {
  34                         struct page *page = pfn_to_page(pfn);
  35
  36                         if (!test_bit(PG_mapped, &page->flags)) {
  37                                 unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
  38                                 __flush_wback_region((void *)P1SEGADDR(phys),
  39                                                      PAGE_SIZE);
  40                                 __set_bit(PG_mapped, &page->flags);
  41                         }
  42                 }
  43         }
  44 #endif
  45
  46         local_irq_save(flags);
  47
  48         /* Set PTEH register */
  49         vpn = (address & MMU_VPN_MASK) | get_asid();
  50         ctrl_outl(vpn, MMU_PTEH);
  51
  52         pteval = pte.pte_low;
  53
  54         /* Set PTEA register */
  55 #ifdef CONFIG_X2TLB
  56         /*
  57          * For the extended mode TLB this is trivial, only the ESZ and
  58          * EPR bits need to be written out to PTEA, with the remainder of
  59          * the protection bits (with the exception of the compat-mode SZ
  60          * and PR bits, which are cleared) being written out in PTEL.
  61          */
  62         ctrl_outl(pte.pte_high, MMU_PTEA);
  63 #else
  64         if (cpu_data->flags & CPU_HAS_PTEA)
  65                 /* TODO: make this look less hacky */
  66                 ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
  67 #endif
  68
  69         /* Set PTEL register */
  70         pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
  71 #ifdef CONFIG_CACHE_WRITETHROUGH
  72         pteval |= _PAGE_WT;
  73 #endif
  74         /* conveniently, we want all the software flags to be 0 anyway */
  75         ctrl_outl(pteval, MMU_PTEL);
  76
  77         /* Load the TLB */
  78         asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
  79         local_irq_restore(flags);
  80 }
  81
  82 void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
  83                                                  unsigned long page)
  84 {
  85         unsigned long addr, data;
  86
  87         /*
  88          * NOTE: PTEH.ASID should be set to this MM
  89          *       _AND_ we need to write ASID to the array.
  90          *
  91          * It would be simple if we didn't need to set PTEH.ASID...
  92          */
  93         addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
  94         data = page | asid; /* VALID bit is off */
  95         jump_to_uncached();
  96         ctrl_outl(data, addr);
  97         back_to_cached();
  98 }