net/mlx4_en: Move filters cleanup to a proper location
[linux/fpc-iii.git] / drivers / net / phy / lxt.c
blobb9fde1bcf0f0c302ed79d97c6a717d5f1ddfe7fe
1 /*
2 * drivers/net/phy/lxt.c
4 * Driver for Intel LXT PHYs
6 * Author: Andy Fleming
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/string.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/interrupt.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/skbuff.h>
26 #include <linux/spinlock.h>
27 #include <linux/mm.h>
28 #include <linux/module.h>
29 #include <linux/mii.h>
30 #include <linux/ethtool.h>
31 #include <linux/phy.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35 #include <asm/uaccess.h>
37 /* The Level one LXT970 is used by many boards */
39 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
41 #define MII_LXT970_IER_IEN 0x0002
43 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
45 #define MII_LXT970_CONFIG 19 /* Configuration Register */
47 /* ------------------------------------------------------------------------- */
48 /* The Level one LXT971 is used on some of my custom boards */
50 /* register definitions for the 971 */
51 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
52 #define MII_LXT971_IER_IEN 0x00f2
54 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
56 /* register definitions for the 973 */
57 #define MII_LXT973_PCR 16 /* Port Configuration Register */
58 #define PCR_FIBER_SELECT 1
60 MODULE_DESCRIPTION("Intel LXT PHY driver");
61 MODULE_AUTHOR("Andy Fleming");
62 MODULE_LICENSE("GPL");
64 static int lxt970_ack_interrupt(struct phy_device *phydev)
66 int err;
68 err = phy_read(phydev, MII_BMSR);
70 if (err < 0)
71 return err;
73 err = phy_read(phydev, MII_LXT970_ISR);
75 if (err < 0)
76 return err;
78 return 0;
81 static int lxt970_config_intr(struct phy_device *phydev)
83 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
84 return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
85 else
86 return phy_write(phydev, MII_LXT970_IER, 0);
89 static int lxt970_config_init(struct phy_device *phydev)
91 return phy_write(phydev, MII_LXT970_CONFIG, 0);
95 static int lxt971_ack_interrupt(struct phy_device *phydev)
97 int err = phy_read(phydev, MII_LXT971_ISR);
99 if (err < 0)
100 return err;
102 return 0;
105 static int lxt971_config_intr(struct phy_device *phydev)
107 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
108 return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
109 else
110 return phy_write(phydev, MII_LXT971_IER, 0);
114 * A2 version of LXT973 chip has an ERRATA: it randomly return the contents
115 * of the previous even register when you read a odd register regularly
118 static int lxt973a2_update_link(struct phy_device *phydev)
120 int status;
121 int control;
122 int retry = 8; /* we try 8 times */
124 /* Do a fake read */
125 status = phy_read(phydev, MII_BMSR);
127 if (status < 0)
128 return status;
130 control = phy_read(phydev, MII_BMCR);
131 if (control < 0)
132 return control;
134 do {
135 /* Read link and autonegotiation status */
136 status = phy_read(phydev, MII_BMSR);
137 } while (status >= 0 && retry-- && status == control);
139 if (status < 0)
140 return status;
142 if ((status & BMSR_LSTATUS) == 0)
143 phydev->link = 0;
144 else
145 phydev->link = 1;
147 return 0;
150 static int lxt973a2_read_status(struct phy_device *phydev)
152 int adv;
153 int err;
154 int lpa;
155 int lpagb = 0;
157 /* Update the link, but return if there was an error */
158 err = lxt973a2_update_link(phydev);
159 if (err)
160 return err;
162 if (AUTONEG_ENABLE == phydev->autoneg) {
163 int retry = 1;
165 adv = phy_read(phydev, MII_ADVERTISE);
167 if (adv < 0)
168 return adv;
170 do {
171 lpa = phy_read(phydev, MII_LPA);
173 if (lpa < 0)
174 return lpa;
176 /* If both registers are equal, it is suspect but not
177 * impossible, hence a new try
179 } while (lpa == adv && retry--);
181 lpa &= adv;
183 phydev->speed = SPEED_10;
184 phydev->duplex = DUPLEX_HALF;
185 phydev->pause = phydev->asym_pause = 0;
187 if (lpagb & (LPA_1000FULL | LPA_1000HALF)) {
188 phydev->speed = SPEED_1000;
190 if (lpagb & LPA_1000FULL)
191 phydev->duplex = DUPLEX_FULL;
192 } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
193 phydev->speed = SPEED_100;
195 if (lpa & LPA_100FULL)
196 phydev->duplex = DUPLEX_FULL;
197 } else {
198 if (lpa & LPA_10FULL)
199 phydev->duplex = DUPLEX_FULL;
202 if (phydev->duplex == DUPLEX_FULL) {
203 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
204 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
206 } else {
207 int bmcr = phy_read(phydev, MII_BMCR);
209 if (bmcr < 0)
210 return bmcr;
212 if (bmcr & BMCR_FULLDPLX)
213 phydev->duplex = DUPLEX_FULL;
214 else
215 phydev->duplex = DUPLEX_HALF;
217 if (bmcr & BMCR_SPEED1000)
218 phydev->speed = SPEED_1000;
219 else if (bmcr & BMCR_SPEED100)
220 phydev->speed = SPEED_100;
221 else
222 phydev->speed = SPEED_10;
224 phydev->pause = phydev->asym_pause = 0;
227 return 0;
230 static int lxt973_probe(struct phy_device *phydev)
232 int val = phy_read(phydev, MII_LXT973_PCR);
234 if (val & PCR_FIBER_SELECT) {
236 * If fiber is selected, then the only correct setting
237 * is 100Mbps, full duplex, and auto negotiation off.
239 val = phy_read(phydev, MII_BMCR);
240 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
241 val &= ~BMCR_ANENABLE;
242 phy_write(phydev, MII_BMCR, val);
243 /* Remember that the port is in fiber mode. */
244 phydev->priv = lxt973_probe;
245 } else {
246 phydev->priv = NULL;
248 return 0;
251 static int lxt973_config_aneg(struct phy_device *phydev)
253 /* Do nothing if port is in fiber mode. */
254 return phydev->priv ? 0 : genphy_config_aneg(phydev);
257 static struct phy_driver lxt97x_driver[] = {
259 .phy_id = 0x78100000,
260 .name = "LXT970",
261 .phy_id_mask = 0xfffffff0,
262 .features = PHY_BASIC_FEATURES,
263 .flags = PHY_HAS_INTERRUPT,
264 .config_init = lxt970_config_init,
265 .config_aneg = genphy_config_aneg,
266 .read_status = genphy_read_status,
267 .ack_interrupt = lxt970_ack_interrupt,
268 .config_intr = lxt970_config_intr,
269 }, {
270 .phy_id = 0x001378e0,
271 .name = "LXT971",
272 .phy_id_mask = 0xfffffff0,
273 .features = PHY_BASIC_FEATURES,
274 .flags = PHY_HAS_INTERRUPT,
275 .config_aneg = genphy_config_aneg,
276 .read_status = genphy_read_status,
277 .ack_interrupt = lxt971_ack_interrupt,
278 .config_intr = lxt971_config_intr,
279 }, {
280 .phy_id = 0x00137a10,
281 .name = "LXT973-A2",
282 .phy_id_mask = 0xffffffff,
283 .features = PHY_BASIC_FEATURES,
284 .flags = 0,
285 .probe = lxt973_probe,
286 .config_aneg = lxt973_config_aneg,
287 .read_status = lxt973a2_read_status,
288 }, {
289 .phy_id = 0x00137a10,
290 .name = "LXT973",
291 .phy_id_mask = 0xfffffff0,
292 .features = PHY_BASIC_FEATURES,
293 .flags = 0,
294 .probe = lxt973_probe,
295 .config_aneg = lxt973_config_aneg,
296 .read_status = genphy_read_status,
297 } };
299 module_phy_driver(lxt97x_driver);
301 static struct mdio_device_id __maybe_unused lxt_tbl[] = {
302 { 0x78100000, 0xfffffff0 },
303 { 0x001378e0, 0xfffffff0 },
304 { 0x00137a10, 0xfffffff0 },
308 MODULE_DEVICE_TABLE(mdio, lxt_tbl);