drivers/clk/mxs/clk-imx23.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk/mxs.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/err.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include "clk.h"
  22
  23 static void __iomem *clkctrl;
  24 static void __iomem *digctrl;
  25
  26 #define CLKCTRL clkctrl
  27 #define DIGCTRL digctrl
  28
  29 #define PLLCTRL0                (CLKCTRL + 0x0000)
  30 #define CPU                     (CLKCTRL + 0x0020)
  31 #define HBUS                    (CLKCTRL + 0x0030)
  32 #define XBUS                    (CLKCTRL + 0x0040)
  33 #define XTAL                    (CLKCTRL + 0x0050)
  34 #define PIX                     (CLKCTRL + 0x0060)
  35 #define SSP                     (CLKCTRL + 0x0070)
  36 #define GPMI                    (CLKCTRL + 0x0080)
  37 #define SPDIF                   (CLKCTRL + 0x0090)
  38 #define EMI                     (CLKCTRL + 0x00a0)
  39 #define SAIF                    (CLKCTRL + 0x00c0)
  40 #define TV                      (CLKCTRL + 0x00d0)
  41 #define ETM                     (CLKCTRL + 0x00e0)
  42 #define FRAC                    (CLKCTRL + 0x00f0)
  43 #define CLKSEQ                  (CLKCTRL + 0x0110)
  44
  45 #define BP_CPU_INTERRUPT_WAIT   12
  46 #define BP_CLKSEQ_BYPASS_SAIF   0
  47 #define BP_CLKSEQ_BYPASS_SSP    5
  48 #define BP_SAIF_DIV_FRAC_EN     16
  49 #define BP_FRAC_IOFRAC          24
  50
  51 static void __init clk_misc_init(void)
  52 {
  53         u32 val;
  54
  55         /* Gate off cpu clock in WFI for power saving */
  56         writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
  57
  58         /* Clear BYPASS for SAIF */
  59         writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
  60
  61         /* SAIF has to use frac div for functional operation */
  62         val = readl_relaxed(SAIF);
  63         val |= 1 << BP_SAIF_DIV_FRAC_EN;
  64         writel_relaxed(val, SAIF);
  65
  66         /*
  67          * Source ssp clock from ref_io than ref_xtal,
  68          * as ref_xtal only provides 24 MHz as maximum.
  69          */
  70         writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
  71
  72         /*
  73          * 480 MHz seems too high to be ssp clock source directly,
  74          * so set frac to get a 288 MHz ref_io.
  75          */
  76         writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
  77         writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
  78 }
  79
  80 static const char *const sel_pll[]  __initconst = { "pll", "ref_xtal", };
  81 static const char *const sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
  82 static const char *const sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
  83 static const char *const sel_io[]   __initconst = { "ref_io", "ref_xtal", };
  84 static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
  85 static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
  86
  87 enum imx23_clk {
  88         ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,
  89         lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll,
  90         cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
  91         emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
  92         clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
  93         lcdif, etm, usb, usb_phy,
  94         clk_max
  95 };
  96
  97 static struct clk *clks[clk_max];
  98 static struct clk_onecell_data clk_data;
  99
 100 static enum imx23_clk clks_init_on[] __initdata = {
 101         cpu, hbus, xbus, emi, uart,
 102 };
 103
 104 static void __init mx23_clocks_init(struct device_node *np)
 105 {
 106         struct device_node *dcnp;
 107         u32 i;
 108
 109         dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
 110         digctrl = of_iomap(dcnp, 0);
 111         WARN_ON(!digctrl);
 112         of_node_put(dcnp);
 113
 114         clkctrl = of_iomap(np, 0);
 115         WARN_ON(!clkctrl);
 116
 117         clk_misc_init();
 118
 119         clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
 120         clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
 121         clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
 122         clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
 123         clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
 124         clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
 125         clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
 126         clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
 127         clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io));
 128         clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io));
 129         clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels));
 130         clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
 131         clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
 132         clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
 133         clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
 134         clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29);
 135         clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
 136         clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29);
 137         clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);
 138         clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
 139         clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
 140         clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
 141         clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29);
 142         clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29);
 143         clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
 144         clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
 145         clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16);
 146         clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4);
 147         clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
 148         clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28);
 149         clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
 150         clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30);
 151         clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
 152         clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31);
 153         clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
 154         clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
 155         clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
 156         clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
 157         clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
 158         clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
 159         clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2);
 160         clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
 161
 162         for (i = 0; i < ARRAY_SIZE(clks); i++)
 163                 if (IS_ERR(clks[i])) {
 164                         pr_err("i.MX23 clk %d: register failed with %ld\n",
 165                                 i, PTR_ERR(clks[i]));
 166                         return;
 167                 }
 168
 169         clk_data.clks = clks;
 170         clk_data.clk_num = ARRAY_SIZE(clks);
 171         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 172
 173         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 174                 clk_prepare_enable(clks[clks_init_on[i]]);
 175
 176 }
 177 CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init);