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visorbus: switch from ioremap_cache to memremap
[linux/fpc-iii.git] / drivers / clk / samsung / clk-exynos5260.c
blob06f96eb7cf93c5b4c7d946d41b57b30078042db2
1 /*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Rahul Sharma <rahul.sharma@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5260 SoC.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16
17 #include "clk-exynos5260.h"
18 #include "clk.h"
19 #include "clk-pll.h"
20
21 #include <dt-bindings/clock/exynos5260-clk.h>
22
23 /*
24 * Applicable for all 2550 Type PLLS for Exynos5260, listed below
25 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
26 */
27 static struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initdata = {
28 PLL_35XX_RATE(1700000000, 425, 6, 0),
29 PLL_35XX_RATE(1600000000, 200, 3, 0),
30 PLL_35XX_RATE(1500000000, 250, 4, 0),
31 PLL_35XX_RATE(1400000000, 175, 3, 0),
32 PLL_35XX_RATE(1300000000, 325, 6, 0),
33 PLL_35XX_RATE(1200000000, 400, 4, 1),
34 PLL_35XX_RATE(1100000000, 275, 3, 1),
35 PLL_35XX_RATE(1000000000, 250, 3, 1),
36 PLL_35XX_RATE(933000000, 311, 4, 1),
37 PLL_35XX_RATE(900000000, 300, 4, 1),
38 PLL_35XX_RATE(800000000, 200, 3, 1),
39 PLL_35XX_RATE(733000000, 733, 12, 1),
40 PLL_35XX_RATE(700000000, 175, 3, 1),
41 PLL_35XX_RATE(667000000, 667, 12, 1),
42 PLL_35XX_RATE(633000000, 211, 4, 1),
43 PLL_35XX_RATE(620000000, 310, 3, 2),
44 PLL_35XX_RATE(600000000, 400, 4, 2),
45 PLL_35XX_RATE(543000000, 362, 4, 2),
46 PLL_35XX_RATE(533000000, 533, 6, 2),
47 PLL_35XX_RATE(500000000, 250, 3, 2),
48 PLL_35XX_RATE(450000000, 300, 4, 2),
49 PLL_35XX_RATE(400000000, 200, 3, 2),
50 PLL_35XX_RATE(350000000, 175, 3, 2),
51 PLL_35XX_RATE(300000000, 400, 4, 3),
52 PLL_35XX_RATE(266000000, 266, 3, 3),
53 PLL_35XX_RATE(200000000, 200, 3, 3),
54 PLL_35XX_RATE(160000000, 160, 3, 3),
55 };
56
57 /*
58 * Applicable for 2650 Type PLL for AUD_PLL.
59 */
60 static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = {
61 PLL_36XX_RATE(1600000000, 200, 3, 0, 0),
62 PLL_36XX_RATE(1200000000, 100, 2, 0, 0),
63 PLL_36XX_RATE(1000000000, 250, 3, 1, 0),
64 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
65 PLL_36XX_RATE(600000000, 100, 2, 1, 0),
66 PLL_36XX_RATE(532000000, 266, 3, 2, 0),
67 PLL_36XX_RATE(480000000, 160, 2, 2, 0),
68 PLL_36XX_RATE(432000000, 144, 2, 2, 0),
69 PLL_36XX_RATE(400000000, 200, 3, 2, 0),
70 PLL_36XX_RATE(394073130, 459, 7, 2, 49282),
71 PLL_36XX_RATE(333000000, 111, 2, 2, 0),
72 PLL_36XX_RATE(300000000, 100, 2, 2, 0),
73 PLL_36XX_RATE(266000000, 266, 3, 3, 0),
74 PLL_36XX_RATE(200000000, 200, 3, 3, 0),
75 PLL_36XX_RATE(166000000, 166, 3, 3, 0),
76 PLL_36XX_RATE(133000000, 266, 3, 4, 0),
77 PLL_36XX_RATE(100000000, 200, 3, 4, 0),
78 PLL_36XX_RATE(66000000, 176, 2, 5, 0),
79 };
80
81 /* CMU_AUD */
82
83 static unsigned long aud_clk_regs[] __initdata = {
84 MUX_SEL_AUD,
85 DIV_AUD0,
86 DIV_AUD1,
87 EN_ACLK_AUD,
88 EN_PCLK_AUD,
89 EN_SCLK_AUD,
90 EN_IP_AUD,
91 };
92
93 PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
94 PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
95 PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
96
97 static struct samsung_mux_clock aud_mux_clks[] __initdata = {
98 MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
99 MUX_SEL_AUD, 0, 1),
100 MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
101 MUX_SEL_AUD, 4, 1),
102 MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
103 MUX_SEL_AUD, 8, 1),
104 };
105
106 static struct samsung_div_clock aud_div_clks[] __initdata = {
107 DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user",
108 DIV_AUD0, 0, 4),
109
110 DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
111 DIV_AUD1, 0, 4),
112 DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
113 DIV_AUD1, 4, 8),
114 DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user",
115 DIV_AUD1, 12, 4),
116 };
117
118 static struct samsung_gate_clock aud_gate_clks[] __initdata = {
119 GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
120 EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
121 GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
122 EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
123 GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
124 EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
125
126 GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD,
127 0, 0, 0),
128 GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
129 EN_IP_AUD, 1, 0, 0),
130 GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
131 GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
132 GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
133 EN_IP_AUD, 4, 0, 0),
134 };
135
136 static void __init exynos5260_clk_aud_init(struct device_node *np)
137 {
138 struct samsung_cmu_info cmu = { NULL };
139
140 cmu.mux_clks = aud_mux_clks;
141 cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);
142 cmu.div_clks = aud_div_clks;
143 cmu.nr_div_clks = ARRAY_SIZE(aud_div_clks);
144 cmu.gate_clks = aud_gate_clks;
145 cmu.nr_gate_clks = ARRAY_SIZE(aud_gate_clks);
146 cmu.nr_clk_ids = AUD_NR_CLK;
147 cmu.clk_regs = aud_clk_regs;
148 cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
149
150 samsung_cmu_register_one(np, &cmu);
151 }
152
153 CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
154 exynos5260_clk_aud_init);
155
156
157 /* CMU_DISP */
158
159 static unsigned long disp_clk_regs[] __initdata = {
160 MUX_SEL_DISP0,
161 MUX_SEL_DISP1,
162 MUX_SEL_DISP2,
163 MUX_SEL_DISP3,
164 MUX_SEL_DISP4,
165 DIV_DISP,
166 EN_ACLK_DISP,
167 EN_PCLK_DISP,
168 EN_SCLK_DISP0,
169 EN_SCLK_DISP1,
170 EN_IP_DISP,
171 EN_IP_DISP_BUS,
172 };
173
174 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
175 "phyclk_dptx_phy_ch3_txd_clk"};
176 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
177 "phyclk_dptx_phy_ch2_txd_clk"};
178 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
179 "phyclk_dptx_phy_ch1_txd_clk"};
180 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
181 "phyclk_dptx_phy_ch0_txd_clk"};
182 PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
183 PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
184 PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
185 PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
186 "phyclk_hdmi_phy_tmds_clko"};
187 PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
188 "phyclk_hdmi_phy_ref_clko"};
189 PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll",
190 "phyclk_hdmi_phy_pixel_clko"};
191 PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll",
192 "phyclk_hdmi_link_o_tmds_clkhi"};
193 PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll",
194 "phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
195 PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll",
196 "phyclk_dptx_phy_o_ref_clk_24m"};
197 PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll",
198 "phyclk_dptx_phy_clk_div2"};
199 PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user",
200 "mout_aclk_disp_222_user"};
201 PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
202 "phyclk_mipi_dphy_4l_m_rxclkesc0"};
203 PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
204 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
205
206 static struct samsung_mux_clock disp_mux_clks[] __initdata = {
207 MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
208 mout_aclk_disp_333_user_p,
209 MUX_SEL_DISP0, 0, 1),
210 MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
211 mout_sclk_disp_pixel_user_p,
212 MUX_SEL_DISP0, 4, 1),
213 MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
214 mout_aclk_disp_222_user_p,
215 MUX_SEL_DISP0, 8, 1),
216 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
217 "mout_phyclk_dptx_phy_ch0_txd_clk_user",
218 mout_phyclk_dptx_phy_ch0_txd_clk_user_p,
219 MUX_SEL_DISP0, 16, 1),
220 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
221 "mout_phyclk_dptx_phy_ch1_txd_clk_user",
222 mout_phyclk_dptx_phy_ch1_txd_clk_user_p,
223 MUX_SEL_DISP0, 20, 1),
224 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
225 "mout_phyclk_dptx_phy_ch2_txd_clk_user",
226 mout_phyclk_dptx_phy_ch2_txd_clk_user_p,
227 MUX_SEL_DISP0, 24, 1),
228 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
229 "mout_phyclk_dptx_phy_ch3_txd_clk_user",
230 mout_phyclk_dptx_phy_ch3_txd_clk_user_p,
231 MUX_SEL_DISP0, 28, 1),
232
233 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER,
234 "mout_phyclk_dptx_phy_clk_div2_user",
235 mout_phyclk_dptx_phy_clk_div2_user_p,
236 MUX_SEL_DISP1, 0, 1),
237 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER,
238 "mout_phyclk_dptx_phy_o_ref_clk_24m_user",
239 mout_phyclk_dptx_phy_o_ref_clk_24m_user_p,
240 MUX_SEL_DISP1, 4, 1),
241 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS,
242 "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
243 mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p,
244 MUX_SEL_DISP1, 8, 1),
245 MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER,
246 "mout_phyclk_hdmi_link_o_tmds_clkhi_user",
247 mout_phyclk_hdmi_link_o_tmds_clkhi_user_p,
248 MUX_SEL_DISP1, 16, 1),
249 MUX(DISP_MOUT_HDMI_PHY_PIXEL,
250 "mout_phyclk_hdmi_phy_pixel_clko_user",
251 mout_phyclk_hdmi_phy_pixel_clko_user_p,
252 MUX_SEL_DISP1, 20, 1),
253 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER,
254 "mout_phyclk_hdmi_phy_ref_clko_user",
255 mout_phyclk_hdmi_phy_ref_clko_user_p,
256 MUX_SEL_DISP1, 24, 1),
257 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER,
258 "mout_phyclk_hdmi_phy_tmds_clko_user",
259 mout_phyclk_hdmi_phy_tmds_clko_user_p,
260 MUX_SEL_DISP1, 28, 1),
261
262 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER,
263 "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
264 mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p,
265 MUX_SEL_DISP2, 0, 1),
266 MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel",
267 mout_sclk_hdmi_pixel_p,
268 MUX_SEL_DISP2, 4, 1),
269
270 MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
271 mout_sclk_hdmi_spdif_p,
272 MUX_SEL_DISP4, 4, 2),
273 };
274
275 static struct samsung_div_clock disp_div_clks[] __initdata = {
276 DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111",
277 "mout_aclk_disp_222_user",
278 DIV_DISP, 8, 4),
279 DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll",
280 "mout_sclk_disp_pixel_user",
281 DIV_DISP, 12, 4),
282 DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI,
283 "dout_sclk_hdmi_phy_pixel_clki",
284 "mout_sclk_hdmi_pixel",
285 DIV_DISP, 16, 4),
286 };
287
288 static struct samsung_gate_clock disp_gate_clks[] __initdata = {
289 GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
290 "mout_phyclk_hdmi_phy_pixel_clko_user",
291 EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
292 GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
293 "dout_sclk_hdmi_phy_pixel_clki",
294 EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
295
296 GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
297 EN_IP_DISP, 4, 0, 0),
298 GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
299 EN_IP_DISP, 5, 0, 0),
300 GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
301 EN_IP_DISP, 6, 0, 0),
302 GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
303 EN_IP_DISP, 7, 0, 0),
304 GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
305 EN_IP_DISP, 8, 0, 0),
306 GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
307 EN_IP_DISP, 9, 0, 0),
308 GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
309 EN_IP_DISP, 10, 0, 0),
310 GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
311 EN_IP_DISP, 11, 0, 0),
312 GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user",
313 EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
314 GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user",
315 EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
316 GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
317 "mout_aclk_disp_222_user",
318 EN_IP_DISP, 22, 0, 0),
319 GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
320 "mout_aclk_disp_222_user",
321 EN_IP_DISP, 23, 0, 0),
322 GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
323 EN_IP_DISP, 25, 0, 0),
324 };
325
326 static void __init exynos5260_clk_disp_init(struct device_node *np)
327 {
328 struct samsung_cmu_info cmu = { NULL };
329
330 cmu.mux_clks = disp_mux_clks;
331 cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);
332 cmu.div_clks = disp_div_clks;
333 cmu.nr_div_clks = ARRAY_SIZE(disp_div_clks);
334 cmu.gate_clks = disp_gate_clks;
335 cmu.nr_gate_clks = ARRAY_SIZE(disp_gate_clks);
336 cmu.nr_clk_ids = DISP_NR_CLK;
337 cmu.clk_regs = disp_clk_regs;
338 cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
339
340 samsung_cmu_register_one(np, &cmu);
341 }
342
343 CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
344 exynos5260_clk_disp_init);
345
346
347 /* CMU_EGL */
348
349 static unsigned long egl_clk_regs[] __initdata = {
350 EGL_PLL_LOCK,
351 EGL_PLL_CON0,
352 EGL_PLL_CON1,
353 EGL_PLL_FREQ_DET,
354 MUX_SEL_EGL,
355 MUX_ENABLE_EGL,
356 DIV_EGL,
357 DIV_EGL_PLL_FDET,
358 EN_ACLK_EGL,
359 EN_PCLK_EGL,
360 EN_SCLK_EGL,
361 };
362
363 PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
364 PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
365
366 static struct samsung_mux_clock egl_mux_clks[] __initdata = {
367 MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p,
368 MUX_SEL_EGL, 4, 1),
369 MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
370 };
371
372 static struct samsung_div_clock egl_div_clks[] __initdata = {
373 DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
374 DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
375 DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
376 DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk",
377 DIV_EGL, 12, 3),
378 DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3),
379 DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk",
380 DIV_EGL, 20, 3),
381 DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
382 };
383
384 static struct samsung_pll_clock egl_pll_clks[] __initdata = {
385 PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
386 EGL_PLL_LOCK, EGL_PLL_CON0,
387 pll2550_24mhz_tbl),
388 };
389
390 static void __init exynos5260_clk_egl_init(struct device_node *np)
391 {
392 struct samsung_cmu_info cmu = { NULL };
393
394 cmu.pll_clks = egl_pll_clks;
395 cmu.nr_pll_clks = ARRAY_SIZE(egl_pll_clks);
396 cmu.mux_clks = egl_mux_clks;
397 cmu.nr_mux_clks = ARRAY_SIZE(egl_mux_clks);
398 cmu.div_clks = egl_div_clks;
399 cmu.nr_div_clks = ARRAY_SIZE(egl_div_clks);
400 cmu.nr_clk_ids = EGL_NR_CLK;
401 cmu.clk_regs = egl_clk_regs;
402 cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs);
403
404 samsung_cmu_register_one(np, &cmu);
405 }
406
407 CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
408 exynos5260_clk_egl_init);
409
410
411 /* CMU_FSYS */
412
413 static unsigned long fsys_clk_regs[] __initdata = {
414 MUX_SEL_FSYS0,
415 MUX_SEL_FSYS1,
416 EN_ACLK_FSYS,
417 EN_ACLK_FSYS_SECURE_RTIC,
418 EN_ACLK_FSYS_SECURE_SMMU_RTIC,
419 EN_SCLK_FSYS,
420 EN_IP_FSYS,
421 EN_IP_FSYS_SECURE_RTIC,
422 EN_IP_FSYS_SECURE_SMMU_RTIC,
423 };
424
425 PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll",
426 "phyclk_usbhost20_phy_phyclock"};
427 PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll",
428 "phyclk_usbhost20_phy_freeclk"};
429 PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll",
430 "phyclk_usbhost20_phy_clk48mohci"};
431 PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
432 "phyclk_usbdrd30_udrd30_pipe_pclk"};
433 PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
434 "phyclk_usbdrd30_udrd30_phyclock"};
435
436 static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
437 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
438 "mout_phyclk_usbdrd30_phyclock_user",
439 mout_phyclk_usbdrd30_phyclock_user_p,
440 MUX_SEL_FSYS1, 0, 1),
441 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER,
442 "mout_phyclk_usbdrd30_pipe_pclk_user",
443 mout_phyclk_usbdrd30_pipe_pclk_user_p,
444 MUX_SEL_FSYS1, 4, 1),
445 MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER,
446 "mout_phyclk_usbhost20_clk48mohci_user",
447 mout_phyclk_usbhost20_clk48mohci_user_p,
448 MUX_SEL_FSYS1, 8, 1),
449 MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER,
450 "mout_phyclk_usbhost20_freeclk_user",
451 mout_phyclk_usbhost20_freeclk_user_p,
452 MUX_SEL_FSYS1, 12, 1),
453 MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER,
454 "mout_phyclk_usbhost20_phyclk_user",
455 mout_phyclk_usbhost20_phyclk_user_p,
456 MUX_SEL_FSYS1, 16, 1),
457 };
458
459 static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
460 GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
461 "mout_phyclk_usbdrd30_phyclock_user",
462 EN_SCLK_FSYS, 1, 0, 0),
463 GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
464 "mout_phyclk_usbdrd30_phyclock_user",
465 EN_SCLK_FSYS, 7, 0, 0),
466
467 GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
468 EN_IP_FSYS, 6, 0, 0),
469 GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
470 EN_IP_FSYS, 7, 0, 0),
471 GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
472 EN_IP_FSYS, 8, 0, 0),
473 GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
474 EN_IP_FSYS, 9, 0, 0),
475 GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
476 EN_IP_FSYS, 13, 0, 0),
477 GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
478 EN_IP_FSYS, 14, 0, 0),
479 GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
480 EN_IP_FSYS, 15, 0, 0),
481 GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
482 EN_IP_FSYS, 18, 0, 0),
483 GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
484 EN_IP_FSYS, 20, 0, 0),
485
486 GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200",
487 EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
488 GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200",
489 EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
490 };
491
492 static void __init exynos5260_clk_fsys_init(struct device_node *np)
493 {
494 struct samsung_cmu_info cmu = { NULL };
495
496 cmu.mux_clks = fsys_mux_clks;
497 cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks);
498 cmu.gate_clks = fsys_gate_clks;
499 cmu.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks);
500 cmu.nr_clk_ids = FSYS_NR_CLK;
501 cmu.clk_regs = fsys_clk_regs;
502 cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs);
503
504 samsung_cmu_register_one(np, &cmu);
505 }
506
507 CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
508 exynos5260_clk_fsys_init);
509
510
511 /* CMU_G2D */
512
513 static unsigned long g2d_clk_regs[] __initdata = {
514 MUX_SEL_G2D,
515 MUX_STAT_G2D,
516 DIV_G2D,
517 EN_ACLK_G2D,
518 EN_ACLK_G2D_SECURE_SSS,
519 EN_ACLK_G2D_SECURE_SLIM_SSS,
520 EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS,
521 EN_ACLK_G2D_SECURE_SMMU_SSS,
522 EN_ACLK_G2D_SECURE_SMMU_MDMA,
523 EN_ACLK_G2D_SECURE_SMMU_G2D,
524 EN_PCLK_G2D,
525 EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS,
526 EN_PCLK_G2D_SECURE_SMMU_SSS,
527 EN_PCLK_G2D_SECURE_SMMU_MDMA,
528 EN_PCLK_G2D_SECURE_SMMU_G2D,
529 EN_IP_G2D,
530 EN_IP_G2D_SECURE_SSS,
531 EN_IP_G2D_SECURE_SLIM_SSS,
532 EN_IP_G2D_SECURE_SMMU_SLIM_SSS,
533 EN_IP_G2D_SECURE_SMMU_SSS,
534 EN_IP_G2D_SECURE_SMMU_MDMA,
535 EN_IP_G2D_SECURE_SMMU_G2D,
536 };
537
538 PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
539
540 static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
541 MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user",
542 mout_aclk_g2d_333_user_p,
543 MUX_SEL_G2D, 0, 1),
544 };
545
546 static struct samsung_div_clock g2d_div_clks[] __initdata = {
547 DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
548 DIV_G2D, 0, 3),
549 };
550
551 static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
552 GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
553 EN_IP_G2D, 4, 0, 0),
554 GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
555 EN_IP_G2D, 5, 0, 0),
556 GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user",
557 EN_IP_G2D, 6, 0, 0),
558 GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
559 EN_IP_G2D, 16, 0, 0),
560
561 GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user",
562 EN_IP_G2D_SECURE_SSS, 17, 0, 0),
563
564 GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user",
565 EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0),
566
567 GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss",
568 "mout_aclk_g2d_333_user",
569 EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0),
570
571 GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user",
572 EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0),
573
574 GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
575 EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0),
576
577 GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
578 EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
579 };
580
581 static void __init exynos5260_clk_g2d_init(struct device_node *np)
582 {
583 struct samsung_cmu_info cmu = { NULL };
584
585 cmu.mux_clks = g2d_mux_clks;
586 cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks);
587 cmu.div_clks = g2d_div_clks;
588 cmu.nr_div_clks = ARRAY_SIZE(g2d_div_clks);
589 cmu.gate_clks = g2d_gate_clks;
590 cmu.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks);
591 cmu.nr_clk_ids = G2D_NR_CLK;
592 cmu.clk_regs = g2d_clk_regs;
593 cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs);
594
595 samsung_cmu_register_one(np, &cmu);
596 }
597
598 CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
599 exynos5260_clk_g2d_init);
600
601
602 /* CMU_G3D */
603
604 static unsigned long g3d_clk_regs[] __initdata = {
605 G3D_PLL_LOCK,
606 G3D_PLL_CON0,
607 G3D_PLL_CON1,
608 G3D_PLL_FDET,
609 MUX_SEL_G3D,
610 DIV_G3D,
611 DIV_G3D_PLL_FDET,
612 EN_ACLK_G3D,
613 EN_PCLK_G3D,
614 EN_SCLK_G3D,
615 EN_IP_G3D,
616 };
617
618 PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
619
620 static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
621 MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
622 MUX_SEL_G3D, 0, 1),
623 };
624
625 static struct samsung_div_clock g3d_div_clks[] __initdata = {
626 DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
627 DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
628 };
629
630 static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
631 GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
632 GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
633 EN_IP_G3D, 3, 0, 0),
634 };
635
636 static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
637 PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
638 G3D_PLL_LOCK, G3D_PLL_CON0,
639 pll2550_24mhz_tbl),
640 };
641
642 static void __init exynos5260_clk_g3d_init(struct device_node *np)
643 {
644 struct samsung_cmu_info cmu = { NULL };
645
646 cmu.pll_clks = g3d_pll_clks;
647 cmu.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks);
648 cmu.mux_clks = g3d_mux_clks;
649 cmu.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks);
650 cmu.div_clks = g3d_div_clks;
651 cmu.nr_div_clks = ARRAY_SIZE(g3d_div_clks);
652 cmu.gate_clks = g3d_gate_clks;
653 cmu.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks);
654 cmu.nr_clk_ids = G3D_NR_CLK;
655 cmu.clk_regs = g3d_clk_regs;
656 cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs);
657
658 samsung_cmu_register_one(np, &cmu);
659 }
660
661 CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
662 exynos5260_clk_g3d_init);
663
664
665 /* CMU_GSCL */
666
667 static unsigned long gscl_clk_regs[] __initdata = {
668 MUX_SEL_GSCL,
669 DIV_GSCL,
670 EN_ACLK_GSCL,
671 EN_ACLK_GSCL_FIMC,
672 EN_ACLK_GSCL_SECURE_SMMU_GSCL0,
673 EN_ACLK_GSCL_SECURE_SMMU_GSCL1,
674 EN_ACLK_GSCL_SECURE_SMMU_MSCL0,
675 EN_ACLK_GSCL_SECURE_SMMU_MSCL1,
676 EN_PCLK_GSCL,
677 EN_PCLK_GSCL_FIMC,
678 EN_PCLK_GSCL_SECURE_SMMU_GSCL0,
679 EN_PCLK_GSCL_SECURE_SMMU_GSCL1,
680 EN_PCLK_GSCL_SECURE_SMMU_MSCL0,
681 EN_PCLK_GSCL_SECURE_SMMU_MSCL1,
682 EN_SCLK_GSCL,
683 EN_SCLK_GSCL_FIMC,
684 EN_IP_GSCL,
685 EN_IP_GSCL_FIMC,
686 EN_IP_GSCL_SECURE_SMMU_GSCL0,
687 EN_IP_GSCL_SECURE_SMMU_GSCL1,
688 EN_IP_GSCL_SECURE_SMMU_MSCL0,
689 EN_IP_GSCL_SECURE_SMMU_MSCL1,
690 };
691
692 PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"};
693 PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
694 PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
695 PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
696
697 static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
698 MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
699 mout_aclk_gscl_333_user_p,
700 MUX_SEL_GSCL, 0, 1),
701 MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user",
702 mout_aclk_m2m_400_user_p,
703 MUX_SEL_GSCL, 4, 1),
704 MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user",
705 mout_aclk_gscl_fimc_user_p,
706 MUX_SEL_GSCL, 8, 1),
707 MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p,
708 MUX_SEL_GSCL, 24, 1),
709 };
710
711 static struct samsung_div_clock gscl_div_clks[] __initdata = {
712 DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100",
713 "mout_aclk_m2m_400_user",
714 DIV_GSCL, 0, 3),
715 DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200",
716 "mout_aclk_m2m_400_user",
717 DIV_GSCL, 4, 3),
718 };
719
720 static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
721 GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
722 EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
723 GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
724 EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
725
726 GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user",
727 EN_IP_GSCL, 2, 0, 0),
728 GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user",
729 EN_IP_GSCL, 3, 0, 0),
730 GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user",
731 EN_IP_GSCL, 4, 0, 0),
732 GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user",
733 EN_IP_GSCL, 5, 0, 0),
734 GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",
735 "mout_aclk_gscl_333_user",
736 EN_IP_GSCL, 8, 0, 0),
737 GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",
738 "mout_aclk_gscl_333_user",
739 EN_IP_GSCL, 9, 0, 0),
740
741 GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
742 "mout_aclk_gscl_fimc_user",
743 EN_IP_GSCL_FIMC, 5, 0, 0),
744 GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
745 "mout_aclk_gscl_fimc_user",
746 EN_IP_GSCL_FIMC, 6, 0, 0),
747 GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
748 "mout_aclk_gscl_fimc_user",
749 EN_IP_GSCL_FIMC, 7, 0, 0),
750 GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
751 EN_IP_GSCL_FIMC, 8, 0, 0),
752 GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
753 EN_IP_GSCL_FIMC, 9, 0, 0),
754 GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
755 "mout_aclk_gscl_fimc_user",
756 EN_IP_GSCL_FIMC, 10, 0, 0),
757 GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
758 "mout_aclk_gscl_fimc_user",
759 EN_IP_GSCL_FIMC, 11, 0, 0),
760 GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
761 "mout_aclk_gscl_fimc_user",
762 EN_IP_GSCL_FIMC, 12, 0, 0),
763
764 GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
765 "mout_aclk_gscl_333_user",
766 EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
767 GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user",
768 EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
769 GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
770 "mout_aclk_m2m_400_user",
771 EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
772 GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
773 "mout_aclk_m2m_400_user",
774 EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
775 };
776
777 static void __init exynos5260_clk_gscl_init(struct device_node *np)
778 {
779 struct samsung_cmu_info cmu = { NULL };
780
781 cmu.mux_clks = gscl_mux_clks;
782 cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks);
783 cmu.div_clks = gscl_div_clks;
784 cmu.nr_div_clks = ARRAY_SIZE(gscl_div_clks);
785 cmu.gate_clks = gscl_gate_clks;
786 cmu.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks);
787 cmu.nr_clk_ids = GSCL_NR_CLK;
788 cmu.clk_regs = gscl_clk_regs;
789 cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs);
790
791 samsung_cmu_register_one(np, &cmu);
792 }
793
794 CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
795 exynos5260_clk_gscl_init);
796
797
798 /* CMU_ISP */
799
800 static unsigned long isp_clk_regs[] __initdata = {
801 MUX_SEL_ISP0,
802 MUX_SEL_ISP1,
803 DIV_ISP,
804 EN_ACLK_ISP0,
805 EN_ACLK_ISP1,
806 EN_PCLK_ISP0,
807 EN_PCLK_ISP1,
808 EN_SCLK_ISP,
809 EN_IP_ISP0,
810 EN_IP_ISP1,
811 };
812
813 PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
814 PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"};
815
816 static struct samsung_mux_clock isp_mux_clks[] __initdata = {
817 MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p,
818 MUX_SEL_ISP0, 0, 1),
819 MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p,
820 MUX_SEL_ISP0, 4, 1),
821 };
822
823 static struct samsung_div_clock isp_div_clks[] __initdata = {
824 DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc",
825 DIV_ISP, 0, 3),
826 DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc",
827 DIV_ISP, 4, 4),
828 DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc",
829 DIV_ISP, 12, 3),
830 DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc",
831 DIV_ISP, 16, 4),
832 DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
833 };
834
835 static struct samsung_gate_clock isp_gate_clks[] __initdata = {
836 GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
837 EN_IP_ISP0, 15, 0, 0),
838
839 GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
840 EN_IP_ISP1, 1, 0, 0),
841 GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
842 EN_IP_ISP1, 2, 0, 0),
843 GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
844 EN_IP_ISP1, 3, 0, 0),
845 GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
846 EN_IP_ISP1, 4, 0, 0),
847 GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
848 "mout_aclk_isp1_266",
849 EN_IP_ISP1, 5, 0, 0),
850 GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
851 "mout_aclk_isp1_266",
852 EN_IP_ISP1, 6, 0, 0),
853 GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
854 EN_IP_ISP1, 7, 0, 0),
855 GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
856 EN_IP_ISP1, 8, 0, 0),
857 GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
858 EN_IP_ISP1, 9, 0, 0),
859 GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
860 EN_IP_ISP1, 10, 0, 0),
861 GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
862 EN_IP_ISP1, 11, 0, 0),
863 GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
864 EN_IP_ISP1, 14, 0, 0),
865 GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
866 EN_IP_ISP1, 21, 0, 0),
867 GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
868 EN_IP_ISP1, 22, 0, 0),
869 GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
870 EN_IP_ISP1, 23, 0, 0),
871 GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
872 EN_IP_ISP1, 24, 0, 0),
873 GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
874 "mout_aclk_isp1_266",
875 EN_IP_ISP1, 25, 0, 0),
876 GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
877 "mout_aclk_isp1_266",
878 EN_IP_ISP1, 26, 0, 0),
879 GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
880 EN_IP_ISP1, 27, 0, 0),
881 GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
882 EN_IP_ISP1, 28, 0, 0),
883 GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
884 EN_IP_ISP1, 31, 0, 0),
885 GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
886 EN_IP_ISP1, 30, 0, 0),
887
888 GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
889 EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
890 GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
891 EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
892 GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
893 EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
894 };
895
896 static void __init exynos5260_clk_isp_init(struct device_node *np)
897 {
898 struct samsung_cmu_info cmu = { NULL };
899
900 cmu.mux_clks = isp_mux_clks;
901 cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks);
902 cmu.div_clks = isp_div_clks;
903 cmu.nr_div_clks = ARRAY_SIZE(isp_div_clks);
904 cmu.gate_clks = isp_gate_clks;
905 cmu.nr_gate_clks = ARRAY_SIZE(isp_gate_clks);
906 cmu.nr_clk_ids = ISP_NR_CLK;
907 cmu.clk_regs = isp_clk_regs;
908 cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs);
909
910 samsung_cmu_register_one(np, &cmu);
911 }
912
913 CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
914 exynos5260_clk_isp_init);
915
916
917 /* CMU_KFC */
918
919 static unsigned long kfc_clk_regs[] __initdata = {
920 KFC_PLL_LOCK,
921 KFC_PLL_CON0,
922 KFC_PLL_CON1,
923 KFC_PLL_FDET,
924 MUX_SEL_KFC0,
925 MUX_SEL_KFC2,
926 DIV_KFC,
927 DIV_KFC_PLL_FDET,
928 EN_ACLK_KFC,
929 EN_PCLK_KFC,
930 EN_SCLK_KFC,
931 EN_IP_KFC,
932 };
933
934 PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
935 PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"};
936
937 static struct samsung_mux_clock kfc_mux_clks[] __initdata = {
938 MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p,
939 MUX_SEL_KFC0, 0, 1),
940 MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
941 };
942
943 static struct samsung_div_clock kfc_div_clks[] __initdata = {
944 DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
945 DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
946 DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
947 DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2",
948 DIV_KFC, 12, 3),
949 DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3),
950 DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3),
951 DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
952 };
953
954 static struct samsung_pll_clock kfc_pll_clks[] __initdata = {
955 PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
956 KFC_PLL_LOCK, KFC_PLL_CON0,
957 pll2550_24mhz_tbl),
958 };
959
960 static void __init exynos5260_clk_kfc_init(struct device_node *np)
961 {
962 struct samsung_cmu_info cmu = { NULL };
963
964 cmu.pll_clks = kfc_pll_clks;
965 cmu.nr_pll_clks = ARRAY_SIZE(kfc_pll_clks);
966 cmu.mux_clks = kfc_mux_clks;
967 cmu.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks);
968 cmu.div_clks = kfc_div_clks;
969 cmu.nr_div_clks = ARRAY_SIZE(kfc_div_clks);
970 cmu.nr_clk_ids = KFC_NR_CLK;
971 cmu.clk_regs = kfc_clk_regs;
972 cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs);
973
974 samsung_cmu_register_one(np, &cmu);
975 }
976
977 CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
978 exynos5260_clk_kfc_init);
979
980
981 /* CMU_MFC */
982
983 static unsigned long mfc_clk_regs[] __initdata = {
984 MUX_SEL_MFC,
985 DIV_MFC,
986 EN_ACLK_MFC,
987 EN_ACLK_SECURE_SMMU2_MFC,
988 EN_PCLK_MFC,
989 EN_PCLK_SECURE_SMMU2_MFC,
990 EN_IP_MFC,
991 EN_IP_MFC_SECURE_SMMU2_MFC,
992 };
993
994 PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
995
996 static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
997 MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user",
998 mout_aclk_mfc_333_user_p,
999 MUX_SEL_MFC, 0, 1),
1000 };
1001
1002 static struct samsung_div_clock mfc_div_clks[] __initdata = {
1003 DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
1004 DIV_MFC, 0, 3),
1005 };
1006
1007 static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
1008 GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
1009 EN_IP_MFC, 1, 0, 0),
1010 GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
1011 EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0),
1012 GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
1013 EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
1014 };
1015
1016 static void __init exynos5260_clk_mfc_init(struct device_node *np)
1017 {
1018 struct samsung_cmu_info cmu = { NULL };
1019
1020 cmu.mux_clks = mfc_mux_clks;
1021 cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks);
1022 cmu.div_clks = mfc_div_clks;
1023 cmu.nr_div_clks = ARRAY_SIZE(mfc_div_clks);
1024 cmu.gate_clks = mfc_gate_clks;
1025 cmu.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks);
1026 cmu.nr_clk_ids = MFC_NR_CLK;
1027 cmu.clk_regs = mfc_clk_regs;
1028 cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs);
1029
1030 samsung_cmu_register_one(np, &cmu);
1031 }
1032
1033 CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
1034 exynos5260_clk_mfc_init);
1035
1036
1037 /* CMU_MIF */
1038
1039 static unsigned long mif_clk_regs[] __initdata = {
1040 MEM_PLL_LOCK,
1041 BUS_PLL_LOCK,
1042 MEDIA_PLL_LOCK,
1043 MEM_PLL_CON0,
1044 MEM_PLL_CON1,
1045 MEM_PLL_FDET,
1046 BUS_PLL_CON0,
1047 BUS_PLL_CON1,
1048 BUS_PLL_FDET,
1049 MEDIA_PLL_CON0,
1050 MEDIA_PLL_CON1,
1051 MEDIA_PLL_FDET,
1052 MUX_SEL_MIF,
1053 DIV_MIF,
1054 DIV_MIF_PLL_FDET,
1055 EN_ACLK_MIF,
1056 EN_ACLK_MIF_SECURE_DREX1_TZ,
1057 EN_ACLK_MIF_SECURE_DREX0_TZ,
1058 EN_ACLK_MIF_SECURE_INTMEM,
1059 EN_PCLK_MIF,
1060 EN_PCLK_MIF_SECURE_MONOCNT,
1061 EN_PCLK_MIF_SECURE_RTC_APBIF,
1062 EN_PCLK_MIF_SECURE_DREX1_TZ,
1063 EN_PCLK_MIF_SECURE_DREX0_TZ,
1064 EN_SCLK_MIF,
1065 EN_IP_MIF,
1066 EN_IP_MIF_SECURE_MONOCNT,
1067 EN_IP_MIF_SECURE_RTC_APBIF,
1068 EN_IP_MIF_SECURE_DREX1_TZ,
1069 EN_IP_MIF_SECURE_DREX0_TZ,
1070 EN_IP_MIF_SECURE_INTEMEM,
1071 };
1072
1073 PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"};
1074 PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"};
1075 PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"};
1076 PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"};
1077 PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
1078 PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
1079 PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
1080
1081 static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1082 MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p,
1083 MUX_SEL_MIF, 0, 1),
1084 MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p,
1085 MUX_SEL_MIF, 4, 1),
1086 MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p,
1087 MUX_SEL_MIF, 8, 1),
1088 MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p,
1089 MUX_SEL_MIF, 12, 1),
1090 MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p,
1091 MUX_SEL_MIF, 16, 1),
1092 MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p,
1093 MUX_SEL_MIF, 20, 1),
1094 MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p,
1095 MUX_SEL_MIF, 24, 1),
1096 };
1097
1098 static struct samsung_div_clock mif_div_clks[] __initdata = {
1099 DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll",
1100 DIV_MIF, 0, 3),
1101 DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll",
1102 DIV_MIF, 4, 3),
1103 DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll",
1104 DIV_MIF, 8, 3),
1105 DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy",
1106 DIV_MIF, 12, 3),
1107 DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy",
1108 DIV_MIF, 16, 4),
1109 DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy",
1110 DIV_MIF, 20, 3),
1111 DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll",
1112 DIV_MIF, 24, 3),
1113 DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll",
1114 DIV_MIF, 28, 4),
1115 };
1116
1117 static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1118 GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
1119 EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
1120 GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
1121 EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
1122
1123 GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100",
1124 EN_IP_MIF_SECURE_MONOCNT, 22,
1125 CLK_IGNORE_UNUSED, 0),
1126
1127 GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100",
1128 EN_IP_MIF_SECURE_RTC_APBIF, 23,
1129 CLK_IGNORE_UNUSED, 0),
1130
1131 GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466",
1132 EN_IP_MIF_SECURE_DREX1_TZ, 9,
1133 CLK_IGNORE_UNUSED, 0),
1134
1135 GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466",
1136 EN_IP_MIF_SECURE_DREX0_TZ, 9,
1137 CLK_IGNORE_UNUSED, 0),
1138
1139 GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200",
1140 EN_IP_MIF_SECURE_INTEMEM, 11,
1141 CLK_IGNORE_UNUSED, 0),
1142
1143 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0",
1144 "dout_clkm_phy", EN_SCLK_MIF, 0,
1145 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1146 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1",
1147 "dout_clkm_phy", EN_SCLK_MIF, 1,
1148 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1149 };
1150
1151 static struct samsung_pll_clock mif_pll_clks[] __initdata = {
1152 PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
1153 MEM_PLL_LOCK, MEM_PLL_CON0,
1154 pll2550_24mhz_tbl),
1155 PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
1156 BUS_PLL_LOCK, BUS_PLL_CON0,
1157 pll2550_24mhz_tbl),
1158 PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
1159 MEDIA_PLL_LOCK, MEDIA_PLL_CON0,
1160 pll2550_24mhz_tbl),
1161 };
1162
1163 static void __init exynos5260_clk_mif_init(struct device_node *np)
1164 {
1165 struct samsung_cmu_info cmu = { NULL };
1166
1167 cmu.pll_clks = mif_pll_clks;
1168 cmu.nr_pll_clks = ARRAY_SIZE(mif_pll_clks);
1169 cmu.mux_clks = mif_mux_clks;
1170 cmu.nr_mux_clks = ARRAY_SIZE(mif_mux_clks);
1171 cmu.div_clks = mif_div_clks;
1172 cmu.nr_div_clks = ARRAY_SIZE(mif_div_clks);
1173 cmu.gate_clks = mif_gate_clks;
1174 cmu.nr_gate_clks = ARRAY_SIZE(mif_gate_clks);
1175 cmu.nr_clk_ids = MIF_NR_CLK;
1176 cmu.clk_regs = mif_clk_regs;
1177 cmu.nr_clk_regs = ARRAY_SIZE(mif_clk_regs);
1178
1179 samsung_cmu_register_one(np, &cmu);
1180 }
1181
1182 CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
1183 exynos5260_clk_mif_init);
1184
1185
1186 /* CMU_PERI */
1187
1188 static unsigned long peri_clk_regs[] __initdata = {
1189 MUX_SEL_PERI,
1190 MUX_SEL_PERI1,
1191 DIV_PERI,
1192 EN_PCLK_PERI0,
1193 EN_PCLK_PERI1,
1194 EN_PCLK_PERI2,
1195 EN_PCLK_PERI3,
1196 EN_PCLK_PERI_SECURE_CHIPID,
1197 EN_PCLK_PERI_SECURE_PROVKEY0,
1198 EN_PCLK_PERI_SECURE_PROVKEY1,
1199 EN_PCLK_PERI_SECURE_SECKEY,
1200 EN_PCLK_PERI_SECURE_ANTIRBKCNT,
1201 EN_PCLK_PERI_SECURE_TOP_RTC,
1202 EN_PCLK_PERI_SECURE_TZPC,
1203 EN_SCLK_PERI,
1204 EN_SCLK_PERI_SECURE_TOP_RTC,
1205 EN_IP_PERI0,
1206 EN_IP_PERI1,
1207 EN_IP_PERI2,
1208 EN_IP_PERI_SECURE_CHIPID,
1209 EN_IP_PERI_SECURE_PROVKEY0,
1210 EN_IP_PERI_SECURE_PROVKEY1,
1211 EN_IP_PERI_SECURE_SECKEY,
1212 EN_IP_PERI_SECURE_ANTIRBKCNT,
1213 EN_IP_PERI_SECURE_TOP_RTC,
1214 EN_IP_PERI_SECURE_TZPC,
1215 };
1216
1217 PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
1218 "phyclk_hdmi_phy_ref_cko"};
1219 PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
1220 "phyclk_hdmi_phy_ref_cko"};
1221 PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll",
1222 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
1223
1224 static struct samsung_mux_clock peri_mux_clks[] __initdata = {
1225 MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p,
1226 MUX_SEL_PERI1, 4, 2),
1227 MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p,
1228 MUX_SEL_PERI1, 12, 2),
1229 MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
1230 MUX_SEL_PERI1, 20, 2),
1231 };
1232
1233 static struct samsung_div_clock peri_div_clks[] __initdata = {
1234 DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
1235 DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6),
1236 };
1237
1238 static struct samsung_gate_clock peri_gate_clks[] __initdata = {
1239 GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
1240 CLK_SET_RATE_PARENT, 0),
1241 GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
1242 CLK_SET_RATE_PARENT, 0),
1243 GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
1244 EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0),
1245 GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
1246 EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0),
1247 GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
1248 EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0),
1249 GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
1250 EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),
1251 GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
1252 EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
1253 GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
1254 EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
1255 GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
1256 EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
1257
1258 GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66",
1259 EN_IP_PERI0, 1, 0, 0),
1260 GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66",
1261 EN_IP_PERI0, 5, 0, 0),
1262 GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66",
1263 EN_IP_PERI0, 6, 0, 0),
1264 GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66",
1265 EN_IP_PERI0, 7, 0, 0),
1266 GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66",
1267 EN_IP_PERI0, 8, 0, 0),
1268 GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66",
1269 EN_IP_PERI0, 9, 0, 0),
1270 GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66",
1271 EN_IP_PERI0, 10, 0, 0),
1272 GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66",
1273 EN_IP_PERI0, 11, 0, 0),
1274 GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66",
1275 EN_IP_PERI0, 12, 0, 0),
1276 GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66",
1277 EN_IP_PERI0, 13, 0, 0),
1278 GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66",
1279 EN_IP_PERI0, 14, 0, 0),
1280 GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66",
1281 EN_IP_PERI0, 15, 0, 0),
1282 GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66",
1283 EN_IP_PERI0, 16, 0, 0),
1284 GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66",
1285 EN_IP_PERI0, 17, 0, 0),
1286 GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66",
1287 EN_IP_PERI0, 18, 0, 0),
1288 GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66",
1289 EN_IP_PERI0, 20, 0, 0),
1290 GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66",
1291 EN_IP_PERI0, 21, 0, 0),
1292 GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66",
1293 EN_IP_PERI0, 22, 0, 0),
1294 GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66",
1295 EN_IP_PERI0, 23, 0, 0),
1296 GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66",
1297 EN_IP_PERI0, 24, 0, 0),
1298 GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66",
1299 EN_IP_PERI0, 25, 0, 0),
1300
1301 GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66",
1302 EN_IP_PERI2, 0, 0, 0),
1303 GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66",
1304 EN_IP_PERI2, 3, 0, 0),
1305 GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66",
1306 EN_IP_PERI2, 6, 0, 0),
1307 GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66",
1308 EN_IP_PERI2, 7, 0, 0),
1309 GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66",
1310 EN_IP_PERI2, 8, 0, 0),
1311 GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66",
1312 EN_IP_PERI2, 9, 0, 0),
1313 GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66",
1314 EN_IP_PERI2, 10, 0, 0),
1315 GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66",
1316 EN_IP_PERI2, 11, 0, 0),
1317 GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66",
1318 EN_IP_PERI2, 12, 0, 0),
1319 GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66",
1320 EN_IP_PERI2, 13, 0, 0),
1321 GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66",
1322 EN_IP_PERI2, 14, 0, 0),
1323 GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66",
1324 EN_IP_PERI2, 18, 0, 0),
1325 GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66",
1326 EN_IP_PERI2, 19, 0, 0),
1327 GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66",
1328 EN_IP_PERI2, 20, 0, 0),
1329 GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66",
1330 EN_IP_PERI2, 21, 0, 0),
1331
1332 GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66",
1333 EN_IP_PERI_SECURE_CHIPID, 2, 0, 0),
1334
1335 GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66",
1336 EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0),
1337
1338 GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66",
1339 EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0),
1340
1341 GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66",
1342 EN_IP_PERI_SECURE_SECKEY, 5, 0, 0),
1343
1344 GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66",
1345 EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0),
1346
1347 GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
1348 EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
1349 GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
1350 EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
1351 GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
1352 EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
1353 GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66",
1354 EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
1355 GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66",
1356 EN_IP_PERI_SECURE_TZPC, 14, 0, 0),
1357 GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66",
1358 EN_IP_PERI_SECURE_TZPC, 15, 0, 0),
1359 GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66",
1360 EN_IP_PERI_SECURE_TZPC, 16, 0, 0),
1361 GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66",
1362 EN_IP_PERI_SECURE_TZPC, 17, 0, 0),
1363 GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66",
1364 EN_IP_PERI_SECURE_TZPC, 18, 0, 0),
1365 GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66",
1366 EN_IP_PERI_SECURE_TZPC, 19, 0, 0),
1367 GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66",
1368 EN_IP_PERI_SECURE_TZPC, 20, 0, 0),
1369 };
1370
1371 static void __init exynos5260_clk_peri_init(struct device_node *np)
1372 {
1373 struct samsung_cmu_info cmu = { NULL };
1374
1375 cmu.mux_clks = peri_mux_clks;
1376 cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks);
1377 cmu.div_clks = peri_div_clks;
1378 cmu.nr_div_clks = ARRAY_SIZE(peri_div_clks);
1379 cmu.gate_clks = peri_gate_clks;
1380 cmu.nr_gate_clks = ARRAY_SIZE(peri_gate_clks);
1381 cmu.nr_clk_ids = PERI_NR_CLK;
1382 cmu.clk_regs = peri_clk_regs;
1383 cmu.nr_clk_regs = ARRAY_SIZE(peri_clk_regs);
1384
1385 samsung_cmu_register_one(np, &cmu);
1386 }
1387
1388 CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
1389 exynos5260_clk_peri_init);
1390
1391
1392 /* CMU_TOP */
1393
1394 static unsigned long top_clk_regs[] __initdata = {
1395 DISP_PLL_LOCK,
1396 AUD_PLL_LOCK,
1397 DISP_PLL_CON0,
1398 DISP_PLL_CON1,
1399 DISP_PLL_FDET,
1400 AUD_PLL_CON0,
1401 AUD_PLL_CON1,
1402 AUD_PLL_CON2,
1403 AUD_PLL_FDET,
1404 MUX_SEL_TOP_PLL0,
1405 MUX_SEL_TOP_MFC,
1406 MUX_SEL_TOP_G2D,
1407 MUX_SEL_TOP_GSCL,
1408 MUX_SEL_TOP_ISP10,
1409 MUX_SEL_TOP_ISP11,
1410 MUX_SEL_TOP_DISP0,
1411 MUX_SEL_TOP_DISP1,
1412 MUX_SEL_TOP_BUS,
1413 MUX_SEL_TOP_PERI0,
1414 MUX_SEL_TOP_PERI1,
1415 MUX_SEL_TOP_FSYS,
1416 DIV_TOP_G2D_MFC,
1417 DIV_TOP_GSCL_ISP0,
1418 DIV_TOP_ISP10,
1419 DIV_TOP_ISP11,
1420 DIV_TOP_DISP,
1421 DIV_TOP_BUS,
1422 DIV_TOP_PERI0,
1423 DIV_TOP_PERI1,
1424 DIV_TOP_PERI2,
1425 DIV_TOP_FSYS0,
1426 DIV_TOP_FSYS1,
1427 DIV_TOP_HPM,
1428 DIV_TOP_PLL_FDET,
1429 EN_ACLK_TOP,
1430 EN_SCLK_TOP,
1431 EN_IP_TOP,
1432 };
1433
1434 /* fixed rate clocks generated inside the soc */
1435 static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
1436 FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,
1437 CLK_IS_ROOT, 270000000),
1438 FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,
1439 CLK_IS_ROOT, 270000000),
1440 FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL,
1441 CLK_IS_ROOT, 270000000),
1442 FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL,
1443 CLK_IS_ROOT, 270000000),
1444 FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL,
1445 CLK_IS_ROOT, 250000000),
1446 FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL,
1447 CLK_IS_ROOT, 1660000000),
1448 FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
1449 NULL, CLK_IS_ROOT, 125000000),
1450 FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
1451 "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
1452 CLK_IS_ROOT, 187500000),
1453 FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
1454 NULL, CLK_IS_ROOT, 24000000),
1455 FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL,
1456 CLK_IS_ROOT, 135000000),
1457 FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0,
1458 "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL,
1459 CLK_IS_ROOT, 20000000),
1460 FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock",
1461 NULL, CLK_IS_ROOT, 60000000),
1462 FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk",
1463 NULL, CLK_IS_ROOT, 60000000),
1464 FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI,
1465 "phyclk_usbhost20_phy_clk48mohci",
1466 NULL, CLK_IS_ROOT, 48000000),
1467 FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
1468 "phyclk_usbdrd30_udrd30_pipe_pclk", NULL,
1469 CLK_IS_ROOT, 125000000),
1470 FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
1471 "phyclk_usbdrd30_udrd30_phyclock", NULL,
1472 CLK_IS_ROOT, 60000000),
1473 };
1474
1475 PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};
1476 PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"};
1477 PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"};
1478 PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"};
1479 PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"};
1480 PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"};
1481 PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1482 PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
1483 PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1484 PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
1485 PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1486 PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user",
1487 "mout_gscl_bustop_333"};
1488 PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1489 PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user",
1490 "mout_m2m_mediatop_400"};
1491 PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1492 PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user",
1493 "mout_gscl_bustop_fimc"};
1494 PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user",
1495 "mout_memtop_pll_user"};
1496 PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
1497 PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1498 PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
1499 PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"};
1500 PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"};
1501 PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"};
1502 PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
1503 PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
1504 PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
1505 PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
1506 PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user",
1507 "mout_bustop_pll_user"};
1508 PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"};
1509 PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1510 PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1511 PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"};
1512 PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"};
1513 PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"};
1514 PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"};
1515 PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a",
1516 "mout_mediatop_pll_user"};
1517 PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
1518 "mout_mediatop_pll_user"};
1519 PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
1520 "mout_mediatop_pll_user"};
1521
1522 static struct samsung_mux_clock top_mux_clks[] __initdata = {
1523 MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user",
1524 mout_mediatop_pll_user_p,
1525 MUX_SEL_TOP_PLL0, 0, 1),
1526 MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user",
1527 mout_memtop_pll_user_p,
1528 MUX_SEL_TOP_PLL0, 4, 1),
1529 MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user",
1530 mout_bustop_pll_user_p,
1531 MUX_SEL_TOP_PLL0, 8, 1),
1532 MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
1533 MUX_SEL_TOP_PLL0, 12, 1),
1534 MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
1535 MUX_SEL_TOP_PLL0, 16, 1),
1536 MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user",
1537 mout_audtop_pll_user_p,
1538 MUX_SEL_TOP_PLL0, 24, 1),
1539
1540 MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p,
1541 MUX_SEL_TOP_DISP0, 0, 1),
1542 MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p,
1543 MUX_SEL_TOP_DISP0, 8, 1),
1544 MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p,
1545 MUX_SEL_TOP_DISP0, 12, 1),
1546 MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p,
1547 MUX_SEL_TOP_DISP0, 20, 1),
1548
1549 MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
1550 MUX_SEL_TOP_DISP1, 0, 1),
1551 MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel",
1552 mout_disp_media_pixel_p,
1553 MUX_SEL_TOP_DISP1, 8, 1),
1554
1555 MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk",
1556 mout_sclk_peri_spi_clk_p,
1557 MUX_SEL_TOP_PERI1, 0, 1),
1558 MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk",
1559 mout_sclk_peri_spi_clk_p,
1560 MUX_SEL_TOP_PERI1, 4, 1),
1561 MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk",
1562 mout_sclk_peri_spi_clk_p,
1563 MUX_SEL_TOP_PERI1, 8, 1),
1564 MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk",
1565 mout_sclk_peri_uart_uclk_p,
1566 MUX_SEL_TOP_PERI1, 12, 1),
1567 MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk",
1568 mout_sclk_peri_uart_uclk_p,
1569 MUX_SEL_TOP_PERI1, 16, 1),
1570 MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk",
1571 mout_sclk_peri_uart_uclk_p,
1572 MUX_SEL_TOP_PERI1, 20, 1),
1573
1574
1575 MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400",
1576 mout_bus_bustop_400_p,
1577 MUX_SEL_TOP_BUS, 0, 1),
1578 MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100",
1579 mout_bus_bustop_100_p,
1580 MUX_SEL_TOP_BUS, 4, 1),
1581 MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100",
1582 mout_bus_bustop_100_p,
1583 MUX_SEL_TOP_BUS, 8, 1),
1584 MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400",
1585 mout_bus_bustop_400_p,
1586 MUX_SEL_TOP_BUS, 12, 1),
1587 MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400",
1588 mout_bus_bustop_400_p,
1589 MUX_SEL_TOP_BUS, 16, 1),
1590 MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100",
1591 mout_bus_bustop_100_p,
1592 MUX_SEL_TOP_BUS, 20, 1),
1593 MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400",
1594 mout_bus_bustop_400_p,
1595 MUX_SEL_TOP_BUS, 24, 1),
1596 MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100",
1597 mout_bus_bustop_100_p,
1598 MUX_SEL_TOP_BUS, 28, 1),
1599
1600 MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb",
1601 mout_sclk_fsys_usb_p,
1602 MUX_SEL_TOP_FSYS, 0, 1),
1603 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a",
1604 mout_sclk_fsys_mmc_sdclkin_a_p,
1605 MUX_SEL_TOP_FSYS, 4, 1),
1606 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b",
1607 mout_sclk_fsys_mmc2_sdclkin_b_p,
1608 MUX_SEL_TOP_FSYS, 8, 1),
1609 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a",
1610 mout_sclk_fsys_mmc_sdclkin_a_p,
1611 MUX_SEL_TOP_FSYS, 12, 1),
1612 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b",
1613 mout_sclk_fsys_mmc1_sdclkin_b_p,
1614 MUX_SEL_TOP_FSYS, 16, 1),
1615 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a",
1616 mout_sclk_fsys_mmc_sdclkin_a_p,
1617 MUX_SEL_TOP_FSYS, 20, 1),
1618 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b",
1619 mout_sclk_fsys_mmc0_sdclkin_b_p,
1620 MUX_SEL_TOP_FSYS, 24, 1),
1621
1622 MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400",
1623 mout_isp1_media_400_p,
1624 MUX_SEL_TOP_ISP10, 4, 1),
1625 MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
1626 MUX_SEL_TOP_ISP10, 8 , 1),
1627 MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
1628 mout_isp1_media_266_p,
1629 MUX_SEL_TOP_ISP10, 16, 1),
1630 MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
1631 MUX_SEL_TOP_ISP10, 20, 1),
1632
1633 MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
1634 MUX_SEL_TOP_ISP11, 4, 1),
1635 MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
1636 MUX_SEL_TOP_ISP11, 8, 1),
1637 MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart",
1638 mout_sclk_isp_uart_p,
1639 MUX_SEL_TOP_ISP11, 12, 1),
1640 MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0",
1641 mout_sclk_isp_sensor_p,
1642 MUX_SEL_TOP_ISP11, 16, 1),
1643 MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1",
1644 mout_sclk_isp_sensor_p,
1645 MUX_SEL_TOP_ISP11, 20, 1),
1646 MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2",
1647 mout_sclk_isp_sensor_p,
1648 MUX_SEL_TOP_ISP11, 24, 1),
1649
1650 MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333",
1651 mout_mfc_bustop_333_p,
1652 MUX_SEL_TOP_MFC, 4, 1),
1653 MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
1654 MUX_SEL_TOP_MFC, 8, 1),
1655
1656 MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333",
1657 mout_g2d_bustop_333_p,
1658 MUX_SEL_TOP_G2D, 4, 1),
1659 MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
1660 MUX_SEL_TOP_G2D, 8, 1),
1661
1662 MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400",
1663 mout_m2m_mediatop_400_p,
1664 MUX_SEL_TOP_GSCL, 0, 1),
1665 MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400",
1666 mout_aclk_gscl_400_p,
1667 MUX_SEL_TOP_GSCL, 4, 1),
1668 MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333",
1669 mout_gscl_bustop_333_p,
1670 MUX_SEL_TOP_GSCL, 8, 1),
1671 MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
1672 mout_aclk_gscl_333_p,
1673 MUX_SEL_TOP_GSCL, 12, 1),
1674 MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc",
1675 mout_gscl_bustop_fimc_p,
1676 MUX_SEL_TOP_GSCL, 16, 1),
1677 MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc",
1678 mout_aclk_gscl_fimc_p,
1679 MUX_SEL_TOP_GSCL, 20, 1),
1680 };
1681
1682 static struct samsung_div_clock top_div_clks[] __initdata = {
1683 DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
1684 DIV_TOP_G2D_MFC, 0, 3),
1685 DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
1686 DIV_TOP_G2D_MFC, 4, 3),
1687
1688 DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
1689 DIV_TOP_GSCL_ISP0, 0, 3),
1690 DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
1691 DIV_TOP_GSCL_ISP0, 4, 3),
1692 DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc",
1693 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3),
1694 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a",
1695 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4),
1696 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a",
1697 "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4),
1698 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a",
1699 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4),
1700
1701 DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
1702 DIV_TOP_ISP10, 0, 3),
1703 DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
1704 DIV_TOP_ISP10, 4, 3),
1705 DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a",
1706 "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4),
1707 DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b",
1708 "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8),
1709
1710 DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a",
1711 "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4),
1712 DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b",
1713 "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8),
1714 DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart",
1715 "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4),
1716 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b",
1717 "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4),
1718 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b",
1719 "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4),
1720 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b",
1721 "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4),
1722
1723 DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk",
1724 "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3),
1725
1726 DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333",
1727 DIV_TOP_DISP, 0, 3),
1728 DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222",
1729 DIV_TOP_DISP, 4, 3),
1730 DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel",
1731 "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3),
1732
1733 DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400",
1734 "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3),
1735 DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100",
1736 "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4),
1737 DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400",
1738 "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3),
1739 DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100",
1740 "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4),
1741 DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400",
1742 "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3),
1743 DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100",
1744 "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4),
1745 DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400",
1746 "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3),
1747 DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100",
1748 "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4),
1749
1750 DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a",
1751 "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4),
1752 DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b",
1753 "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8),
1754 DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a",
1755 "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4),
1756 DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b",
1757 "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8),
1758
1759 DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a",
1760 "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4),
1761 DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b",
1762 "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8),
1763 DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1",
1764 "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4),
1765 DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2",
1766 "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4),
1767 DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0",
1768 "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4),
1769
1770 DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user",
1771 DIV_TOP_PERI2, 20, 4),
1772 DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud",
1773 "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3),
1774
1775 DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200",
1776 "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3),
1777 DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK,
1778 "dout_sclk_fsys_usbdrd30_suspend_clk",
1779 "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4),
1780 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a",
1781 "mout_sclk_fsys_mmc0_sdclkin_b",
1782 DIV_TOP_FSYS0, 12, 4),
1783 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b",
1784 "dout_sclk_fsys_mmc0_sdclkin_a",
1785 DIV_TOP_FSYS0, 16, 8),
1786
1787
1788 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a",
1789 "mout_sclk_fsys_mmc1_sdclkin_b",
1790 DIV_TOP_FSYS1, 0, 4),
1791 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b",
1792 "dout_sclk_fsys_mmc1_sdclkin_a",
1793 DIV_TOP_FSYS1, 4, 8),
1794 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a",
1795 "mout_sclk_fsys_mmc2_sdclkin_b",
1796 DIV_TOP_FSYS1, 12, 4),
1797 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b",
1798 "dout_sclk_fsys_mmc2_sdclkin_a",
1799 DIV_TOP_FSYS1, 16, 8),
1800
1801 };
1802
1803 static struct samsung_gate_clock top_gate_clks[] __initdata = {
1804 GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
1805 "dout_sclk_fsys_mmc0_sdclkin_b",
1806 EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
1807 GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
1808 "dout_sclk_fsys_mmc1_sdclkin_b",
1809 EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0),
1810 GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
1811 "dout_sclk_fsys_mmc2_sdclkin_b",
1812 EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
1813 GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel",
1814 EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED |
1815 CLK_SET_RATE_PARENT, 0),
1816 };
1817
1818 static struct samsung_pll_clock top_pll_clks[] __initdata = {
1819 PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
1820 DISP_PLL_LOCK, DISP_PLL_CON0,
1821 pll2550_24mhz_tbl),
1822 PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
1823 AUD_PLL_LOCK, AUD_PLL_CON0,
1824 pll2650_24mhz_tbl),
1825 };
1826
1827 static void __init exynos5260_clk_top_init(struct device_node *np)
1828 {
1829 struct samsung_cmu_info cmu = { NULL };
1830
1831 cmu.pll_clks = top_pll_clks;
1832 cmu.nr_pll_clks = ARRAY_SIZE(top_pll_clks);
1833 cmu.mux_clks = top_mux_clks;
1834 cmu.nr_mux_clks = ARRAY_SIZE(top_mux_clks);
1835 cmu.div_clks = top_div_clks;
1836 cmu.nr_div_clks = ARRAY_SIZE(top_div_clks);
1837 cmu.gate_clks = top_gate_clks;
1838 cmu.nr_gate_clks = ARRAY_SIZE(top_gate_clks);
1839 cmu.fixed_clks = fixed_rate_clks;
1840 cmu.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks);
1841 cmu.nr_clk_ids = TOP_NR_CLK;
1842 cmu.clk_regs = top_clk_regs;
1843 cmu.nr_clk_regs = ARRAY_SIZE(top_clk_regs);
1844
1845 samsung_cmu_register_one(np, &cmu);
1846 }
1847
1848 CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
1849 exynos5260_clk_top_init);
Linux with added FPC-III support