drivers/clk/samsung/clk-s3c2412.c

   1 /*
   2  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Common Clock Framework support for S3C2412 and S3C2413.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/syscore_ops.h>
  17 #include <linux/reboot.h>
  18
  19 #include <dt-bindings/clock/s3c2412.h>
  20
  21 #include "clk.h"
  22 #include "clk-pll.h"
  23
  24 #define LOCKTIME        0x00
  25 #define MPLLCON         0x04
  26 #define UPLLCON         0x08
  27 #define CLKCON          0x0c
  28 #define CLKDIVN         0x14
  29 #define CLKSRC          0x1c
  30 #define SWRST           0x30
  31
  32 /* list of PLLs to be registered */
  33 enum s3c2412_plls {
  34         mpll, upll,
  35 };
  36
  37 static void __iomem *reg_base;
  38
  39 #ifdef CONFIG_PM_SLEEP
  40 static struct samsung_clk_reg_dump *s3c2412_save;
  41
  42 /*
  43  * list of controller registers to be saved and restored during a
  44  * suspend/resume cycle.
  45  */
  46 static unsigned long s3c2412_clk_regs[] __initdata = {
  47         LOCKTIME,
  48         MPLLCON,
  49         UPLLCON,
  50         CLKCON,
  51         CLKDIVN,
  52         CLKSRC,
  53 };
  54
  55 static int s3c2412_clk_suspend(void)
  56 {
  57         samsung_clk_save(reg_base, s3c2412_save,
  58                                 ARRAY_SIZE(s3c2412_clk_regs));
  59
  60         return 0;
  61 }
  62
  63 static void s3c2412_clk_resume(void)
  64 {
  65         samsung_clk_restore(reg_base, s3c2412_save,
  66                                 ARRAY_SIZE(s3c2412_clk_regs));
  67 }
  68
  69 static struct syscore_ops s3c2412_clk_syscore_ops = {
  70         .suspend = s3c2412_clk_suspend,
  71         .resume = s3c2412_clk_resume,
  72 };
  73
  74 static void s3c2412_clk_sleep_init(void)
  75 {
  76         s3c2412_save = samsung_clk_alloc_reg_dump(s3c2412_clk_regs,
  77                                                 ARRAY_SIZE(s3c2412_clk_regs));
  78         if (!s3c2412_save) {
  79                 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
  80                         __func__);
  81                 return;
  82         }
  83
  84         register_syscore_ops(&s3c2412_clk_syscore_ops);
  85         return;
  86 }
  87 #else
  88 static void s3c2412_clk_sleep_init(void) {}
  89 #endif
  90
  91 static struct clk_div_table divxti_d[] = {
  92         { .val = 0, .div = 1 },
  93         { .val = 1, .div = 2 },
  94         { .val = 2, .div = 4 },
  95         { .val = 3, .div = 6 },
  96         { .val = 4, .div = 8 },
  97         { .val = 5, .div = 10 },
  98         { .val = 6, .div = 12 },
  99         { .val = 7, .div = 14 },
 100         { /* sentinel */ },
 101 };
 102
 103 struct samsung_div_clock s3c2412_dividers[] __initdata = {
 104         DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d),
 105         DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4),
 106         DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4),
 107         DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4),
 108         DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1),
 109         DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1),
 110         DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1),
 111         DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
 112         DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
 113 };
 114
 115 struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = {
 116         FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
 117 };
 118
 119 /*
 120  * The first two use the OM[4] setting, which is not readable from
 121  * software, so assume it is set to xti.
 122  */
 123 PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
 124 PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
 125
 126 PNAME(camclk_p) = { "usysclk", "hclk" };
 127 PNAME(usbclk_p) = { "usysclk", "hclk" };
 128 PNAME(i2sclk_p) = { "erefclk", "mpll" };
 129 PNAME(uartclk_p) = { "erefclk", "mpll" };
 130 PNAME(usysclk_p) = { "urefclk", "upll" };
 131 PNAME(msysclk_p) = { "mdivclk", "mpll" };
 132 PNAME(mdivclk_p) = { "xti", "div_xti" };
 133 PNAME(armclk_p) = { "armdiv", "hclk" };
 134
 135 struct samsung_mux_clock s3c2412_muxes[] __initdata = {
 136         MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
 137         MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
 138         MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
 139         MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
 140         MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
 141         MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
 142         MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
 143         MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
 144         MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
 145         MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
 146 };
 147
 148 static struct samsung_pll_clock s3c2412_plls[] __initdata = {
 149         [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
 150                                                 LOCKTIME, MPLLCON, NULL),
 151         [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk",
 152                                                 LOCKTIME, UPLLCON, NULL),
 153 };
 154
 155 struct samsung_gate_clock s3c2412_gates[] __initdata = {
 156         GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
 157         GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
 158         GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
 159         GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
 160         GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
 161         GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
 162         GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
 163         GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
 164         GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
 165         GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
 166         GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0),
 167         GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
 168         GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0),
 169         GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0),
 170         GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0),
 171         GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0),
 172         GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0),
 173         GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0),
 174         GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0),
 175         GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0),
 176         GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
 177         GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
 178         GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
 179         GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
 180         GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0),
 181         GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0),
 182         GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0),
 183         GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0),
 184 };
 185
 186 struct samsung_clock_alias s3c2412_aliases[] __initdata = {
 187         ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
 188         ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
 189         ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"),
 190         ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
 191         ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
 192         ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"),
 193         ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
 194         ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
 195         ALIAS(PCLK_ADC, NULL, "adc"),
 196         ALIAS(PCLK_RTC, NULL, "rtc"),
 197         ALIAS(PCLK_PWM, NULL, "timers"),
 198         ALIAS(HCLK_LCD, NULL, "lcd"),
 199         ALIAS(PCLK_USBD, NULL, "usb-device"),
 200         ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"),
 201         ALIAS(HCLK_USBH, NULL, "usb-host"),
 202         ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
 203         ALIAS(ARMCLK, NULL, "armclk"),
 204         ALIAS(HCLK, NULL, "hclk"),
 205         ALIAS(MPLL, NULL, "mpll"),
 206         ALIAS(MSYSCLK, NULL, "fclk"),
 207 };
 208
 209 static int s3c2412_restart(struct notifier_block *this,
 210                            unsigned long mode, void *cmd)
 211 {
 212         /* errata "Watch-dog/Software Reset Problem" specifies that
 213          * this reset must be done with the SYSCLK sourced from
 214          * EXTCLK instead of FOUT to avoid a glitch in the reset
 215          * mechanism.
 216          *
 217          * See the watchdog section of the S3C2412 manual for more
 218          * information on this fix.
 219          */
 220
 221         __raw_writel(0x00, reg_base + CLKSRC);
 222         __raw_writel(0x533C2412, reg_base + SWRST);
 223         return NOTIFY_DONE;
 224 }
 225
 226 static struct notifier_block s3c2412_restart_handler = {
 227         .notifier_call = s3c2412_restart,
 228         .priority = 129,
 229 };
 230
 231 /*
 232  * fixed rate clocks generated outside the soc
 233  * Only necessary until the devicetree-move is complete
 234  */
 235 #define XTI     1
 236 struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
 237         FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0),
 238         FRATE(0, "ext", NULL, CLK_IS_ROOT, 0),
 239 };
 240
 241 static void __init s3c2412_common_clk_register_fixed_ext(
 242                 struct samsung_clk_provider *ctx,
 243                 unsigned long xti_f, unsigned long ext_f)
 244 {
 245         /* xtal alias is necessary for the current cpufreq driver */
 246         struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
 247
 248         s3c2412_common_frate_clks[0].fixed_rate = xti_f;
 249         s3c2412_common_frate_clks[1].fixed_rate = ext_f;
 250         samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
 251                                 ARRAY_SIZE(s3c2412_common_frate_clks));
 252
 253         samsung_clk_register_alias(ctx, &xti_alias, 1);
 254 }
 255
 256 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
 257                                     unsigned long ext_f, void __iomem *base)
 258 {
 259         struct samsung_clk_provider *ctx;
 260         int ret;
 261         reg_base = base;
 262
 263         if (np) {
 264                 reg_base = of_iomap(np, 0);
 265                 if (!reg_base)
 266                         panic("%s: failed to map registers\n", __func__);
 267         }
 268
 269         ctx = samsung_clk_init(np, reg_base, NR_CLKS);
 270         if (!ctx)
 271                 panic("%s: unable to allocate context.\n", __func__);
 272
 273         /* Register external clocks only in non-dt cases */
 274         if (!np)
 275                 s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
 276
 277         /* Register PLLs. */
 278         samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
 279                                  reg_base);
 280
 281         /* Register common internal clocks. */
 282         samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
 283         samsung_clk_register_div(ctx, s3c2412_dividers,
 284                                           ARRAY_SIZE(s3c2412_dividers));
 285         samsung_clk_register_gate(ctx, s3c2412_gates,
 286                                         ARRAY_SIZE(s3c2412_gates));
 287         samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
 288                                           ARRAY_SIZE(s3c2412_ffactor));
 289         samsung_clk_register_alias(ctx, s3c2412_aliases,
 290                                    ARRAY_SIZE(s3c2412_aliases));
 291
 292         s3c2412_clk_sleep_init();
 293
 294         samsung_clk_of_add_provider(np, ctx);
 295
 296         ret = register_restart_handler(&s3c2412_restart_handler);
 297         if (ret)
 298                 pr_warn("cannot register restart handler, %d\n", ret);
 299 }
 300
 301 static void __init s3c2412_clk_init(struct device_node *np)
 302 {
 303         s3c2412_common_clk_init(np, 0, 0, 0);
 304 }
 305 CLK_OF_DECLARE(s3c2412_clk, "samsung,s3c2412-clock", s3c2412_clk_init);