drivers/devfreq/event/exynos-ppmu.h

   1 /*
   2  * exynos_ppmu.h - EXYNOS PPMU header file
   3  *
   4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5  * Author : Chanwoo Choi <cw00.choi@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #ifndef __EXYNOS_PPMU_H__
  13 #define __EXYNOS_PPMU_H__
  14
  15 enum ppmu_state {
  16         PPMU_DISABLE = 0,
  17         PPMU_ENABLE,
  18 };
  19
  20 enum ppmu_counter {
  21         PPMU_PMNCNT0 = 0,
  22         PPMU_PMNCNT1,
  23         PPMU_PMNCNT2,
  24         PPMU_PMNCNT3,
  25
  26         PPMU_PMNCNT_MAX,
  27 };
  28
  29 enum ppmu_event_type {
  30         PPMU_RO_BUSY_CYCLE_CNT  = 0x0,
  31         PPMU_WO_BUSY_CYCLE_CNT  = 0x1,
  32         PPMU_RW_BUSY_CYCLE_CNT  = 0x2,
  33         PPMU_RO_REQUEST_CNT     = 0x3,
  34         PPMU_WO_REQUEST_CNT     = 0x4,
  35         PPMU_RO_DATA_CNT        = 0x5,
  36         PPMU_WO_DATA_CNT        = 0x6,
  37         PPMU_RO_LATENCY         = 0x12,
  38         PPMU_WO_LATENCY         = 0x16,
  39 };
  40
  41 enum ppmu_reg {
  42         /* PPC control register */
  43         PPMU_PMNC               = 0x00,
  44         PPMU_CNTENS             = 0x10,
  45         PPMU_CNTENC             = 0x20,
  46         PPMU_INTENS             = 0x30,
  47         PPMU_INTENC             = 0x40,
  48         PPMU_FLAG               = 0x50,
  49
  50         /* Cycle Counter and Performance Event Counter Register */
  51         PPMU_CCNT               = 0x100,
  52         PPMU_PMCNT0             = 0x110,
  53         PPMU_PMCNT1             = 0x120,
  54         PPMU_PMCNT2             = 0x130,
  55         PPMU_PMCNT3_HIGH        = 0x140,
  56         PPMU_PMCNT3_LOW         = 0x150,
  57
  58         /* Bus Event Generator */
  59         PPMU_BEVT0SEL           = 0x1000,
  60         PPMU_BEVT1SEL           = 0x1100,
  61         PPMU_BEVT2SEL           = 0x1200,
  62         PPMU_BEVT3SEL           = 0x1300,
  63         PPMU_COUNTER_RESET      = 0x1810,
  64         PPMU_READ_OVERFLOW_CNT  = 0x1810,
  65         PPMU_READ_UNDERFLOW_CNT = 0x1814,
  66         PPMU_WRITE_OVERFLOW_CNT = 0x1850,
  67         PPMU_WRITE_UNDERFLOW_CNT = 0x1854,
  68         PPMU_READ_PENDING_CNT   = 0x1880,
  69         PPMU_WRITE_PENDING_CNT  = 0x1884
  70 };
  71
  72 /* PMNC register */
  73 #define PPMU_PMNC_CC_RESET_SHIFT        2
  74 #define PPMU_PMNC_COUNTER_RESET_SHIFT   1
  75 #define PPMU_PMNC_ENABLE_SHIFT          0
  76 #define PPMU_PMNC_START_MODE_MASK       BIT(16)
  77 #define PPMU_PMNC_CC_DIVIDER_MASK       BIT(3)
  78 #define PPMU_PMNC_CC_RESET_MASK         BIT(2)
  79 #define PPMU_PMNC_COUNTER_RESET_MASK    BIT(1)
  80 #define PPMU_PMNC_ENABLE_MASK           BIT(0)
  81
  82 /* CNTENS/CNTENC/INTENS/INTENC/FLAG register */
  83 #define PPMU_CCNT_MASK                  BIT(31)
  84 #define PPMU_PMCNT3_MASK                BIT(3)
  85 #define PPMU_PMCNT2_MASK                BIT(2)
  86 #define PPMU_PMCNT1_MASK                BIT(1)
  87 #define PPMU_PMCNT0_MASK                BIT(0)
  88
  89 /* PPMU_PMNCTx/PPMU_BETxSEL registers */
  90 #define PPMU_PMNCT(x)                   (PPMU_PMCNT0 + (0x10 * x))
  91 #define PPMU_BEVTxSEL(x)                (PPMU_BEVT0SEL + (0x100 * x))
  92
  93 #endif /* __EXYNOS_PPMU_H__ */