drivers/irqchip/irq-renesas-irqc.c

   1 /*
   2  * Renesas IRQC Driver
   3  *
   4  *  Copyright (C) 2013 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/clk.h>
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/ioport.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqdomain.h>
  29 #include <linux/err.h>
  30 #include <linux/slab.h>
  31 #include <linux/module.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #define IRQC_IRQ_MAX    32      /* maximum 32 interrupts per driver instance */
  35
  36 #define IRQC_REQ_STS    0x00    /* Interrupt Request Status Register */
  37 #define IRQC_EN_STS     0x04    /* Interrupt Enable Status Register */
  38 #define IRQC_EN_SET     0x08    /* Interrupt Enable Set Register */
  39 #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
  40                                 /* SYS-CPU vs. RT-CPU */
  41 #define DETECT_STATUS   0x100   /* IRQn Detect Status Register */
  42 #define MONITOR         0x104   /* IRQn Signal Level Monitor Register */
  43 #define HLVL_STS        0x108   /* IRQn High Level Detect Status Register */
  44 #define LLVL_STS        0x10c   /* IRQn Low Level Detect Status Register */
  45 #define S_R_EDGE_STS    0x110   /* IRQn Sync Rising Edge Detect Status Reg. */
  46 #define S_F_EDGE_STS    0x114   /* IRQn Sync Falling Edge Detect Status Reg. */
  47 #define A_R_EDGE_STS    0x118   /* IRQn Async Rising Edge Detect Status Reg. */
  48 #define A_F_EDGE_STS    0x11c   /* IRQn Async Falling Edge Detect Status Reg. */
  49 #define CHTEN_STS       0x120   /* Chattering Reduction Status Register */
  50 #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
  51                                 /* IRQn Configuration Register */
  52
  53 struct irqc_irq {
  54         int hw_irq;
  55         int requested_irq;
  56         int domain_irq;
  57         struct irqc_priv *p;
  58 };
  59
  60 struct irqc_priv {
  61         void __iomem *iomem;
  62         void __iomem *cpu_int_base;
  63         struct irqc_irq irq[IRQC_IRQ_MAX];
  64         unsigned int number_of_irqs;
  65         struct platform_device *pdev;
  66         struct irq_chip irq_chip;
  67         struct irq_domain *irq_domain;
  68         struct clk *clk;
  69 };
  70
  71 static void irqc_dbg(struct irqc_irq *i, char *str)
  72 {
  73         dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
  74                 str, i->requested_irq, i->hw_irq, i->domain_irq);
  75 }
  76
  77 static void irqc_irq_enable(struct irq_data *d)
  78 {
  79         struct irqc_priv *p = irq_data_get_irq_chip_data(d);
  80         int hw_irq = irqd_to_hwirq(d);
  81
  82         irqc_dbg(&p->irq[hw_irq], "enable");
  83         iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
  84 }
  85
  86 static void irqc_irq_disable(struct irq_data *d)
  87 {
  88         struct irqc_priv *p = irq_data_get_irq_chip_data(d);
  89         int hw_irq = irqd_to_hwirq(d);
  90
  91         irqc_dbg(&p->irq[hw_irq], "disable");
  92         iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
  93 }
  94
  95 static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
  96         [IRQ_TYPE_LEVEL_LOW]    = 0x01,
  97         [IRQ_TYPE_LEVEL_HIGH]   = 0x02,
  98         [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
  99         [IRQ_TYPE_EDGE_RISING]  = 0x08, /* Synchronous */
 100         [IRQ_TYPE_EDGE_BOTH]    = 0x0c, /* Synchronous */
 101 };
 102
 103 static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
 104 {
 105         struct irqc_priv *p = irq_data_get_irq_chip_data(d);
 106         int hw_irq = irqd_to_hwirq(d);
 107         unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
 108         u32 tmp;
 109
 110         irqc_dbg(&p->irq[hw_irq], "sense");
 111
 112         if (!value)
 113                 return -EINVAL;
 114
 115         tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
 116         tmp &= ~0x3f;
 117         tmp |= value;
 118         iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
 119         return 0;
 120 }
 121
 122 static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
 123 {
 124         struct irqc_priv *p = irq_data_get_irq_chip_data(d);
 125
 126         if (!p->clk)
 127                 return 0;
 128
 129         if (on)
 130                 clk_enable(p->clk);
 131         else
 132                 clk_disable(p->clk);
 133
 134         return 0;
 135 }
 136
 137 static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
 138 {
 139         struct irqc_irq *i = dev_id;
 140         struct irqc_priv *p = i->p;
 141         u32 bit = BIT(i->hw_irq);
 142
 143         irqc_dbg(i, "demux1");
 144
 145         if (ioread32(p->iomem + DETECT_STATUS) & bit) {
 146                 iowrite32(bit, p->iomem + DETECT_STATUS);
 147                 irqc_dbg(i, "demux2");
 148                 generic_handle_irq(i->domain_irq);
 149                 return IRQ_HANDLED;
 150         }
 151         return IRQ_NONE;
 152 }
 153
 154 static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
 155                                irq_hw_number_t hw)
 156 {
 157         struct irqc_priv *p = h->host_data;
 158
 159         p->irq[hw].domain_irq = virq;
 160         p->irq[hw].hw_irq = hw;
 161
 162         irqc_dbg(&p->irq[hw], "map");
 163         irq_set_chip_data(virq, h->host_data);
 164         irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
 165         set_irq_flags(virq, IRQF_VALID); /* kill me now */
 166         return 0;
 167 }
 168
 169 static const struct irq_domain_ops irqc_irq_domain_ops = {
 170         .map    = irqc_irq_domain_map,
 171         .xlate  = irq_domain_xlate_twocell,
 172 };
 173
 174 static int irqc_probe(struct platform_device *pdev)
 175 {
 176         struct irqc_priv *p;
 177         struct resource *io;
 178         struct resource *irq;
 179         struct irq_chip *irq_chip;
 180         const char *name = dev_name(&pdev->dev);
 181         int ret;
 182         int k;
 183
 184         p = kzalloc(sizeof(*p), GFP_KERNEL);
 185         if (!p) {
 186                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 187                 ret = -ENOMEM;
 188                 goto err0;
 189         }
 190
 191         p->pdev = pdev;
 192         platform_set_drvdata(pdev, p);
 193
 194         p->clk = devm_clk_get(&pdev->dev, NULL);
 195         if (IS_ERR(p->clk)) {
 196                 dev_warn(&pdev->dev, "unable to get clock\n");
 197                 p->clk = NULL;
 198         }
 199
 200         pm_runtime_enable(&pdev->dev);
 201         pm_runtime_get_sync(&pdev->dev);
 202
 203         /* get hold of manadatory IOMEM */
 204         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 205         if (!io) {
 206                 dev_err(&pdev->dev, "not enough IOMEM resources\n");
 207                 ret = -EINVAL;
 208                 goto err1;
 209         }
 210
 211         /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
 212         for (k = 0; k < IRQC_IRQ_MAX; k++) {
 213                 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
 214                 if (!irq)
 215                         break;
 216
 217                 p->irq[k].p = p;
 218                 p->irq[k].requested_irq = irq->start;
 219         }
 220
 221         p->number_of_irqs = k;
 222         if (p->number_of_irqs < 1) {
 223                 dev_err(&pdev->dev, "not enough IRQ resources\n");
 224                 ret = -EINVAL;
 225                 goto err1;
 226         }
 227
 228         /* ioremap IOMEM and setup read/write callbacks */
 229         p->iomem = ioremap_nocache(io->start, resource_size(io));
 230         if (!p->iomem) {
 231                 dev_err(&pdev->dev, "failed to remap IOMEM\n");
 232                 ret = -ENXIO;
 233                 goto err2;
 234         }
 235
 236         p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
 237
 238         irq_chip = &p->irq_chip;
 239         irq_chip->name = name;
 240         irq_chip->irq_mask = irqc_irq_disable;
 241         irq_chip->irq_unmask = irqc_irq_enable;
 242         irq_chip->irq_set_type = irqc_irq_set_type;
 243         irq_chip->irq_set_wake = irqc_irq_set_wake;
 244         irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
 245
 246         p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
 247                                               p->number_of_irqs, 0,
 248                                               &irqc_irq_domain_ops, p);
 249         if (!p->irq_domain) {
 250                 ret = -ENXIO;
 251                 dev_err(&pdev->dev, "cannot initialize irq domain\n");
 252                 goto err2;
 253         }
 254
 255         /* request interrupts one by one */
 256         for (k = 0; k < p->number_of_irqs; k++) {
 257                 if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
 258                                 0, name, &p->irq[k])) {
 259                         dev_err(&pdev->dev, "failed to request IRQ\n");
 260                         ret = -ENOENT;
 261                         goto err3;
 262                 }
 263         }
 264
 265         dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
 266
 267         return 0;
 268 err3:
 269         while (--k >= 0)
 270                 free_irq(p->irq[k].requested_irq, &p->irq[k]);
 271
 272         irq_domain_remove(p->irq_domain);
 273 err2:
 274         iounmap(p->iomem);
 275 err1:
 276         pm_runtime_put(&pdev->dev);
 277         pm_runtime_disable(&pdev->dev);
 278         kfree(p);
 279 err0:
 280         return ret;
 281 }
 282
 283 static int irqc_remove(struct platform_device *pdev)
 284 {
 285         struct irqc_priv *p = platform_get_drvdata(pdev);
 286         int k;
 287
 288         for (k = 0; k < p->number_of_irqs; k++)
 289                 free_irq(p->irq[k].requested_irq, &p->irq[k]);
 290
 291         irq_domain_remove(p->irq_domain);
 292         iounmap(p->iomem);
 293         pm_runtime_put(&pdev->dev);
 294         pm_runtime_disable(&pdev->dev);
 295         kfree(p);
 296         return 0;
 297 }
 298
 299 static const struct of_device_id irqc_dt_ids[] = {
 300         { .compatible = "renesas,irqc", },
 301         {},
 302 };
 303 MODULE_DEVICE_TABLE(of, irqc_dt_ids);
 304
 305 static struct platform_driver irqc_device_driver = {
 306         .probe          = irqc_probe,
 307         .remove         = irqc_remove,
 308         .driver         = {
 309                 .name   = "renesas_irqc",
 310                 .of_match_table = irqc_dt_ids,
 311         }
 312 };
 313
 314 static int __init irqc_init(void)
 315 {
 316         return platform_driver_register(&irqc_device_driver);
 317 }
 318 postcore_initcall(irqc_init);
 319
 320 static void __exit irqc_exit(void)
 321 {
 322         platform_driver_unregister(&irqc_device_driver);
 323 }
 324 module_exit(irqc_exit);
 325
 326 MODULE_AUTHOR("Magnus Damm");
 327 MODULE_DESCRIPTION("Renesas IRQC Driver");
 328 MODULE_LICENSE("GPL v2");