1 // SPDX-License-Identifier: GPL-2.0-only
3 * motu-protocol-v2.c - a part of driver for MOTU FireWire series
5 * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
10 #define V2_CLOCK_STATUS_OFFSET 0x0b14
11 #define V2_CLOCK_RATE_MASK 0x00000038
12 #define V2_CLOCK_RATE_SHIFT 3
13 #define V2_CLOCK_SRC_MASK 0x00000007
14 #define V2_CLOCK_SRC_SHIFT 0
15 #define V2_CLOCK_FETCH_ENABLE 0x02000000
16 #define V2_CLOCK_MODEL_SPECIFIC 0x04000000
18 #define V2_IN_OUT_CONF_OFFSET 0x0c04
19 #define V2_OPT_OUT_IFACE_MASK 0x00000c00
20 #define V2_OPT_OUT_IFACE_SHIFT 10
21 #define V2_OPT_IN_IFACE_MASK 0x00000300
22 #define V2_OPT_IN_IFACE_SHIFT 8
23 #define V2_OPT_IFACE_MODE_NONE 0
24 #define V2_OPT_IFACE_MODE_ADAT 1
25 #define V2_OPT_IFACE_MODE_SPDIF 2
27 static int get_clock_rate(u32 data
, unsigned int *rate
)
29 unsigned int index
= (data
& V2_CLOCK_RATE_MASK
) >> V2_CLOCK_RATE_SHIFT
;
30 if (index
>= ARRAY_SIZE(snd_motu_clock_rates
))
33 *rate
= snd_motu_clock_rates
[index
];
38 static int v2_get_clock_rate(struct snd_motu
*motu
, unsigned int *rate
)
43 err
= snd_motu_transaction_read(motu
, V2_CLOCK_STATUS_OFFSET
, ®
,
48 return get_clock_rate(be32_to_cpu(reg
), rate
);
51 static int v2_set_clock_rate(struct snd_motu
*motu
, unsigned int rate
)
58 for (i
= 0; i
< ARRAY_SIZE(snd_motu_clock_rates
); ++i
) {
59 if (snd_motu_clock_rates
[i
] == rate
)
62 if (i
== ARRAY_SIZE(snd_motu_clock_rates
))
65 err
= snd_motu_transaction_read(motu
, V2_CLOCK_STATUS_OFFSET
, ®
,
69 data
= be32_to_cpu(reg
);
71 data
&= ~V2_CLOCK_RATE_MASK
;
72 data
|= i
<< V2_CLOCK_RATE_SHIFT
;
74 reg
= cpu_to_be32(data
);
75 return snd_motu_transaction_write(motu
, V2_CLOCK_STATUS_OFFSET
, ®
,
79 static int get_clock_source(struct snd_motu
*motu
, u32 data
,
80 enum snd_motu_clock_source
*src
)
82 unsigned int index
= data
& V2_CLOCK_SRC_MASK
;
88 *src
= SND_MOTU_CLOCK_SOURCE_INTERNAL
;
94 // To check the configuration of optical interface.
95 int err
= snd_motu_transaction_read(motu
, V2_IN_OUT_CONF_OFFSET
,
100 if (be32_to_cpu(reg
) & 0x00000200)
101 *src
= SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT
;
103 *src
= SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT
;
107 *src
= SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX
;
110 *src
= SND_MOTU_CLOCK_SOURCE_SPH
;
113 *src
= SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC
;
116 *src
= SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB
;
125 static int v2_get_clock_source(struct snd_motu
*motu
,
126 enum snd_motu_clock_source
*src
)
131 err
= snd_motu_transaction_read(motu
, V2_CLOCK_STATUS_OFFSET
, ®
,
136 return get_clock_source(motu
, be32_to_cpu(reg
), src
);
139 static int v2_switch_fetching_mode(struct snd_motu
*motu
, bool enable
)
141 enum snd_motu_clock_source src
;
146 // 828mkII implements Altera ACEX 1K EP1K30. Nothing to do.
147 if (motu
->spec
== &snd_motu_spec_828mk2
)
150 err
= snd_motu_transaction_read(motu
, V2_CLOCK_STATUS_OFFSET
, ®
,
154 data
= be32_to_cpu(reg
);
156 err
= get_clock_source(motu
, data
, &src
);
160 data
&= ~(V2_CLOCK_FETCH_ENABLE
| V2_CLOCK_MODEL_SPECIFIC
);
162 data
|= V2_CLOCK_FETCH_ENABLE
;
164 if (motu
->spec
->flags
& SND_MOTU_SPEC_SUPPORT_CLOCK_X4
) {
165 // Expected for Traveler and 896HD, which implements Altera
167 data
|= V2_CLOCK_MODEL_SPECIFIC
;
169 // For UltraLite and 8pre, which implements Xilinx Spartan
173 err
= get_clock_rate(data
, &rate
);
177 if (src
== SND_MOTU_CLOCK_SOURCE_SPH
&& rate
> 48000)
178 data
|= V2_CLOCK_MODEL_SPECIFIC
;
181 reg
= cpu_to_be32(data
);
182 return snd_motu_transaction_write(motu
, V2_CLOCK_STATUS_OFFSET
, ®
,
186 static void calculate_fixed_part(struct snd_motu_packet_format
*formats
,
187 enum amdtp_stream_direction dir
,
188 enum snd_motu_spec_flags flags
,
189 unsigned char analog_ports
)
191 unsigned char pcm_chunks
[3] = {0, 0, 0};
193 formats
->msg_chunks
= 2;
195 pcm_chunks
[0] = analog_ports
;
196 pcm_chunks
[1] = analog_ports
;
197 if (flags
& SND_MOTU_SPEC_SUPPORT_CLOCK_X4
)
198 pcm_chunks
[2] = analog_ports
;
200 if (dir
== AMDTP_IN_STREAM
) {
201 if (flags
& SND_MOTU_SPEC_TX_MICINST_CHUNK
) {
205 if (flags
& SND_MOTU_SPEC_TX_RETURN_CHUNK
) {
210 if (flags
& SND_MOTU_SPEC_RX_SEPARATED_MAIN
) {
215 // Packets to v2 units include 2 chunks for phone 1/2, except
216 // for 176.4/192.0 kHz.
221 if (flags
& SND_MOTU_SPEC_HAS_AESEBU_IFACE
) {
227 * All of v2 models have a pair of coaxial interfaces for digital in/out
228 * port. At 44.1/48.0/88.2/96.0 kHz, packets includes PCM from these
234 formats
->fixed_part_pcm_chunks
[0] = pcm_chunks
[0];
235 formats
->fixed_part_pcm_chunks
[1] = pcm_chunks
[1];
236 formats
->fixed_part_pcm_chunks
[2] = pcm_chunks
[2];
239 static void calculate_differed_part(struct snd_motu_packet_format
*formats
,
240 enum snd_motu_spec_flags flags
,
241 u32 data
, u32 mask
, u32 shift
)
243 unsigned char pcm_chunks
[2] = {0, 0};
246 * When optical interfaces are configured for S/PDIF (TOSLINK),
247 * the above PCM frames come from them, instead of coaxial
250 data
= (data
& mask
) >> shift
;
251 if (data
== V2_OPT_IFACE_MODE_ADAT
) {
252 if (flags
& SND_MOTU_SPEC_HAS_OPT_IFACE_A
) {
256 // 8pre has two sets of optical interface and doesn't reduce
257 // chunks for ADAT signals.
258 if (flags
& SND_MOTU_SPEC_HAS_OPT_IFACE_B
) {
263 /* At mode x4, no data chunks are supported in this part. */
264 formats
->differed_part_pcm_chunks
[0] = pcm_chunks
[0];
265 formats
->differed_part_pcm_chunks
[1] = pcm_chunks
[1];
268 static int v2_cache_packet_formats(struct snd_motu
*motu
)
274 err
= snd_motu_transaction_read(motu
, V2_IN_OUT_CONF_OFFSET
, ®
,
278 data
= be32_to_cpu(reg
);
280 calculate_fixed_part(&motu
->tx_packet_formats
, AMDTP_IN_STREAM
,
281 motu
->spec
->flags
, motu
->spec
->analog_in_ports
);
282 calculate_differed_part(&motu
->tx_packet_formats
, motu
->spec
->flags
,
283 data
, V2_OPT_IN_IFACE_MASK
, V2_OPT_IN_IFACE_SHIFT
);
285 calculate_fixed_part(&motu
->rx_packet_formats
, AMDTP_OUT_STREAM
,
286 motu
->spec
->flags
, motu
->spec
->analog_out_ports
);
287 calculate_differed_part(&motu
->rx_packet_formats
, motu
->spec
->flags
,
288 data
, V2_OPT_OUT_IFACE_MASK
, V2_OPT_OUT_IFACE_SHIFT
);
290 motu
->tx_packet_formats
.pcm_byte_offset
= 10;
291 motu
->rx_packet_formats
.pcm_byte_offset
= 10;
296 const struct snd_motu_protocol snd_motu_protocol_v2
= {
297 .get_clock_rate
= v2_get_clock_rate
,
298 .set_clock_rate
= v2_set_clock_rate
,
299 .get_clock_source
= v2_get_clock_source
,
300 .switch_fetching_mode
= v2_switch_fetching_mode
,
301 .cache_packet_formats
= v2_cache_packet_formats
,