1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features
4 * Copyright (c) 2019 Intel Corporation.
9 int isst_get_ctdp_levels(int cpu
, struct isst_pkg_ctdp
*pkg_dev
)
14 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
15 CONFIG_TDP_GET_LEVELS_INFO
, 0, 0, &resp
);
19 pkg_dev
->current_level
= 0;
25 debug_printf("cpu:%d CONFIG_TDP_GET_LEVELS_INFO resp:%x\n", cpu
, resp
);
27 pkg_dev
->version
= resp
& 0xff;
28 pkg_dev
->levels
= (resp
>> 8) & 0xff;
29 pkg_dev
->current_level
= (resp
>> 16) & 0xff;
30 pkg_dev
->locked
= !!(resp
& BIT(24));
31 pkg_dev
->enabled
= !!(resp
& BIT(31));
36 int isst_get_ctdp_control(int cpu
, int config_index
,
37 struct isst_pkg_ctdp_level_info
*ctdp_level
)
42 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
43 CONFIG_TDP_GET_TDP_CONTROL
, 0,
48 ctdp_level
->fact_support
= resp
& BIT(0);
49 ctdp_level
->pbf_support
= !!(resp
& BIT(1));
50 ctdp_level
->fact_enabled
= !!(resp
& BIT(16));
51 ctdp_level
->pbf_enabled
= !!(resp
& BIT(17));
54 "cpu:%d CONFIG_TDP_GET_TDP_CONTROL resp:%x fact_support:%d pbf_support: %d fact_enabled:%d pbf_enabled:%d\n",
55 cpu
, resp
, ctdp_level
->fact_support
, ctdp_level
->pbf_support
,
56 ctdp_level
->fact_enabled
, ctdp_level
->pbf_enabled
);
61 int isst_get_tdp_info(int cpu
, int config_index
,
62 struct isst_pkg_ctdp_level_info
*ctdp_level
)
67 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
, CONFIG_TDP_GET_TDP_INFO
,
68 0, config_index
, &resp
);
72 ctdp_level
->pkg_tdp
= resp
& GENMASK(14, 0);
73 ctdp_level
->tdp_ratio
= (resp
& GENMASK(23, 16)) >> 16;
76 "cpu:%d ctdp:%d CONFIG_TDP_GET_TDP_INFO resp:%x tdp_ratio:%d pkg_tdp:%d\n",
77 cpu
, config_index
, resp
, ctdp_level
->tdp_ratio
,
82 int isst_get_pwr_info(int cpu
, int config_index
,
83 struct isst_pkg_ctdp_level_info
*ctdp_level
)
88 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
, CONFIG_TDP_GET_PWR_INFO
,
89 0, config_index
, &resp
);
93 ctdp_level
->pkg_max_power
= resp
& GENMASK(14, 0);
94 ctdp_level
->pkg_min_power
= (resp
& GENMASK(30, 16)) >> 16;
97 "cpu:%d ctdp:%d CONFIG_TDP_GET_PWR_INFO resp:%x pkg_max_power:%d pkg_min_power:%d\n",
98 cpu
, config_index
, resp
, ctdp_level
->pkg_max_power
,
99 ctdp_level
->pkg_min_power
);
104 void isst_get_uncore_p0_p1_info(int cpu
, int config_index
,
105 struct isst_pkg_ctdp_level_info
*ctdp_level
)
109 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
110 CONFIG_TDP_GET_UNCORE_P0_P1_INFO
, 0,
111 config_index
, &resp
);
113 ctdp_level
->uncore_p0
= 0;
114 ctdp_level
->uncore_p1
= 0;
118 ctdp_level
->uncore_p0
= resp
& GENMASK(7, 0);
119 ctdp_level
->uncore_p1
= (resp
& GENMASK(15, 8)) >> 8;
121 "cpu:%d ctdp:%d CONFIG_TDP_GET_UNCORE_P0_P1_INFO resp:%x uncore p0:%d uncore p1:%d\n",
122 cpu
, config_index
, resp
, ctdp_level
->uncore_p0
,
123 ctdp_level
->uncore_p1
);
126 void isst_get_p1_info(int cpu
, int config_index
,
127 struct isst_pkg_ctdp_level_info
*ctdp_level
)
131 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
, CONFIG_TDP_GET_P1_INFO
, 0,
132 config_index
, &resp
);
134 ctdp_level
->sse_p1
= 0;
135 ctdp_level
->avx2_p1
= 0;
136 ctdp_level
->avx512_p1
= 0;
140 ctdp_level
->sse_p1
= resp
& GENMASK(7, 0);
141 ctdp_level
->avx2_p1
= (resp
& GENMASK(15, 8)) >> 8;
142 ctdp_level
->avx512_p1
= (resp
& GENMASK(23, 16)) >> 16;
144 "cpu:%d ctdp:%d CONFIG_TDP_GET_P1_INFO resp:%x sse_p1:%d avx2_p1:%d avx512_p1:%d\n",
145 cpu
, config_index
, resp
, ctdp_level
->sse_p1
,
146 ctdp_level
->avx2_p1
, ctdp_level
->avx512_p1
);
149 void isst_get_uncore_mem_freq(int cpu
, int config_index
,
150 struct isst_pkg_ctdp_level_info
*ctdp_level
)
154 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
, CONFIG_TDP_GET_MEM_FREQ
,
155 0, config_index
, &resp
);
157 ctdp_level
->mem_freq
= 0;
161 ctdp_level
->mem_freq
= resp
& GENMASK(7, 0);
163 "cpu:%d ctdp:%d CONFIG_TDP_GET_MEM_FREQ resp:%x uncore mem_freq:%d\n",
164 cpu
, config_index
, resp
, ctdp_level
->mem_freq
);
167 int isst_get_tjmax_info(int cpu
, int config_index
,
168 struct isst_pkg_ctdp_level_info
*ctdp_level
)
173 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
, CONFIG_TDP_GET_TJMAX_INFO
,
174 0, config_index
, &resp
);
178 ctdp_level
->t_proc_hot
= resp
& GENMASK(7, 0);
181 "cpu:%d ctdp:%d CONFIG_TDP_GET_TJMAX_INFO resp:%x t_proc_hot:%d\n",
182 cpu
, config_index
, resp
, ctdp_level
->t_proc_hot
);
187 int isst_get_coremask_info(int cpu
, int config_index
,
188 struct isst_pkg_ctdp_level_info
*ctdp_level
)
193 ctdp_level
->cpu_count
= 0;
194 for (i
= 0; i
< 2; ++i
) {
195 unsigned long long mask
;
198 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
199 CONFIG_TDP_GET_CORE_MASK
, 0,
200 (i
<< 8) | config_index
, &resp
);
205 "cpu:%d ctdp:%d mask:%d CONFIG_TDP_GET_CORE_MASK resp:%x\n",
206 cpu
, config_index
, i
, resp
);
208 mask
= (unsigned long long)resp
<< (32 * i
);
209 set_cpu_mask_from_punit_coremask(cpu
, mask
,
210 ctdp_level
->core_cpumask_size
,
211 ctdp_level
->core_cpumask
,
213 ctdp_level
->cpu_count
+= cpu_count
;
214 debug_printf("cpu:%d ctdp:%d mask:%d cpu count:%d\n", cpu
,
215 config_index
, i
, ctdp_level
->cpu_count
);
221 int isst_get_get_trl_from_msr(int cpu
, int *trl
)
223 unsigned long long msr_trl
;
226 ret
= isst_send_msr_command(cpu
, 0x1AD, 0, &msr_trl
);
230 trl
[0] = msr_trl
& GENMASK(7, 0);
231 trl
[1] = (msr_trl
& GENMASK(15, 8)) >> 8;
232 trl
[2] = (msr_trl
& GENMASK(23, 16)) >> 16;
233 trl
[3] = (msr_trl
& GENMASK(31, 24)) >> 24;
234 trl
[4] = (msr_trl
& GENMASK(39, 32)) >> 32;
235 trl
[5] = (msr_trl
& GENMASK(47, 40)) >> 40;
236 trl
[6] = (msr_trl
& GENMASK(55, 48)) >> 48;
237 trl
[7] = (msr_trl
& GENMASK(63, 56)) >> 56;
242 int isst_get_get_trl(int cpu
, int level
, int avx_level
, int *trl
)
244 unsigned int req
, resp
;
247 req
= level
| (avx_level
<< 16);
248 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
249 CONFIG_TDP_GET_TURBO_LIMIT_RATIOS
, 0, req
,
255 "cpu:%d CONFIG_TDP_GET_TURBO_LIMIT_RATIOS req:%x resp:%x\n",
258 trl
[0] = resp
& GENMASK(7, 0);
259 trl
[1] = (resp
& GENMASK(15, 8)) >> 8;
260 trl
[2] = (resp
& GENMASK(23, 16)) >> 16;
261 trl
[3] = (resp
& GENMASK(31, 24)) >> 24;
263 req
= level
| BIT(8) | (avx_level
<< 16);
264 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
265 CONFIG_TDP_GET_TURBO_LIMIT_RATIOS
, 0, req
,
270 debug_printf("cpu:%d CONFIG_TDP_GET_TURBO_LIMIT req:%x resp:%x\n", cpu
,
273 trl
[4] = resp
& GENMASK(7, 0);
274 trl
[5] = (resp
& GENMASK(15, 8)) >> 8;
275 trl
[6] = (resp
& GENMASK(23, 16)) >> 16;
276 trl
[7] = (resp
& GENMASK(31, 24)) >> 24;
281 int isst_get_trl_bucket_info(int cpu
, unsigned long long *buckets_info
)
285 debug_printf("cpu:%d bucket info via MSR\n", cpu
);
289 ret
= isst_send_msr_command(cpu
, 0x1ae, 0, buckets_info
);
293 debug_printf("cpu:%d bucket info via MSR successful 0x%llx\n", cpu
,
299 int isst_set_tdp_level_msr(int cpu
, int tdp_level
)
301 unsigned long long level
= tdp_level
;
304 debug_printf("cpu: tdp_level via MSR %d\n", cpu
, tdp_level
);
306 if (isst_get_config_tdp_lock_status(cpu
)) {
307 debug_printf("cpu: tdp_locked %d\n", cpu
);
312 return -1; /* invalid value */
314 ret
= isst_send_msr_command(cpu
, 0x64b, 1, &level
);
318 debug_printf("cpu: tdp_level via MSR successful %d\n", cpu
, tdp_level
);
323 int isst_set_tdp_level(int cpu
, int tdp_level
)
328 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
, CONFIG_TDP_SET_LEVEL
, 0,
331 return isst_set_tdp_level_msr(cpu
, tdp_level
);
336 int isst_get_pbf_info(int cpu
, int level
, struct isst_pbf_info
*pbf_info
)
338 int i
, ret
, core_cnt
, max
;
339 unsigned int req
, resp
;
341 pbf_info
->core_cpumask_size
= alloc_cpu_set(&pbf_info
->core_cpumask
);
343 core_cnt
= get_core_count(get_physical_package_id(cpu
), get_physical_die_id(cpu
));
344 max
= core_cnt
> 32 ? 2 : 1;
346 for (i
= 0; i
< max
; ++i
) {
347 unsigned long long mask
;
350 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
351 CONFIG_TDP_PBF_GET_CORE_MASK_INFO
,
352 0, (i
<< 8) | level
, &resp
);
357 "cpu:%d CONFIG_TDP_PBF_GET_CORE_MASK_INFO resp:%x\n",
360 mask
= (unsigned long long)resp
<< (32 * i
);
361 set_cpu_mask_from_punit_coremask(cpu
, mask
,
362 pbf_info
->core_cpumask_size
,
363 pbf_info
->core_cpumask
,
368 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
369 CONFIG_TDP_PBF_GET_P1HI_P1LO_INFO
, 0, req
,
374 debug_printf("cpu:%d CONFIG_TDP_PBF_GET_P1HI_P1LO_INFO resp:%x\n", cpu
,
377 pbf_info
->p1_low
= resp
& 0xff;
378 pbf_info
->p1_high
= (resp
& GENMASK(15, 8)) >> 8;
381 ret
= isst_send_mbox_command(
382 cpu
, CONFIG_TDP
, CONFIG_TDP_PBF_GET_TDP_INFO
, 0, req
, &resp
);
386 debug_printf("cpu:%d CONFIG_TDP_PBF_GET_TDP_INFO resp:%x\n", cpu
, resp
);
388 pbf_info
->tdp
= resp
& 0xffff;
391 ret
= isst_send_mbox_command(
392 cpu
, CONFIG_TDP
, CONFIG_TDP_PBF_GET_TJ_MAX_INFO
, 0, req
, &resp
);
396 debug_printf("cpu:%d CONFIG_TDP_PBF_GET_TJ_MAX_INFO resp:%x\n", cpu
,
398 pbf_info
->t_control
= (resp
>> 8) & 0xff;
399 pbf_info
->t_prochot
= resp
& 0xff;
404 void isst_get_pbf_info_complete(struct isst_pbf_info
*pbf_info
)
406 free_cpu_set(pbf_info
->core_cpumask
);
409 int isst_set_pbf_fact_status(int cpu
, int pbf
, int enable
)
411 struct isst_pkg_ctdp pkg_dev
;
412 struct isst_pkg_ctdp_level_info ctdp_level
;
414 unsigned int req
= 0, resp
;
417 ret
= isst_get_ctdp_levels(cpu
, &pkg_dev
);
419 debug_printf("cpu:%d No support for dynamic ISST\n", cpu
);
421 current_level
= pkg_dev
.current_level
;
423 ret
= isst_get_ctdp_control(cpu
, current_level
, &ctdp_level
);
428 if (ctdp_level
.fact_enabled
)
436 if (ctdp_level
.pbf_enabled
)
445 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
446 CONFIG_TDP_SET_TDP_CONTROL
, 0, req
, &resp
);
450 debug_printf("cpu:%d CONFIG_TDP_SET_TDP_CONTROL pbf/fact:%d req:%x\n",
456 int isst_get_fact_bucket_info(int cpu
, int level
,
457 struct isst_fact_bucket_info
*bucket_info
)
462 for (i
= 0; i
< 2; ++i
) {
465 ret
= isst_send_mbox_command(
467 CONFIG_TDP_GET_FACT_HP_TURBO_LIMIT_NUMCORES
, 0,
468 (i
<< 8) | level
, &resp
);
473 "cpu:%d CONFIG_TDP_GET_FACT_HP_TURBO_LIMIT_NUMCORES index:%d level:%d resp:%x\n",
474 cpu
, i
, level
, resp
);
476 for (j
= 0; j
< 4; ++j
) {
477 bucket_info
[j
+ (i
* 4)].high_priority_cores_count
=
478 (resp
>> (j
* 8)) & 0xff;
482 for (k
= 0; k
< 3; ++k
) {
483 for (i
= 0; i
< 2; ++i
) {
486 ret
= isst_send_mbox_command(
488 CONFIG_TDP_GET_FACT_HP_TURBO_LIMIT_RATIOS
, 0,
489 (k
<< 16) | (i
<< 8) | level
, &resp
);
494 "cpu:%d CONFIG_TDP_GET_FACT_HP_TURBO_LIMIT_RATIOS index:%d level:%d avx:%d resp:%x\n",
495 cpu
, i
, level
, k
, resp
);
497 for (j
= 0; j
< 4; ++j
) {
500 bucket_info
[j
+ (i
* 4)].sse_trl
=
501 (resp
>> (j
* 8)) & 0xff;
504 bucket_info
[j
+ (i
* 4)].avx_trl
=
505 (resp
>> (j
* 8)) & 0xff;
508 bucket_info
[j
+ (i
* 4)].avx512_trl
=
509 (resp
>> (j
* 8)) & 0xff;
521 int isst_get_fact_info(int cpu
, int level
, struct isst_fact_info
*fact_info
)
526 ret
= isst_send_mbox_command(cpu
, CONFIG_TDP
,
527 CONFIG_TDP_GET_FACT_LP_CLIPPING_RATIO
, 0,
532 debug_printf("cpu:%d CONFIG_TDP_GET_FACT_LP_CLIPPING_RATIO resp:%x\n",
535 fact_info
->lp_clipping_ratio_license_sse
= resp
& 0xff;
536 fact_info
->lp_clipping_ratio_license_avx2
= (resp
>> 8) & 0xff;
537 fact_info
->lp_clipping_ratio_license_avx512
= (resp
>> 16) & 0xff;
539 ret
= isst_get_fact_bucket_info(cpu
, level
, fact_info
->bucket_info
);
544 int isst_set_trl(int cpu
, unsigned long long trl
)
549 trl
= 0xFFFFFFFFFFFFFFFFULL
;
551 ret
= isst_send_msr_command(cpu
, 0x1AD, 1, &trl
);
558 int isst_set_trl_from_current_tdp(int cpu
, unsigned long long trl
)
560 unsigned long long msr_trl
;
566 struct isst_pkg_ctdp pkg_dev
;
570 ret
= isst_get_ctdp_levels(cpu
, &pkg_dev
);
574 ret
= isst_get_get_trl(cpu
, pkg_dev
.current_level
, 0, trl
);
579 for (i
= 0; i
< 8; ++i
) {
580 unsigned long long _trl
= trl
[i
];
582 msr_trl
|= (_trl
<< (i
* 8));
585 ret
= isst_send_msr_command(cpu
, 0x1AD, 1, &msr_trl
);
592 /* Return 1 if locked */
593 int isst_get_config_tdp_lock_status(int cpu
)
595 unsigned long long tdp_control
= 0;
598 ret
= isst_send_msr_command(cpu
, 0x64b, 0, &tdp_control
);
602 ret
= !!(tdp_control
& BIT(31));
607 void isst_get_process_ctdp_complete(int cpu
, struct isst_pkg_ctdp
*pkg_dev
)
611 if (!pkg_dev
->processed
)
614 for (i
= 0; i
< pkg_dev
->levels
; ++i
) {
615 struct isst_pkg_ctdp_level_info
*ctdp_level
;
617 ctdp_level
= &pkg_dev
->ctdp_level
[i
];
618 if (ctdp_level
->pbf_support
)
619 free_cpu_set(ctdp_level
->pbf_info
.core_cpumask
);
620 free_cpu_set(ctdp_level
->core_cpumask
);
624 int isst_get_process_ctdp(int cpu
, int tdp_level
, struct isst_pkg_ctdp
*pkg_dev
)
628 if (pkg_dev
->processed
)
631 ret
= isst_get_ctdp_levels(cpu
, pkg_dev
);
635 debug_printf("cpu: %d ctdp enable:%d current level: %d levels:%d\n",
636 cpu
, pkg_dev
->enabled
, pkg_dev
->current_level
,
639 for (i
= 0; i
<= pkg_dev
->levels
; ++i
) {
640 struct isst_pkg_ctdp_level_info
*ctdp_level
;
642 if (tdp_level
!= 0xff && i
!= tdp_level
)
645 debug_printf("cpu:%d Get Information for TDP level:%d\n", cpu
,
647 ctdp_level
= &pkg_dev
->ctdp_level
[i
];
649 ctdp_level
->level
= i
;
650 ctdp_level
->control_cpu
= cpu
;
651 ctdp_level
->pkg_id
= get_physical_package_id(cpu
);
652 ctdp_level
->die_id
= get_physical_die_id(cpu
);
654 ret
= isst_get_ctdp_control(cpu
, i
, ctdp_level
);
658 pkg_dev
->processed
= 1;
659 ctdp_level
->processed
= 1;
661 if (ctdp_level
->pbf_support
) {
662 ret
= isst_get_pbf_info(cpu
, i
, &ctdp_level
->pbf_info
);
664 ctdp_level
->pbf_found
= 1;
667 if (ctdp_level
->fact_support
) {
668 ret
= isst_get_fact_info(cpu
, i
,
669 &ctdp_level
->fact_info
);
674 if (!pkg_dev
->enabled
) {
677 freq
= get_cpufreq_base_freq(cpu
);
679 ctdp_level
->sse_p1
= freq
/ 100000;
680 ctdp_level
->tdp_ratio
= ctdp_level
->sse_p1
;
683 isst_get_get_trl_from_msr(cpu
, ctdp_level
->trl_sse_active_cores
);
684 isst_get_trl_bucket_info(cpu
, &ctdp_level
->buckets_info
);
688 ret
= isst_get_tdp_info(cpu
, i
, ctdp_level
);
692 ret
= isst_get_pwr_info(cpu
, i
, ctdp_level
);
696 ret
= isst_get_tjmax_info(cpu
, i
, ctdp_level
);
700 ctdp_level
->core_cpumask_size
=
701 alloc_cpu_set(&ctdp_level
->core_cpumask
);
702 ret
= isst_get_coremask_info(cpu
, i
, ctdp_level
);
706 ret
= isst_get_trl_bucket_info(cpu
, &ctdp_level
->buckets_info
);
710 ret
= isst_get_get_trl(cpu
, i
, 0,
711 ctdp_level
->trl_sse_active_cores
);
715 ret
= isst_get_get_trl(cpu
, i
, 1,
716 ctdp_level
->trl_avx_active_cores
);
720 ret
= isst_get_get_trl(cpu
, i
, 2,
721 ctdp_level
->trl_avx_512_active_cores
);
725 isst_get_uncore_p0_p1_info(cpu
, i
, ctdp_level
);
726 isst_get_p1_info(cpu
, i
, ctdp_level
);
727 isst_get_uncore_mem_freq(cpu
, i
, ctdp_level
);
733 int isst_clos_get_clos_information(int cpu
, int *enable
, int *type
)
738 ret
= isst_send_mbox_command(cpu
, CONFIG_CLOS
, CLOS_PM_QOS_CONFIG
, 0, 0,
743 debug_printf("cpu:%d CLOS_PM_QOS_CONFIG resp:%x\n", cpu
, resp
);
758 int isst_pm_qos_config(int cpu
, int enable_clos
, int priority_type
)
760 unsigned int req
, resp
;
764 struct isst_pkg_ctdp pkg_dev
;
765 struct isst_pkg_ctdp_level_info ctdp_level
;
767 ret
= isst_get_ctdp_levels(cpu
, &pkg_dev
);
769 debug_printf("isst_get_ctdp_levels\n");
773 ret
= isst_get_ctdp_control(cpu
, pkg_dev
.current_level
,
778 if (ctdp_level
.fact_enabled
) {
779 debug_printf("Turbo-freq feature must be disabled first\n");
784 ret
= isst_send_mbox_command(cpu
, CONFIG_CLOS
, CLOS_PM_QOS_CONFIG
, 0, 0,
789 debug_printf("cpu:%d CLOS_PM_QOS_CONFIG resp:%x\n", cpu
, resp
);
803 ret
= isst_send_mbox_command(cpu
, CONFIG_CLOS
, CLOS_PM_QOS_CONFIG
,
804 BIT(MBOX_CMD_WRITE_BIT
), req
, &resp
);
808 debug_printf("cpu:%d CLOS_PM_QOS_CONFIG priority type:%d req:%x\n", cpu
,
814 int isst_pm_get_clos(int cpu
, int clos
, struct isst_clos_config
*clos_config
)
819 ret
= isst_send_mbox_command(cpu
, CONFIG_CLOS
, CLOS_PM_CLOS
, clos
, 0,
824 clos_config
->pkg_id
= get_physical_package_id(cpu
);
825 clos_config
->die_id
= get_physical_die_id(cpu
);
827 clos_config
->epp
= resp
& 0x0f;
828 clos_config
->clos_prop_prio
= (resp
>> 4) & 0x0f;
829 clos_config
->clos_min
= (resp
>> 8) & 0xff;
830 clos_config
->clos_max
= (resp
>> 16) & 0xff;
831 clos_config
->clos_desired
= (resp
>> 24) & 0xff;
836 int isst_set_clos(int cpu
, int clos
, struct isst_clos_config
*clos_config
)
838 unsigned int req
, resp
;
842 req
= clos_config
->epp
& 0x0f;
843 req
|= (clos_config
->clos_prop_prio
& 0x0f) << 4;
844 req
|= (clos_config
->clos_min
& 0xff) << 8;
845 req
|= (clos_config
->clos_max
& 0xff) << 16;
846 req
|= (clos_config
->clos_desired
& 0xff) << 24;
848 param
= BIT(MBOX_CMD_WRITE_BIT
) | clos
;
850 ret
= isst_send_mbox_command(cpu
, CONFIG_CLOS
, CLOS_PM_CLOS
, param
, req
,
855 debug_printf("cpu:%d CLOS_PM_CLOS param:%x req:%x\n", cpu
, param
, req
);
860 int isst_clos_get_assoc_status(int cpu
, int *clos_id
)
866 core_id
= find_phy_core_num(cpu
);
869 ret
= isst_send_mbox_command(cpu
, CONFIG_CLOS
, CLOS_PQR_ASSOC
, param
, 0,
874 debug_printf("cpu:%d CLOS_PQR_ASSOC param:%x resp:%x\n", cpu
, param
,
876 *clos_id
= (resp
>> 16) & 0x03;
881 int isst_clos_associate(int cpu
, int clos_id
)
883 unsigned int req
, resp
;
887 req
= (clos_id
& 0x03) << 16;
888 core_id
= find_phy_core_num(cpu
);
889 param
= BIT(MBOX_CMD_WRITE_BIT
) | core_id
;
891 ret
= isst_send_mbox_command(cpu
, CONFIG_CLOS
, CLOS_PQR_ASSOC
, param
,
896 debug_printf("cpu:%d CLOS_PQR_ASSOC param:%x req:%x\n", cpu
, param
,