arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/uio_driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_intc.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/pm_domain.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/platform_data/sh_ipmmu.h>
  37 #include <mach/dma-register.h>
  38 #include <mach/irqs.h>
  39 #include <mach/sh7372.h>
  40 #include <mach/common.h>
  41 #include <asm/mach/map.h>
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/time.h>
  45
  46 static struct map_desc sh7372_io_desc[] __initdata = {
  47         /* create a 1:1 entity map for 0xe6xxxxxx
  48          * used by CPGA, INTC and PFC.
  49          */
  50         {
  51                 .virtual        = 0xe6000000,
  52                 .pfn            = __phys_to_pfn(0xe6000000),
  53                 .length         = 256 << 20,
  54                 .type           = MT_DEVICE_NONSHARED
  55         },
  56 };
  57
  58 void __init sh7372_map_io(void)
  59 {
  60         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  61 }
  62
  63 /* PFC */
  64 static struct resource sh7372_pfc_resources[] = {
  65         [0] = {
  66                 .start  = 0xe6050000,
  67                 .end    = 0xe6057fff,
  68                 .flags  = IORESOURCE_MEM,
  69         },
  70         [1] = {
  71                 .start  = 0xe605800c,
  72                 .end    = 0xe6058027,
  73                 .flags  = IORESOURCE_MEM,
  74         }
  75 };
  76
  77 static struct platform_device sh7372_pfc_device = {
  78         .name           = "pfc-sh7372",
  79         .id             = -1,
  80         .resource       = sh7372_pfc_resources,
  81         .num_resources  = ARRAY_SIZE(sh7372_pfc_resources),
  82 };
  83
  84 void __init sh7372_pinmux_init(void)
  85 {
  86         platform_device_register(&sh7372_pfc_device);
  87 }
  88
  89 /* SCIF */
  90 #define SH7372_SCIF(scif_type, index, baseaddr, irq)            \
  91 static struct plat_sci_port scif##index##_platform_data = {     \
  92         .type           = scif_type,                            \
  93         .flags          = UPF_BOOT_AUTOCONF,                    \
  94         .scscr          = SCSCR_RE | SCSCR_TE,                  \
  95 };                                                              \
  96                                                                 \
  97 static struct resource scif##index##_resources[] = {            \
  98         DEFINE_RES_MEM(baseaddr, 0x100),                        \
  99         DEFINE_RES_IRQ(irq),                                    \
 100 };                                                              \
 101                                                                 \
 102 static struct platform_device scif##index##_device = {          \
 103         .name           = "sh-sci",                             \
 104         .id             = index,                                \
 105         .resource       = scif##index##_resources,              \
 106         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 107         .dev            = {                                     \
 108                 .platform_data  = &scif##index##_platform_data, \
 109         },                                                      \
 110 }
 111
 112 SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
 113 SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
 114 SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
 115 SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
 116 SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
 117 SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
 118 SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
 119
 120 /* CMT */
 121 static struct sh_timer_config cmt2_platform_data = {
 122         .name = "CMT2",
 123         .channel_offset = 0x40,
 124         .timer_bit = 5,
 125         .clockevent_rating = 125,
 126         .clocksource_rating = 125,
 127 };
 128
 129 static struct resource cmt2_resources[] = {
 130         [0] = {
 131                 .name   = "CMT2",
 132                 .start  = 0xe6130040,
 133                 .end    = 0xe613004b,
 134                 .flags  = IORESOURCE_MEM,
 135         },
 136         [1] = {
 137                 .start  = evt2irq(0x0b80), /* CMT2 */
 138                 .flags  = IORESOURCE_IRQ,
 139         },
 140 };
 141
 142 static struct platform_device cmt2_device = {
 143         .name           = "sh_cmt",
 144         .id             = 2,
 145         .dev = {
 146                 .platform_data  = &cmt2_platform_data,
 147         },
 148         .resource       = cmt2_resources,
 149         .num_resources  = ARRAY_SIZE(cmt2_resources),
 150 };
 151
 152 /* TMU */
 153 static struct sh_timer_config tmu00_platform_data = {
 154         .name = "TMU00",
 155         .channel_offset = 0x4,
 156         .timer_bit = 0,
 157         .clockevent_rating = 200,
 158 };
 159
 160 static struct resource tmu00_resources[] = {
 161         [0] = {
 162                 .name   = "TMU00",
 163                 .start  = 0xfff60008,
 164                 .end    = 0xfff60013,
 165                 .flags  = IORESOURCE_MEM,
 166         },
 167         [1] = {
 168                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 169                 .flags  = IORESOURCE_IRQ,
 170         },
 171 };
 172
 173 static struct platform_device tmu00_device = {
 174         .name           = "sh_tmu",
 175         .id             = 0,
 176         .dev = {
 177                 .platform_data  = &tmu00_platform_data,
 178         },
 179         .resource       = tmu00_resources,
 180         .num_resources  = ARRAY_SIZE(tmu00_resources),
 181 };
 182
 183 static struct sh_timer_config tmu01_platform_data = {
 184         .name = "TMU01",
 185         .channel_offset = 0x10,
 186         .timer_bit = 1,
 187         .clocksource_rating = 200,
 188 };
 189
 190 static struct resource tmu01_resources[] = {
 191         [0] = {
 192                 .name   = "TMU01",
 193                 .start  = 0xfff60014,
 194                 .end    = 0xfff6001f,
 195                 .flags  = IORESOURCE_MEM,
 196         },
 197         [1] = {
 198                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 199                 .flags  = IORESOURCE_IRQ,
 200         },
 201 };
 202
 203 static struct platform_device tmu01_device = {
 204         .name           = "sh_tmu",
 205         .id             = 1,
 206         .dev = {
 207                 .platform_data  = &tmu01_platform_data,
 208         },
 209         .resource       = tmu01_resources,
 210         .num_resources  = ARRAY_SIZE(tmu01_resources),
 211 };
 212
 213 /* I2C */
 214 static struct resource iic0_resources[] = {
 215         [0] = {
 216                 .name   = "IIC0",
 217                 .start  = 0xFFF20000,
 218                 .end    = 0xFFF20425 - 1,
 219                 .flags  = IORESOURCE_MEM,
 220         },
 221         [1] = {
 222                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 223                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 224                 .flags  = IORESOURCE_IRQ,
 225         },
 226 };
 227
 228 static struct platform_device iic0_device = {
 229         .name           = "i2c-sh_mobile",
 230         .id             = 0, /* "i2c0" clock */
 231         .num_resources  = ARRAY_SIZE(iic0_resources),
 232         .resource       = iic0_resources,
 233 };
 234
 235 static struct resource iic1_resources[] = {
 236         [0] = {
 237                 .name   = "IIC1",
 238                 .start  = 0xE6C20000,
 239                 .end    = 0xE6C20425 - 1,
 240                 .flags  = IORESOURCE_MEM,
 241         },
 242         [1] = {
 243                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 244                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 245                 .flags  = IORESOURCE_IRQ,
 246         },
 247 };
 248
 249 static struct platform_device iic1_device = {
 250         .name           = "i2c-sh_mobile",
 251         .id             = 1, /* "i2c1" clock */
 252         .num_resources  = ARRAY_SIZE(iic1_resources),
 253         .resource       = iic1_resources,
 254 };
 255
 256 /* DMA */
 257 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 258         {
 259                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 260                 .addr           = 0xe6c40020,
 261                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 262                 .mid_rid        = 0x21,
 263         }, {
 264                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 265                 .addr           = 0xe6c40024,
 266                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 267                 .mid_rid        = 0x22,
 268         }, {
 269                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 270                 .addr           = 0xe6c50020,
 271                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 272                 .mid_rid        = 0x25,
 273         }, {
 274                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 275                 .addr           = 0xe6c50024,
 276                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 277                 .mid_rid        = 0x26,
 278         }, {
 279                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 280                 .addr           = 0xe6c60020,
 281                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 282                 .mid_rid        = 0x29,
 283         }, {
 284                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 285                 .addr           = 0xe6c60024,
 286                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 287                 .mid_rid        = 0x2a,
 288         }, {
 289                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 290                 .addr           = 0xe6c70020,
 291                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 292                 .mid_rid        = 0x2d,
 293         }, {
 294                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 295                 .addr           = 0xe6c70024,
 296                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 297                 .mid_rid        = 0x2e,
 298         }, {
 299                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 300                 .addr           = 0xe6c80020,
 301                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 302                 .mid_rid        = 0x39,
 303         }, {
 304                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 305                 .addr           = 0xe6c80024,
 306                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 307                 .mid_rid        = 0x3a,
 308         }, {
 309                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 310                 .addr           = 0xe6cb0020,
 311                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 312                 .mid_rid        = 0x35,
 313         }, {
 314                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 315                 .addr           = 0xe6cb0024,
 316                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 317                 .mid_rid        = 0x36,
 318         }, {
 319                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 320                 .addr           = 0xe6c30040,
 321                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 322                 .mid_rid        = 0x3d,
 323         }, {
 324                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 325                 .addr           = 0xe6c30060,
 326                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 327                 .mid_rid        = 0x3e,
 328         }, {
 329                 .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
 330                 .addr           = 0xe6a30050,
 331                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 332                 .mid_rid        = 0x83,
 333         }, {
 334                 .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
 335                 .addr           = 0xe6a30050,
 336                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 337                 .mid_rid        = 0x83,
 338         }, {
 339                 .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
 340                 .addr           = 0xe6a30060,
 341                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 342                 .mid_rid        = 0x87,
 343         }, {
 344                 .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
 345                 .addr           = 0xe6a30060,
 346                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 347                 .mid_rid        = 0x87,
 348         }, {
 349                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 350                 .addr           = 0xe6850030,
 351                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 352                 .mid_rid        = 0xc1,
 353         }, {
 354                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 355                 .addr           = 0xe6850030,
 356                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 357                 .mid_rid        = 0xc2,
 358         }, {
 359                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 360                 .addr           = 0xe6860030,
 361                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 362                 .mid_rid        = 0xc9,
 363         }, {
 364                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 365                 .addr           = 0xe6860030,
 366                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 367                 .mid_rid        = 0xca,
 368         }, {
 369                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 370                 .addr           = 0xe6870030,
 371                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 372                 .mid_rid        = 0xcd,
 373         }, {
 374                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 375                 .addr           = 0xe6870030,
 376                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 377                 .mid_rid        = 0xce,
 378         }, {
 379                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 380                 .addr           = 0xfe1f0024,
 381                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 382                 .mid_rid        = 0xb1,
 383         }, {
 384                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 385                 .addr           = 0xfe1f0020,
 386                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 387                 .mid_rid        = 0xb2,
 388         }, {
 389                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 390                 .addr           = 0xe6bd0034,
 391                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 392                 .mid_rid        = 0xd1,
 393         }, {
 394                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 395                 .addr           = 0xe6bd0034,
 396                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 397                 .mid_rid        = 0xd2,
 398         },
 399 };
 400
 401 #define SH7372_CHCLR (0x220 - 0x20)
 402
 403 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 404         {
 405                 .offset = 0,
 406                 .dmars = 0,
 407                 .dmars_bit = 0,
 408                 .chclr_offset = SH7372_CHCLR + 0,
 409         }, {
 410                 .offset = 0x10,
 411                 .dmars = 0,
 412                 .dmars_bit = 8,
 413                 .chclr_offset = SH7372_CHCLR + 0x10,
 414         }, {
 415                 .offset = 0x20,
 416                 .dmars = 4,
 417                 .dmars_bit = 0,
 418                 .chclr_offset = SH7372_CHCLR + 0x20,
 419         }, {
 420                 .offset = 0x30,
 421                 .dmars = 4,
 422                 .dmars_bit = 8,
 423                 .chclr_offset = SH7372_CHCLR + 0x30,
 424         }, {
 425                 .offset = 0x50,
 426                 .dmars = 8,
 427                 .dmars_bit = 0,
 428                 .chclr_offset = SH7372_CHCLR + 0x50,
 429         }, {
 430                 .offset = 0x60,
 431                 .dmars = 8,
 432                 .dmars_bit = 8,
 433                 .chclr_offset = SH7372_CHCLR + 0x60,
 434         }
 435 };
 436
 437 static struct sh_dmae_pdata dma_platform_data = {
 438         .slave          = sh7372_dmae_slaves,
 439         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 440         .channel        = sh7372_dmae_channels,
 441         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 442         .ts_low_shift   = TS_LOW_SHIFT,
 443         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 444         .ts_high_shift  = TS_HI_SHIFT,
 445         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 446         .ts_shift       = dma_ts_shift,
 447         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 448         .dmaor_init     = DMAOR_DME,
 449         .chclr_present  = 1,
 450 };
 451
 452 /* Resource order important! */
 453 static struct resource sh7372_dmae0_resources[] = {
 454         {
 455                 /* Channel registers and DMAOR */
 456                 .start  = 0xfe008020,
 457                 .end    = 0xfe00828f,
 458                 .flags  = IORESOURCE_MEM,
 459         },
 460         {
 461                 /* DMARSx */
 462                 .start  = 0xfe009000,
 463                 .end    = 0xfe00900b,
 464                 .flags  = IORESOURCE_MEM,
 465         },
 466         {
 467                 .name   = "error_irq",
 468                 .start  = evt2irq(0x20c0),
 469                 .end    = evt2irq(0x20c0),
 470                 .flags  = IORESOURCE_IRQ,
 471         },
 472         {
 473                 /* IRQ for channels 0-5 */
 474                 .start  = evt2irq(0x2000),
 475                 .end    = evt2irq(0x20a0),
 476                 .flags  = IORESOURCE_IRQ,
 477         },
 478 };
 479
 480 /* Resource order important! */
 481 static struct resource sh7372_dmae1_resources[] = {
 482         {
 483                 /* Channel registers and DMAOR */
 484                 .start  = 0xfe018020,
 485                 .end    = 0xfe01828f,
 486                 .flags  = IORESOURCE_MEM,
 487         },
 488         {
 489                 /* DMARSx */
 490                 .start  = 0xfe019000,
 491                 .end    = 0xfe01900b,
 492                 .flags  = IORESOURCE_MEM,
 493         },
 494         {
 495                 .name   = "error_irq",
 496                 .start  = evt2irq(0x21c0),
 497                 .end    = evt2irq(0x21c0),
 498                 .flags  = IORESOURCE_IRQ,
 499         },
 500         {
 501                 /* IRQ for channels 0-5 */
 502                 .start  = evt2irq(0x2100),
 503                 .end    = evt2irq(0x21a0),
 504                 .flags  = IORESOURCE_IRQ,
 505         },
 506 };
 507
 508 /* Resource order important! */
 509 static struct resource sh7372_dmae2_resources[] = {
 510         {
 511                 /* Channel registers and DMAOR */
 512                 .start  = 0xfe028020,
 513                 .end    = 0xfe02828f,
 514                 .flags  = IORESOURCE_MEM,
 515         },
 516         {
 517                 /* DMARSx */
 518                 .start  = 0xfe029000,
 519                 .end    = 0xfe02900b,
 520                 .flags  = IORESOURCE_MEM,
 521         },
 522         {
 523                 .name   = "error_irq",
 524                 .start  = evt2irq(0x22c0),
 525                 .end    = evt2irq(0x22c0),
 526                 .flags  = IORESOURCE_IRQ,
 527         },
 528         {
 529                 /* IRQ for channels 0-5 */
 530                 .start  = evt2irq(0x2200),
 531                 .end    = evt2irq(0x22a0),
 532                 .flags  = IORESOURCE_IRQ,
 533         },
 534 };
 535
 536 static struct platform_device dma0_device = {
 537         .name           = "sh-dma-engine",
 538         .id             = 0,
 539         .resource       = sh7372_dmae0_resources,
 540         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 541         .dev            = {
 542                 .platform_data  = &dma_platform_data,
 543         },
 544 };
 545
 546 static struct platform_device dma1_device = {
 547         .name           = "sh-dma-engine",
 548         .id             = 1,
 549         .resource       = sh7372_dmae1_resources,
 550         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 551         .dev            = {
 552                 .platform_data  = &dma_platform_data,
 553         },
 554 };
 555
 556 static struct platform_device dma2_device = {
 557         .name           = "sh-dma-engine",
 558         .id             = 2,
 559         .resource       = sh7372_dmae2_resources,
 560         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 561         .dev            = {
 562                 .platform_data  = &dma_platform_data,
 563         },
 564 };
 565
 566 /*
 567  * USB-DMAC
 568  */
 569 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 570         {
 571                 .offset = 0,
 572         }, {
 573                 .offset = 0x20,
 574         },
 575 };
 576
 577 /* USB DMAC0 */
 578 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 579         {
 580                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 581                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 582         }, {
 583                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 584                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 585         },
 586 };
 587
 588 static struct sh_dmae_pdata usb_dma0_platform_data = {
 589         .slave          = sh7372_usb_dmae0_slaves,
 590         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 591         .channel        = sh7372_usb_dmae_channels,
 592         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 593         .ts_low_shift   = USBTS_LOW_SHIFT,
 594         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 595         .ts_high_shift  = USBTS_HI_SHIFT,
 596         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 597         .ts_shift       = dma_usbts_shift,
 598         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 599         .dmaor_init     = DMAOR_DME,
 600         .chcr_offset    = 0x14,
 601         .chcr_ie_bit    = 1 << 5,
 602         .dmaor_is_32bit = 1,
 603         .needs_tend_set = 1,
 604         .no_dmars       = 1,
 605         .slave_only     = 1,
 606 };
 607
 608 static struct resource sh7372_usb_dmae0_resources[] = {
 609         {
 610                 /* Channel registers and DMAOR */
 611                 .start  = 0xe68a0020,
 612                 .end    = 0xe68a0064 - 1,
 613                 .flags  = IORESOURCE_MEM,
 614         },
 615         {
 616                 /* VCR/SWR/DMICR */
 617                 .start  = 0xe68a0000,
 618                 .end    = 0xe68a0014 - 1,
 619                 .flags  = IORESOURCE_MEM,
 620         },
 621         {
 622                 /* IRQ for channels */
 623                 .start  = evt2irq(0x0a00),
 624                 .end    = evt2irq(0x0a00),
 625                 .flags  = IORESOURCE_IRQ,
 626         },
 627 };
 628
 629 static struct platform_device usb_dma0_device = {
 630         .name           = "sh-dma-engine",
 631         .id             = 3,
 632         .resource       = sh7372_usb_dmae0_resources,
 633         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 634         .dev            = {
 635                 .platform_data  = &usb_dma0_platform_data,
 636         },
 637 };
 638
 639 /* USB DMAC1 */
 640 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 641         {
 642                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 643                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 644         }, {
 645                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 646                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 647         },
 648 };
 649
 650 static struct sh_dmae_pdata usb_dma1_platform_data = {
 651         .slave          = sh7372_usb_dmae1_slaves,
 652         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 653         .channel        = sh7372_usb_dmae_channels,
 654         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 655         .ts_low_shift   = USBTS_LOW_SHIFT,
 656         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 657         .ts_high_shift  = USBTS_HI_SHIFT,
 658         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 659         .ts_shift       = dma_usbts_shift,
 660         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 661         .dmaor_init     = DMAOR_DME,
 662         .chcr_offset    = 0x14,
 663         .chcr_ie_bit    = 1 << 5,
 664         .dmaor_is_32bit = 1,
 665         .needs_tend_set = 1,
 666         .no_dmars       = 1,
 667         .slave_only     = 1,
 668 };
 669
 670 static struct resource sh7372_usb_dmae1_resources[] = {
 671         {
 672                 /* Channel registers and DMAOR */
 673                 .start  = 0xe68c0020,
 674                 .end    = 0xe68c0064 - 1,
 675                 .flags  = IORESOURCE_MEM,
 676         },
 677         {
 678                 /* VCR/SWR/DMICR */
 679                 .start  = 0xe68c0000,
 680                 .end    = 0xe68c0014 - 1,
 681                 .flags  = IORESOURCE_MEM,
 682         },
 683         {
 684                 /* IRQ for channels */
 685                 .start  = evt2irq(0x1d00),
 686                 .end    = evt2irq(0x1d00),
 687                 .flags  = IORESOURCE_IRQ,
 688         },
 689 };
 690
 691 static struct platform_device usb_dma1_device = {
 692         .name           = "sh-dma-engine",
 693         .id             = 4,
 694         .resource       = sh7372_usb_dmae1_resources,
 695         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 696         .dev            = {
 697                 .platform_data  = &usb_dma1_platform_data,
 698         },
 699 };
 700
 701 /* VPU */
 702 static struct uio_info vpu_platform_data = {
 703         .name = "VPU5HG",
 704         .version = "0",
 705         .irq = intcs_evt2irq(0x980),
 706 };
 707
 708 static struct resource vpu_resources[] = {
 709         [0] = {
 710                 .name   = "VPU",
 711                 .start  = 0xfe900000,
 712                 .end    = 0xfe900157,
 713                 .flags  = IORESOURCE_MEM,
 714         },
 715 };
 716
 717 static struct platform_device vpu_device = {
 718         .name           = "uio_pdrv_genirq",
 719         .id             = 0,
 720         .dev = {
 721                 .platform_data  = &vpu_platform_data,
 722         },
 723         .resource       = vpu_resources,
 724         .num_resources  = ARRAY_SIZE(vpu_resources),
 725 };
 726
 727 /* VEU0 */
 728 static struct uio_info veu0_platform_data = {
 729         .name = "VEU0",
 730         .version = "0",
 731         .irq = intcs_evt2irq(0x700),
 732 };
 733
 734 static struct resource veu0_resources[] = {
 735         [0] = {
 736                 .name   = "VEU0",
 737                 .start  = 0xfe920000,
 738                 .end    = 0xfe9200cb,
 739                 .flags  = IORESOURCE_MEM,
 740         },
 741 };
 742
 743 static struct platform_device veu0_device = {
 744         .name           = "uio_pdrv_genirq",
 745         .id             = 1,
 746         .dev = {
 747                 .platform_data  = &veu0_platform_data,
 748         },
 749         .resource       = veu0_resources,
 750         .num_resources  = ARRAY_SIZE(veu0_resources),
 751 };
 752
 753 /* VEU1 */
 754 static struct uio_info veu1_platform_data = {
 755         .name = "VEU1",
 756         .version = "0",
 757         .irq = intcs_evt2irq(0x720),
 758 };
 759
 760 static struct resource veu1_resources[] = {
 761         [0] = {
 762                 .name   = "VEU1",
 763                 .start  = 0xfe924000,
 764                 .end    = 0xfe9240cb,
 765                 .flags  = IORESOURCE_MEM,
 766         },
 767 };
 768
 769 static struct platform_device veu1_device = {
 770         .name           = "uio_pdrv_genirq",
 771         .id             = 2,
 772         .dev = {
 773                 .platform_data  = &veu1_platform_data,
 774         },
 775         .resource       = veu1_resources,
 776         .num_resources  = ARRAY_SIZE(veu1_resources),
 777 };
 778
 779 /* VEU2 */
 780 static struct uio_info veu2_platform_data = {
 781         .name = "VEU2",
 782         .version = "0",
 783         .irq = intcs_evt2irq(0x740),
 784 };
 785
 786 static struct resource veu2_resources[] = {
 787         [0] = {
 788                 .name   = "VEU2",
 789                 .start  = 0xfe928000,
 790                 .end    = 0xfe928307,
 791                 .flags  = IORESOURCE_MEM,
 792         },
 793 };
 794
 795 static struct platform_device veu2_device = {
 796         .name           = "uio_pdrv_genirq",
 797         .id             = 3,
 798         .dev = {
 799                 .platform_data  = &veu2_platform_data,
 800         },
 801         .resource       = veu2_resources,
 802         .num_resources  = ARRAY_SIZE(veu2_resources),
 803 };
 804
 805 /* VEU3 */
 806 static struct uio_info veu3_platform_data = {
 807         .name = "VEU3",
 808         .version = "0",
 809         .irq = intcs_evt2irq(0x760),
 810 };
 811
 812 static struct resource veu3_resources[] = {
 813         [0] = {
 814                 .name   = "VEU3",
 815                 .start  = 0xfe92c000,
 816                 .end    = 0xfe92c307,
 817                 .flags  = IORESOURCE_MEM,
 818         },
 819 };
 820
 821 static struct platform_device veu3_device = {
 822         .name           = "uio_pdrv_genirq",
 823         .id             = 4,
 824         .dev = {
 825                 .platform_data  = &veu3_platform_data,
 826         },
 827         .resource       = veu3_resources,
 828         .num_resources  = ARRAY_SIZE(veu3_resources),
 829 };
 830
 831 /* JPU */
 832 static struct uio_info jpu_platform_data = {
 833         .name = "JPU",
 834         .version = "0",
 835         .irq = intcs_evt2irq(0x560),
 836 };
 837
 838 static struct resource jpu_resources[] = {
 839         [0] = {
 840                 .name   = "JPU",
 841                 .start  = 0xfe980000,
 842                 .end    = 0xfe9902d3,
 843                 .flags  = IORESOURCE_MEM,
 844         },
 845 };
 846
 847 static struct platform_device jpu_device = {
 848         .name           = "uio_pdrv_genirq",
 849         .id             = 5,
 850         .dev = {
 851                 .platform_data  = &jpu_platform_data,
 852         },
 853         .resource       = jpu_resources,
 854         .num_resources  = ARRAY_SIZE(jpu_resources),
 855 };
 856
 857 /* SPU2DSP0 */
 858 static struct uio_info spu0_platform_data = {
 859         .name = "SPU2DSP0",
 860         .version = "0",
 861         .irq = evt2irq(0x1800),
 862 };
 863
 864 static struct resource spu0_resources[] = {
 865         [0] = {
 866                 .name   = "SPU2DSP0",
 867                 .start  = 0xfe200000,
 868                 .end    = 0xfe2fffff,
 869                 .flags  = IORESOURCE_MEM,
 870         },
 871 };
 872
 873 static struct platform_device spu0_device = {
 874         .name           = "uio_pdrv_genirq",
 875         .id             = 6,
 876         .dev = {
 877                 .platform_data  = &spu0_platform_data,
 878         },
 879         .resource       = spu0_resources,
 880         .num_resources  = ARRAY_SIZE(spu0_resources),
 881 };
 882
 883 /* SPU2DSP1 */
 884 static struct uio_info spu1_platform_data = {
 885         .name = "SPU2DSP1",
 886         .version = "0",
 887         .irq = evt2irq(0x1820),
 888 };
 889
 890 static struct resource spu1_resources[] = {
 891         [0] = {
 892                 .name   = "SPU2DSP1",
 893                 .start  = 0xfe300000,
 894                 .end    = 0xfe3fffff,
 895                 .flags  = IORESOURCE_MEM,
 896         },
 897 };
 898
 899 static struct platform_device spu1_device = {
 900         .name           = "uio_pdrv_genirq",
 901         .id             = 7,
 902         .dev = {
 903                 .platform_data  = &spu1_platform_data,
 904         },
 905         .resource       = spu1_resources,
 906         .num_resources  = ARRAY_SIZE(spu1_resources),
 907 };
 908
 909 /* IPMMUI (an IPMMU module for ICB/LMB) */
 910 static struct resource ipmmu_resources[] = {
 911         [0] = {
 912                 .name   = "IPMMUI",
 913                 .start  = 0xfe951000,
 914                 .end    = 0xfe9510ff,
 915                 .flags  = IORESOURCE_MEM,
 916         },
 917 };
 918
 919 static const char * const ipmmu_dev_names[] = {
 920         "sh_mobile_lcdc_fb.0",
 921         "sh_mobile_lcdc_fb.1",
 922         "sh_mobile_ceu.0",
 923         "uio_pdrv_genirq.0",
 924         "uio_pdrv_genirq.1",
 925         "uio_pdrv_genirq.2",
 926         "uio_pdrv_genirq.3",
 927         "uio_pdrv_genirq.4",
 928         "uio_pdrv_genirq.5",
 929 };
 930
 931 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 932         .dev_names = ipmmu_dev_names,
 933         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 934 };
 935
 936 static struct platform_device ipmmu_device = {
 937         .name           = "ipmmu",
 938         .id             = -1,
 939         .dev = {
 940                 .platform_data = &ipmmu_platform_data,
 941         },
 942         .resource       = ipmmu_resources,
 943         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 944 };
 945
 946 static struct platform_device *sh7372_early_devices[] __initdata = {
 947         &scif0_device,
 948         &scif1_device,
 949         &scif2_device,
 950         &scif3_device,
 951         &scif4_device,
 952         &scif5_device,
 953         &scif6_device,
 954         &cmt2_device,
 955         &tmu00_device,
 956         &tmu01_device,
 957         &ipmmu_device,
 958 };
 959
 960 static struct platform_device *sh7372_late_devices[] __initdata = {
 961         &iic0_device,
 962         &iic1_device,
 963         &dma0_device,
 964         &dma1_device,
 965         &dma2_device,
 966         &usb_dma0_device,
 967         &usb_dma1_device,
 968         &vpu_device,
 969         &veu0_device,
 970         &veu1_device,
 971         &veu2_device,
 972         &veu3_device,
 973         &jpu_device,
 974         &spu0_device,
 975         &spu1_device,
 976 };
 977
 978 void __init sh7372_add_standard_devices(void)
 979 {
 980         struct pm_domain_device domain_devices[] = {
 981                 { "A3RV", &vpu_device, },
 982                 { "A4MP", &spu0_device, },
 983                 { "A4MP", &spu1_device, },
 984                 { "A3SP", &scif0_device, },
 985                 { "A3SP", &scif1_device, },
 986                 { "A3SP", &scif2_device, },
 987                 { "A3SP", &scif3_device, },
 988                 { "A3SP", &scif4_device, },
 989                 { "A3SP", &scif5_device, },
 990                 { "A3SP", &scif6_device, },
 991                 { "A3SP", &iic1_device, },
 992                 { "A3SP", &dma0_device, },
 993                 { "A3SP", &dma1_device, },
 994                 { "A3SP", &dma2_device, },
 995                 { "A3SP", &usb_dma0_device, },
 996                 { "A3SP", &usb_dma1_device, },
 997                 { "A4R", &iic0_device, },
 998                 { "A4R", &veu0_device, },
 999                 { "A4R", &veu1_device, },
1000                 { "A4R", &veu2_device, },
1001                 { "A4R", &veu3_device, },
1002                 { "A4R", &jpu_device, },
1003                 { "A4R", &tmu00_device, },
1004                 { "A4R", &tmu01_device, },
1005         };
1006
1007         sh7372_init_pm_domains();
1008
1009         platform_add_devices(sh7372_early_devices,
1010                             ARRAY_SIZE(sh7372_early_devices));
1011
1012         platform_add_devices(sh7372_late_devices,
1013                             ARRAY_SIZE(sh7372_late_devices));
1014
1015         rmobile_add_devices_to_domains(domain_devices,
1016                                        ARRAY_SIZE(domain_devices));
1017 }
1018
1019 void __init sh7372_earlytimer_init(void)
1020 {
1021         sh7372_clock_init();
1022         shmobile_earlytimer_init();
1023 }
1024
1025 void __init sh7372_add_early_devices(void)
1026 {
1027         early_platform_add_devices(sh7372_early_devices,
1028                                    ARRAY_SIZE(sh7372_early_devices));
1029
1030         /* setup early console here as well */
1031         shmobile_setup_console();
1032 }
1033
1034 #ifdef CONFIG_USE_OF
1035
1036 void __init sh7372_add_early_devices_dt(void)
1037 {
1038         shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1039
1040         early_platform_add_devices(sh7372_early_devices,
1041                                    ARRAY_SIZE(sh7372_early_devices));
1042
1043         /* setup early console here as well */
1044         shmobile_setup_console();
1045 }
1046
1047 void __init sh7372_add_standard_devices_dt(void)
1048 {
1049         /* clocks are setup late during boot in the case of DT */
1050         sh7372_clock_init();
1051
1052         platform_add_devices(sh7372_early_devices,
1053                             ARRAY_SIZE(sh7372_early_devices));
1054
1055         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1056 }
1057
1058 static const char *sh7372_boards_compat_dt[] __initdata = {
1059         "renesas,sh7372",
1060         NULL,
1061 };
1062
1063 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1064         .map_io         = sh7372_map_io,
1065         .init_early     = sh7372_add_early_devices_dt,
1066         .nr_irqs        = NR_IRQS_LEGACY,
1067         .init_irq       = sh7372_init_irq,
1068         .handle_irq     = shmobile_handle_irq_intc,
1069         .init_machine   = sh7372_add_standard_devices_dt,
1070         .dt_compat      = sh7372_boards_compat_dt,
1071 MACHINE_END
1072
1073 #endif /* CONFIG_USE_OF */