arch/arm/mach-ux500/board-mop500-pins.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License terms: GNU General Public License (GPL) version 2
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/bug.h>
  10 #include <linux/string.h>
  11 #include <linux/pinctrl/machine.h>
  12 #include <linux/pinctrl/pinconf-generic.h>
  13
  14 #include <asm/mach-types.h>
  15
  16 #include "board-mop500.h"
  17
  18 /* These simply sets bias for pins */
  19 #define BIAS(a,b) static unsigned long a[] = { b }
  20
  21 BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
  22 BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
  23 BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
  24
  25 #define AB8500_MUX_HOG(group, func) \
  26         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
  27 #define AB8500_PIN_HOG(pin, conf) \
  28         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
  29
  30 #define AB8500_MUX_STATE(group, func, dev, state) \
  31         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
  32 #define AB8500_PIN_STATE(pin, conf, dev, state) \
  33         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
  34
  35 #define AB8505_MUX_HOG(group, func) \
  36         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
  37 #define AB8505_PIN_HOG(pin, conf) \
  38         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
  39
  40 #define AB8505_MUX_STATE(group, func, dev, state) \
  41         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
  42 #define AB8505_PIN_STATE(pin, conf, dev, state) \
  43         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
  44
  45 static struct pinctrl_map __initdata ab8500_pinmap[] = {
  46         /* Sysclkreq2 */
  47         AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
  48         AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
  49         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
  50         AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
  51         AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
  52
  53         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
  54         AB8500_MUX_HOG("gpio2_a_1", "gpio"),
  55         AB8500_PIN_HOG("GPIO2_T9", in_pd),
  56
  57         /* Sysclkreq4 */
  58         AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
  59         AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
  60         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
  61         AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
  62         AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
  63
  64         /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
  65         AB8500_MUX_HOG("gpio4_a_1", "gpio"),
  66         AB8500_PIN_HOG("GPIO4_W2", in_pd),
  67
  68         /*
  69          * pins 6,7,8 and 9 are muxed in YCBCR0123
  70          * configured in INPUT PULL UP
  71          */
  72         AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
  73         AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
  74         AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
  75         AB8500_PIN_HOG("GPIO8_W18", in_nopull),
  76         AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
  77
  78         /*
  79          * pins 10,11,12 and 13 are muxed in GPIO
  80          * configured in INPUT PULL DOWN
  81          */
  82         AB8500_MUX_HOG("gpio10_d_1", "gpio"),
  83         AB8500_PIN_HOG("GPIO10_U17", in_pd),
  84
  85         AB8500_MUX_HOG("gpio11_d_1", "gpio"),
  86         AB8500_PIN_HOG("GPIO11_AA18", in_pd),
  87
  88         AB8500_MUX_HOG("gpio12_d_1", "gpio"),
  89         AB8500_PIN_HOG("GPIO12_U16", in_pd),
  90
  91         AB8500_MUX_HOG("gpio13_d_1", "gpio"),
  92         AB8500_PIN_HOG("GPIO13_W17", in_pd),
  93
  94         /*
  95          * pins 14,15 are muxed in PWM1 and PWM2
  96          * configured in INPUT PULL DOWN
  97          */
  98         AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
  99         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 100
 101         AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
 102         AB8500_PIN_HOG("GPIO15_B17", in_pd),
 103
 104         /*
 105          * pins 16 is muxed in GPIO
 106          * configured in INPUT PULL DOWN
 107          */
 108         AB8500_MUX_HOG("gpio16_a_1", "gpio"),
 109         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 110
 111         /*
 112          * pins 17,18,19 and 20 are muxed in AUDIO interface 1
 113          * configured in INPUT PULL DOWN
 114          */
 115         AB8500_MUX_HOG("adi1_d_1", "adi1"),
 116         AB8500_PIN_HOG("GPIO17_P5", in_pd),
 117         AB8500_PIN_HOG("GPIO18_R5", in_pd),
 118         AB8500_PIN_HOG("GPIO19_U5", in_pd),
 119         AB8500_PIN_HOG("GPIO20_T5", in_pd),
 120
 121         /*
 122          * pins 21,22 and 23 are muxed in USB UICC
 123          * configured in INPUT PULL DOWN
 124          */
 125         AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
 126         AB8500_PIN_HOG("GPIO21_H19", in_pd),
 127         AB8500_PIN_HOG("GPIO22_G20", in_pd),
 128         AB8500_PIN_HOG("GPIO23_G19", in_pd),
 129
 130         /*
 131          * pins 24,25 are muxed in GPIO
 132          * configured in INPUT PULL DOWN
 133          */
 134         AB8500_MUX_HOG("gpio24_a_1", "gpio"),
 135         AB8500_PIN_HOG("GPIO24_T14", in_pd),
 136
 137         AB8500_MUX_HOG("gpio25_a_1", "gpio"),
 138         AB8500_PIN_HOG("GPIO25_R16", in_pd),
 139
 140         /*
 141          * pins 26 is muxed in GPIO
 142          * configured in OUTPUT LOW
 143          */
 144         AB8500_MUX_HOG("gpio26_d_1", "gpio"),
 145         AB8500_PIN_HOG("GPIO26_M16", out_lo),
 146
 147         /*
 148          * pins 27,28 are muxed in DMIC12
 149          * configured in INPUT PULL DOWN
 150          */
 151         AB8500_MUX_HOG("dmic12_d_1", "dmic"),
 152         AB8500_PIN_HOG("GPIO27_J6", in_pd),
 153         AB8500_PIN_HOG("GPIO28_K6", in_pd),
 154
 155         /*
 156          * pins 29,30 are muxed in DMIC34
 157          * configured in INPUT PULL DOWN
 158          */
 159         AB8500_MUX_HOG("dmic34_d_1", "dmic"),
 160         AB8500_PIN_HOG("GPIO29_G6", in_pd),
 161         AB8500_PIN_HOG("GPIO30_H6", in_pd),
 162
 163         /*
 164          * pins 31,32 are muxed in DMIC56
 165          * configured in INPUT PULL DOWN
 166          */
 167         AB8500_MUX_HOG("dmic56_d_1", "dmic"),
 168         AB8500_PIN_HOG("GPIO31_F5", in_pd),
 169         AB8500_PIN_HOG("GPIO32_G5", in_pd),
 170
 171         /*
 172          * pins 34 is muxed in EXTCPENA
 173          * configured INPUT PULL DOWN
 174          */
 175         AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
 176         AB8500_PIN_HOG("GPIO34_R17", in_pd),
 177
 178         /*
 179          * pins 35 is muxed in GPIO
 180          * configured in OUTPUT LOW
 181          */
 182         AB8500_MUX_HOG("gpio35_d_1", "gpio"),
 183         AB8500_PIN_HOG("GPIO35_W15", in_pd),
 184
 185         /*
 186          * pins 36,37,38 and 39 are muxed in GPIO
 187          * configured in INPUT PULL DOWN
 188          */
 189         AB8500_MUX_HOG("gpio36_a_1", "gpio"),
 190         AB8500_PIN_HOG("GPIO36_A17", in_pd),
 191
 192         AB8500_MUX_HOG("gpio37_a_1", "gpio"),
 193         AB8500_PIN_HOG("GPIO37_E15", in_pd),
 194
 195         AB8500_MUX_HOG("gpio38_a_1", "gpio"),
 196         AB8500_PIN_HOG("GPIO38_C17", in_pd),
 197
 198         AB8500_MUX_HOG("gpio39_a_1", "gpio"),
 199         AB8500_PIN_HOG("GPIO39_E16", in_pd),
 200
 201         /*
 202          * pins 40 and 41 are muxed in MODCSLSDA
 203          * configured INPUT PULL DOWN
 204          */
 205         AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
 206         AB8500_PIN_HOG("GPIO40_T19", in_pd),
 207         AB8500_PIN_HOG("GPIO41_U19", in_pd),
 208
 209         /*
 210          * pins 42 is muxed in GPIO
 211          * configured INPUT PULL DOWN
 212          */
 213         AB8500_MUX_HOG("gpio42_a_1", "gpio"),
 214         AB8500_PIN_HOG("GPIO42_U2", in_pd),
 215 };
 216
 217 static struct pinctrl_map __initdata ab8505_pinmap[] = {
 218         /* Sysclkreq2 */
 219         AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
 220         AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
 221         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
 222         AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
 223         AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
 224
 225         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
 226         AB8505_MUX_HOG("gpio2_a_1", "gpio"),
 227         AB8505_PIN_HOG("GPIO2_R5", in_pd),
 228
 229         /* Sysclkreq4 */
 230         AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
 231         AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
 232         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
 233         AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
 234         AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
 235
 236         AB8505_MUX_HOG("gpio10_d_1", "gpio"),
 237         AB8505_PIN_HOG("GPIO10_B16", in_pd),
 238
 239         AB8505_MUX_HOG("gpio11_d_1", "gpio"),
 240         AB8505_PIN_HOG("GPIO11_B17", in_pd),
 241
 242         AB8505_MUX_HOG("gpio13_d_1", "gpio"),
 243         AB8505_PIN_HOG("GPIO13_D17", in_nopull),
 244
 245         AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
 246         AB8505_PIN_HOG("GPIO14_C16", in_pd),
 247
 248         AB8505_MUX_HOG("adi2_d_1", "adi2"),
 249         AB8505_PIN_HOG("GPIO17_P2", in_pd),
 250         AB8505_PIN_HOG("GPIO18_N3", in_pd),
 251         AB8505_PIN_HOG("GPIO19_T1", in_pd),
 252         AB8505_PIN_HOG("GPIO20_P3", in_pd),
 253
 254         AB8505_MUX_HOG("gpio34_a_1", "gpio"),
 255         AB8505_PIN_HOG("GPIO34_H14", in_pd),
 256
 257         AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
 258         AB8505_PIN_HOG("GPIO40_J15", in_pd),
 259         AB8505_PIN_HOG("GPIO41_J14", in_pd),
 260
 261         AB8505_MUX_HOG("gpio50_d_1", "gpio"),
 262         AB8505_PIN_HOG("GPIO50_L4", in_nopull),
 263
 264         AB8505_MUX_HOG("resethw_d_1", "resethw"),
 265         AB8505_PIN_HOG("GPIO52_D16", in_pd),
 266
 267         AB8505_MUX_HOG("service_d_1", "service"),
 268         AB8505_PIN_HOG("GPIO53_D15", in_pd),
 269 };
 270
 271 void __init mop500_pinmaps_init(void)
 272 {
 273         if (machine_is_u8520())
 274                 pinctrl_register_mappings(ab8505_pinmap,
 275                                           ARRAY_SIZE(ab8505_pinmap));
 276         else
 277                 pinctrl_register_mappings(ab8500_pinmap,
 278                                           ARRAY_SIZE(ab8500_pinmap));
 279 }
 280
 281 void __init snowball_pinmaps_init(void)
 282 {
 283         pinctrl_register_mappings(ab8500_pinmap,
 284                                   ARRAY_SIZE(ab8500_pinmap));
 285 }
 286
 287 void __init hrefv60_pinmaps_init(void)
 288 {
 289         pinctrl_register_mappings(ab8500_pinmap,
 290                                   ARRAY_SIZE(ab8500_pinmap));
 291 }