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mei: fix regressions caused by removing ext_msg
[linux/fpc-iii.git] / arch / tile / kernel / pci_gx.c
bloba97a6452b812cdb9681d49fb4130ab3403ff3d2d
1 /*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/mmzone.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/capability.h>
22 #include <linux/sched.h>
23 #include <linux/errno.h>
24 #include <linux/irq.h>
25 #include <linux/msi.h>
26 #include <linux/io.h>
27 #include <linux/uaccess.h>
28 #include <linux/ctype.h>
29
30 #include <asm/processor.h>
31 #include <asm/sections.h>
32 #include <asm/byteorder.h>
33
34 #include <gxio/iorpc_globals.h>
35 #include <gxio/kiorpc.h>
36 #include <gxio/trio.h>
37 #include <gxio/iorpc_trio.h>
38 #include <hv/drv_trio_intf.h>
39
40 #include <arch/sim.h>
41
42 /*
43 * This file containes the routines to search for PCI buses,
44 * enumerate the buses, and configure any attached devices.
45 */
46
47 #define DEBUG_PCI_CFG 0
48
49 #if DEBUG_PCI_CFG
50 #define TRACE_CFG_WR(size, val, bus, dev, func, offset) \
51 pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
52 size, val, bus, dev, func, offset & 0xFFF);
53 #define TRACE_CFG_RD(size, val, bus, dev, func, offset) \
54 pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
55 size, val, bus, dev, func, offset & 0xFFF);
56 #else
57 #define TRACE_CFG_WR(...)
58 #define TRACE_CFG_RD(...)
59 #endif
60
61 static int pci_probe = 1;
62
63 /* Information on the PCIe RC ports configuration. */
64 static int pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
65
66 /*
67 * On some platforms with one or more Gx endpoint ports, we need to
68 * delay the PCIe RC port probe for a few seconds to work around
69 * a HW PCIe link-training bug. The exact delay is specified with
70 * a kernel boot argument in the form of "pcie_rc_delay=T,P,S",
71 * where T is the TRIO instance number, P is the port number and S is
72 * the delay in seconds. If the argument is specified, but the delay is
73 * not provided, the value will be DEFAULT_RC_DELAY.
74 */
75 static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
76
77 /* Default number of seconds that the PCIe RC port probe can be delayed. */
78 #define DEFAULT_RC_DELAY 10
79
80 /* The PCI I/O space size in each PCI domain. */
81 #define IO_SPACE_SIZE 0x10000
82
83 /* Provide shorter versions of some very long constant names. */
84 #define AUTO_CONFIG_RC \
85 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC
86 #define AUTO_CONFIG_RC_G1 \
87 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1
88 #define AUTO_CONFIG_EP \
89 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT
90 #define AUTO_CONFIG_EP_G1 \
91 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1
92
93 /* Array of the PCIe ports configuration info obtained from the BIB. */
94 struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO];
95
96 /* Number of configured TRIO instances. */
97 int num_trio_shims;
98
99 /* All drivers share the TRIO contexts defined here. */
100 gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
101
102 /* Pointer to an array of PCIe RC controllers. */
103 struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
104 int num_rc_controllers;
105
106 static struct pci_ops tile_cfg_ops;
107
108 /* Mask of CPUs that should receive PCIe interrupts. */
109 static struct cpumask intr_cpus_map;
110
111 /* We don't need to worry about the alignment of resources. */
112 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
113 resource_size_t size,
114 resource_size_t align)
115 {
116 return res->start;
117 }
118 EXPORT_SYMBOL(pcibios_align_resource);
119
120 /*
121 * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
122 * For now, we simply send interrupts to non-dataplane CPUs.
123 * We may implement methods to allow user to specify the target CPUs,
124 * e.g. via boot arguments.
125 */
126 static int tile_irq_cpu(int irq)
127 {
128 unsigned int count;
129 int i = 0;
130 int cpu;
131
132 count = cpumask_weight(&intr_cpus_map);
133 if (unlikely(count == 0)) {
134 pr_warning("intr_cpus_map empty, interrupts will be"
135 " delievered to dataplane tiles\n");
136 return irq % (smp_height * smp_width);
137 }
138
139 count = irq % count;
140 for_each_cpu(cpu, &intr_cpus_map) {
141 if (i++ == count)
142 break;
143 }
144 return cpu;
145 }
146
147 /* Open a file descriptor to the TRIO shim. */
148 static int tile_pcie_open(int trio_index)
149 {
150 gxio_trio_context_t *context = &trio_contexts[trio_index];
151 int ret;
152 int mac;
153
154 /* This opens a file descriptor to the TRIO shim. */
155 ret = gxio_trio_init(context, trio_index);
156 if (ret < 0)
157 goto gxio_trio_init_failure;
158
159 /* Allocate an ASID for the kernel. */
160 ret = gxio_trio_alloc_asids(context, 1, 0, 0);
161 if (ret < 0) {
162 pr_err("PCI: ASID alloc failure on TRIO %d, give up\n",
163 trio_index);
164 goto asid_alloc_failure;
165 }
166
167 context->asid = ret;
168
169 #ifdef USE_SHARED_PCIE_CONFIG_REGION
170 /*
171 * Alloc a PIO region for config access, shared by all MACs per TRIO.
172 * This shouldn't fail since the kernel is supposed to the first
173 * client of the TRIO's PIO regions.
174 */
175 ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0);
176 if (ret < 0) {
177 pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n",
178 trio_index);
179 goto pio_alloc_failure;
180 }
181
182 context->pio_cfg_index = ret;
183
184 /*
185 * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter
186 * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR.
187 */
188 ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index,
189 0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
190 if (ret < 0) {
191 pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n",
192 trio_index);
193 goto pio_alloc_failure;
194 }
195 #endif
196
197 /* Get the properties of the PCIe ports on this TRIO instance. */
198 ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]);
199 if (ret < 0) {
200 pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d,"
201 " on TRIO %d\n", ret, trio_index);
202 goto get_port_property_failure;
203 }
204
205 context->mmio_base_mac =
206 iorpc_ioremap(context->fd, 0, HV_TRIO_CONFIG_IOREMAP_SIZE);
207 if (context->mmio_base_mac == NULL) {
208 pr_err("PCI: TRIO config space mapping failure, error %d,"
209 " on TRIO %d\n", ret, trio_index);
210 ret = -ENOMEM;
211
212 goto trio_mmio_mapping_failure;
213 }
214
215 /* Check the port strap state which will override the BIB setting. */
216 for (mac = 0; mac < TILEGX_TRIO_PCIES; mac++) {
217 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
218 unsigned int reg_offset;
219
220 /* Ignore ports that are not specified in the BIB. */
221 if (!pcie_ports[trio_index].ports[mac].allow_rc &&
222 !pcie_ports[trio_index].ports[mac].allow_ep)
223 continue;
224
225 reg_offset =
226 (TRIO_PCIE_INTFC_PORT_CONFIG <<
227 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
228 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
229 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
230 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
231
232 port_config.word =
233 __gxio_mmio_read(context->mmio_base_mac + reg_offset);
234
235 if (port_config.strap_state != AUTO_CONFIG_RC &&
236 port_config.strap_state != AUTO_CONFIG_RC_G1) {
237 /*
238 * If this is really intended to be an EP port, record
239 * it so that the endpoint driver will know about it.
240 */
241 if (port_config.strap_state == AUTO_CONFIG_EP ||
242 port_config.strap_state == AUTO_CONFIG_EP_G1)
243 pcie_ports[trio_index].ports[mac].allow_ep = 1;
244 }
245 }
246
247 return ret;
248
249 trio_mmio_mapping_failure:
250 get_port_property_failure:
251 asid_alloc_failure:
252 #ifdef USE_SHARED_PCIE_CONFIG_REGION
253 pio_alloc_failure:
254 #endif
255 hv_dev_close(context->fd);
256 gxio_trio_init_failure:
257 context->fd = -1;
258
259 return ret;
260 }
261
262 static int __init tile_trio_init(void)
263 {
264 int i;
265
266 /* We loop over all the TRIO shims. */
267 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
268 if (tile_pcie_open(i) < 0)
269 continue;
270 num_trio_shims++;
271 }
272
273 return 0;
274 }
275 postcore_initcall(tile_trio_init);
276
277 static void tilegx_legacy_irq_ack(struct irq_data *d)
278 {
279 __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
280 }
281
282 static void tilegx_legacy_irq_mask(struct irq_data *d)
283 {
284 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
285 }
286
287 static void tilegx_legacy_irq_unmask(struct irq_data *d)
288 {
289 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
290 }
291
292 static struct irq_chip tilegx_legacy_irq_chip = {
293 .name = "tilegx_legacy_irq",
294 .irq_ack = tilegx_legacy_irq_ack,
295 .irq_mask = tilegx_legacy_irq_mask,
296 .irq_unmask = tilegx_legacy_irq_unmask,
297
298 /* TBD: support set_affinity. */
299 };
300
301 /*
302 * This is a wrapper function of the kernel level-trigger interrupt
303 * handler handle_level_irq() for PCI legacy interrupts. The TRIO
304 * is configured such that only INTx Assert interrupts are proxied
305 * to Linux which just calls handle_level_irq() after clearing the
306 * MAC INTx Assert status bit associated with this interrupt.
307 */
308 static void trio_handle_level_irq(unsigned int irq, struct irq_desc *desc)
309 {
310 struct pci_controller *controller = irq_desc_get_handler_data(desc);
311 gxio_trio_context_t *trio_context = controller->trio;
312 uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
313 int mac = controller->mac;
314 unsigned int reg_offset;
315 uint64_t level_mask;
316
317 handle_level_irq(irq, desc);
318
319 /*
320 * Clear the INTx Level status, otherwise future interrupts are
321 * not sent.
322 */
323 reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS <<
324 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
325 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
326 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
327 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
328
329 level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx;
330
331 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask);
332 }
333
334 /*
335 * Create kernel irqs and set up the handlers for the legacy interrupts.
336 * Also some minimum initialization for the MSI support.
337 */
338 static int tile_init_irqs(struct pci_controller *controller)
339 {
340 int i;
341 int j;
342 int irq;
343 int result;
344
345 cpumask_copy(&intr_cpus_map, cpu_online_mask);
346
347
348 for (i = 0; i < 4; i++) {
349 gxio_trio_context_t *context = controller->trio;
350 int cpu;
351
352 /* Ask the kernel to allocate an IRQ. */
353 irq = create_irq();
354 if (irq < 0) {
355 pr_err("PCI: no free irq vectors, failed for %d\n", i);
356
357 goto free_irqs;
358 }
359 controller->irq_intx_table[i] = irq;
360
361 /* Distribute the 4 IRQs to different tiles. */
362 cpu = tile_irq_cpu(irq);
363
364 /* Configure the TRIO intr binding for this IRQ. */
365 result = gxio_trio_config_legacy_intr(context, cpu_x(cpu),
366 cpu_y(cpu), KERNEL_PL,
367 irq, controller->mac, i);
368 if (result < 0) {
369 pr_err("PCI: MAC intx config failed for %d\n", i);
370
371 goto free_irqs;
372 }
373
374 /* Register the IRQ handler with the kernel. */
375 irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip,
376 trio_handle_level_irq);
377 irq_set_chip_data(irq, (void *)(uint64_t)i);
378 irq_set_handler_data(irq, controller);
379 }
380
381 return 0;
382
383 free_irqs:
384 for (j = 0; j < i; j++)
385 destroy_irq(controller->irq_intx_table[j]);
386
387 return -1;
388 }
389
390 /*
391 * Return 1 if the port is strapped to operate in RC mode.
392 */
393 static int
394 strapped_for_rc(gxio_trio_context_t *trio_context, int mac)
395 {
396 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
397 unsigned int reg_offset;
398
399 /* Check the port configuration. */
400 reg_offset =
401 (TRIO_PCIE_INTFC_PORT_CONFIG <<
402 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
403 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
404 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
405 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
406 port_config.word =
407 __gxio_mmio_read(trio_context->mmio_base_mac + reg_offset);
408
409 if (port_config.strap_state == AUTO_CONFIG_RC ||
410 port_config.strap_state == AUTO_CONFIG_RC_G1)
411 return 1;
412 else
413 return 0;
414 }
415
416 /*
417 * Find valid controllers and fill in pci_controller structs for each
418 * of them.
419 *
420 * Return the number of controllers discovered.
421 */
422 int __init tile_pci_init(void)
423 {
424 int ctl_index = 0;
425 int i, j;
426
427 if (!pci_probe) {
428 pr_info("PCI: disabled by boot argument\n");
429 return 0;
430 }
431
432 pr_info("PCI: Searching for controllers...\n");
433
434 if (num_trio_shims == 0 || sim_is_simulator())
435 return 0;
436
437 /*
438 * Now determine which PCIe ports are configured to operate in RC
439 * mode. There is a differece in the port configuration capability
440 * between the Gx36 and Gx72 devices.
441 *
442 * The Gx36 has configuration capability for each of the 3 PCIe
443 * interfaces (disable, auto endpoint, auto RC, etc.).
444 * On the Gx72, you can only select one of the 3 PCIe interfaces per
445 * TRIO to train automatically. Further, the allowable training modes
446 * are reduced to four options (auto endpoint, auto RC, stream x1,
447 * stream x4).
448 *
449 * For Gx36 ports, it must be allowed to be in RC mode by the
450 * Board Information Block, and the hardware strapping pins must be
451 * set to RC mode.
452 *
453 * For Gx72 ports, the port will operate in RC mode if either of the
454 * following is true:
455 * 1. It is allowed to be in RC mode by the Board Information Block,
456 * and the BIB doesn't allow the EP mode.
457 * 2. It is allowed to be in either the RC or the EP mode by the BIB,
458 * and the hardware strapping pin is set to RC mode.
459 */
460 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
461 gxio_trio_context_t *context = &trio_contexts[i];
462
463 if (context->fd < 0)
464 continue;
465
466 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
467 int is_rc = 0;
468
469 if (pcie_ports[i].is_gx72 &&
470 pcie_ports[i].ports[j].allow_rc) {
471 if (!pcie_ports[i].ports[j].allow_ep ||
472 strapped_for_rc(context, j))
473 is_rc = 1;
474 } else if (pcie_ports[i].ports[j].allow_rc &&
475 strapped_for_rc(context, j)) {
476 is_rc = 1;
477 }
478 if (is_rc) {
479 pcie_rc[i][j] = 1;
480 num_rc_controllers++;
481 }
482 }
483 }
484
485 /* Return if no PCIe ports are configured to operate in RC mode. */
486 if (num_rc_controllers == 0)
487 return 0;
488
489 /* Set the TRIO pointer and MAC index for each PCIe RC port. */
490 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
491 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
492 if (pcie_rc[i][j]) {
493 pci_controllers[ctl_index].trio =
494 &trio_contexts[i];
495 pci_controllers[ctl_index].mac = j;
496 pci_controllers[ctl_index].trio_index = i;
497 ctl_index++;
498 if (ctl_index == num_rc_controllers)
499 goto out;
500 }
501 }
502 }
503
504 out:
505 /* Configure each PCIe RC port. */
506 for (i = 0; i < num_rc_controllers; i++) {
507
508 /* Configure the PCIe MAC to run in RC mode. */
509 struct pci_controller *controller = &pci_controllers[i];
510
511 controller->index = i;
512 controller->ops = &tile_cfg_ops;
513
514 controller->io_space.start = PCIBIOS_MIN_IO +
515 (i * IO_SPACE_SIZE);
516 controller->io_space.end = controller->io_space.start +
517 IO_SPACE_SIZE - 1;
518 BUG_ON(controller->io_space.end > IO_SPACE_LIMIT);
519 controller->io_space.flags = IORESOURCE_IO;
520 snprintf(controller->io_space_name,
521 sizeof(controller->io_space_name),
522 "PCI I/O domain %d", i);
523 controller->io_space.name = controller->io_space_name;
524
525 /*
526 * The PCI memory resource is located above the PA space.
527 * For every host bridge, the BAR window or the MMIO aperture
528 * is in range [3GB, 4GB - 1] of a 4GB space beyond the
529 * PA space.
530 */
531 controller->mem_offset = TILE_PCI_MEM_START +
532 (i * TILE_PCI_BAR_WINDOW_TOP);
533 controller->mem_space.start = controller->mem_offset +
534 TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE;
535 controller->mem_space.end = controller->mem_offset +
536 TILE_PCI_BAR_WINDOW_TOP - 1;
537 controller->mem_space.flags = IORESOURCE_MEM;
538 snprintf(controller->mem_space_name,
539 sizeof(controller->mem_space_name),
540 "PCI mem domain %d", i);
541 controller->mem_space.name = controller->mem_space_name;
542 }
543
544 return num_rc_controllers;
545 }
546
547 /*
548 * (pin - 1) converts from the PCI standard's [1:4] convention to
549 * a normal [0:3] range.
550 */
551 static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin)
552 {
553 struct pci_controller *controller =
554 (struct pci_controller *)dev->sysdata;
555 return controller->irq_intx_table[pin - 1];
556 }
557
558 static void fixup_read_and_payload_sizes(struct pci_controller *controller)
559 {
560 gxio_trio_context_t *trio_context = controller->trio;
561 struct pci_bus *root_bus = controller->root_bus;
562 TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control;
563 TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap;
564 unsigned int reg_offset;
565 struct pci_bus *child;
566 int mac;
567 int err;
568
569 mac = controller->mac;
570
571 /* Set our max read request size to be 4KB. */
572 reg_offset =
573 (TRIO_PCIE_RC_DEVICE_CONTROL <<
574 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
575 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
576 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
577 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
578
579 dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
580 reg_offset);
581 dev_control.max_read_req_sz = 5;
582 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
583 dev_control.word);
584
585 /*
586 * Set the max payload size supported by this Gx PCIe MAC.
587 * Though Gx PCIe supports Max Payload Size of up to 1024 bytes,
588 * experiments have shown that setting MPS to 256 yields the
589 * best performance.
590 */
591 reg_offset =
592 (TRIO_PCIE_RC_DEVICE_CAP <<
593 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
594 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
595 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
596 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
597
598 rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
599 reg_offset);
600 rc_dev_cap.mps_sup = 1;
601 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
602 rc_dev_cap.word);
603
604 /* Configure PCI Express MPS setting. */
605 list_for_each_entry(child, &root_bus->children, node)
606 pcie_bus_configure_settings(child);
607
608 /*
609 * Set the mac_config register in trio based on the MPS/MRS of the link.
610 */
611 reg_offset =
612 (TRIO_PCIE_RC_DEVICE_CONTROL <<
613 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
614 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
615 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
616 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
617
618 dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
619 reg_offset);
620
621 err = gxio_trio_set_mps_mrs(trio_context,
622 dev_control.max_payload_size,
623 dev_control.max_read_req_sz,
624 mac);
625 if (err < 0) {
626 pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, "
627 "MAC %d on TRIO %d\n",
628 mac, controller->trio_index);
629 }
630 }
631
632 static int setup_pcie_rc_delay(char *str)
633 {
634 unsigned long delay = 0;
635 unsigned long trio_index;
636 unsigned long mac;
637
638 if (str == NULL || !isdigit(*str))
639 return -EINVAL;
640 trio_index = simple_strtoul(str, (char **)&str, 10);
641 if (trio_index >= TILEGX_NUM_TRIO)
642 return -EINVAL;
643
644 if (*str != ',')
645 return -EINVAL;
646
647 str++;
648 if (!isdigit(*str))
649 return -EINVAL;
650 mac = simple_strtoul(str, (char **)&str, 10);
651 if (mac >= TILEGX_TRIO_PCIES)
652 return -EINVAL;
653
654 if (*str != '\0') {
655 if (*str != ',')
656 return -EINVAL;
657
658 str++;
659 if (!isdigit(*str))
660 return -EINVAL;
661 delay = simple_strtoul(str, (char **)&str, 10);
662 }
663
664 rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY;
665 return 0;
666 }
667 early_param("pcie_rc_delay", setup_pcie_rc_delay);
668
669 /* PCI initialization entry point, called by subsys_initcall. */
670 int __init pcibios_init(void)
671 {
672 resource_size_t offset;
673 LIST_HEAD(resources);
674 int next_busno;
675 int i;
676
677 tile_pci_init();
678
679 if (num_rc_controllers == 0)
680 return 0;
681
682 /*
683 * Delay a bit in case devices aren't ready. Some devices are
684 * known to require at least 20ms here, but we use a more
685 * conservative value.
686 */
687 msleep(250);
688
689 /* Scan all of the recorded PCI controllers. */
690 for (next_busno = 0, i = 0; i < num_rc_controllers; i++) {
691 struct pci_controller *controller = &pci_controllers[i];
692 gxio_trio_context_t *trio_context = controller->trio;
693 TRIO_PCIE_INTFC_PORT_STATUS_t port_status;
694 TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl;
695 struct pci_bus *bus;
696 unsigned int reg_offset;
697 unsigned int class_code_revision;
698 int trio_index;
699 int mac;
700 int ret;
701
702 if (trio_context->fd < 0)
703 continue;
704
705 trio_index = controller->trio_index;
706 mac = controller->mac;
707
708 /*
709 * Check for PCIe link-up status to decide if we need
710 * to force the link to come up.
711 */
712 reg_offset =
713 (TRIO_PCIE_INTFC_PORT_STATUS <<
714 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
715 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
716 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
717 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
718
719 port_status.word =
720 __gxio_mmio_read(trio_context->mmio_base_mac +
721 reg_offset);
722 if (!port_status.dl_up) {
723 if (rc_delay[trio_index][mac]) {
724 pr_info("Delaying PCIe RC TRIO init %d sec"
725 " on MAC %d on TRIO %d\n",
726 rc_delay[trio_index][mac], mac,
727 trio_index);
728 msleep(rc_delay[trio_index][mac] * 1000);
729 }
730 ret = gxio_trio_force_rc_link_up(trio_context, mac);
731 if (ret < 0)
732 pr_err("PCI: PCIE_FORCE_LINK_UP failure, "
733 "MAC %d on TRIO %d\n", mac, trio_index);
734 }
735
736 pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n", i,
737 trio_index, controller->mac);
738
739 /* Delay the bus probe if needed. */
740 if (rc_delay[trio_index][mac]) {
741 pr_info("Delaying PCIe RC bus enumerating %d sec"
742 " on MAC %d on TRIO %d\n",
743 rc_delay[trio_index][mac], mac,
744 trio_index);
745 msleep(rc_delay[trio_index][mac] * 1000);
746 } else {
747 /*
748 * Wait a bit here because some EP devices
749 * take longer to come up.
750 */
751 msleep(1000);
752 }
753
754 /* Check for PCIe link-up status again. */
755 port_status.word =
756 __gxio_mmio_read(trio_context->mmio_base_mac +
757 reg_offset);
758 if (!port_status.dl_up) {
759 if (pcie_ports[trio_index].ports[mac].removable) {
760 pr_info("PCI: link is down, MAC %d on TRIO %d\n",
761 mac, trio_index);
762 pr_info("This is expected if no PCIe card"
763 " is connected to this link\n");
764 } else
765 pr_err("PCI: link is down, MAC %d on TRIO %d\n",
766 mac, trio_index);
767 continue;
768 }
769
770 /*
771 * Ensure that the link can come out of L1 power down state.
772 * Strictly speaking, this is needed only in the case of
773 * heavy RC-initiated DMAs.
774 */
775 reg_offset =
776 (TRIO_PCIE_INTFC_TX_FIFO_CTL <<
777 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
778 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
779 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
780 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
781 tx_fifo_ctl.word =
782 __gxio_mmio_read(trio_context->mmio_base_mac +
783 reg_offset);
784 tx_fifo_ctl.min_p_credits = 0;
785 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset,
786 tx_fifo_ctl.word);
787
788 /*
789 * Change the device ID so that Linux bus crawl doesn't confuse
790 * the internal bridge with any Tilera endpoints.
791 */
792 reg_offset =
793 (TRIO_PCIE_RC_DEVICE_ID_VEN_ID <<
794 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
795 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
796 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
797 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
798
799 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
800 (TILERA_GX36_RC_DEV_ID <<
801 TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) |
802 TILERA_VENDOR_ID);
803
804 /* Set the internal P2P bridge class code. */
805 reg_offset =
806 (TRIO_PCIE_RC_REVISION_ID <<
807 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
808 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
809 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
810 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
811
812 class_code_revision =
813 __gxio_mmio_read32(trio_context->mmio_base_mac +
814 reg_offset);
815 class_code_revision = (class_code_revision & 0xff) |
816 (PCI_CLASS_BRIDGE_PCI << 16);
817
818 __gxio_mmio_write32(trio_context->mmio_base_mac +
819 reg_offset, class_code_revision);
820
821 #ifdef USE_SHARED_PCIE_CONFIG_REGION
822
823 /* Map in the MMIO space for the PIO region. */
824 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) |
825 (((unsigned long long)mac) <<
826 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
827
828 #else
829
830 /* Alloc a PIO region for PCI config access per MAC. */
831 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
832 if (ret < 0) {
833 pr_err("PCI: PCI CFG PIO alloc failure for mac %d "
834 "on TRIO %d, give up\n", mac, trio_index);
835
836 continue;
837 }
838
839 trio_context->pio_cfg_index[mac] = ret;
840
841 /* For PIO CFG, the bus_address_hi parameter is 0. */
842 ret = gxio_trio_init_pio_region_aux(trio_context,
843 trio_context->pio_cfg_index[mac],
844 mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
845 if (ret < 0) {
846 pr_err("PCI: PCI CFG PIO init failure for mac %d "
847 "on TRIO %d, give up\n", mac, trio_index);
848
849 continue;
850 }
851
852 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) |
853 (((unsigned long long)mac) <<
854 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
855
856 #endif
857
858 /*
859 * To save VMALLOC space, we take advantage of the fact that
860 * bit 29 in the PIO CFG address format is reserved 0. With
861 * TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT being 30,
862 * this cuts VMALLOC space usage from 1GB to 512MB per mac.
863 */
864 trio_context->mmio_base_pio_cfg[mac] =
865 iorpc_ioremap(trio_context->fd, offset, (1UL <<
866 (TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT - 1)));
867 if (trio_context->mmio_base_pio_cfg[mac] == NULL) {
868 pr_err("PCI: PIO map failure for mac %d on TRIO %d\n",
869 mac, trio_index);
870
871 continue;
872 }
873
874 /* Initialize the PCIe interrupts. */
875 if (tile_init_irqs(controller)) {
876 pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n",
877 mac, trio_index);
878
879 continue;
880 }
881
882 /*
883 * The PCI memory resource is located above the PA space.
884 * The memory range for the PCI root bus should not overlap
885 * with the physical RAM.
886 */
887 pci_add_resource_offset(&resources, &controller->mem_space,
888 controller->mem_offset);
889 pci_add_resource(&resources, &controller->io_space);
890 controller->first_busno = next_busno;
891 bus = pci_scan_root_bus(NULL, next_busno, controller->ops,
892 controller, &resources);
893 controller->root_bus = bus;
894 next_busno = bus->busn_res.end + 1;
895 }
896
897 /* Do machine dependent PCI interrupt routing */
898 pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
899
900 /*
901 * This comes from the generic Linux PCI driver.
902 *
903 * It allocates all of the resources (I/O memory, etc)
904 * associated with the devices read in above.
905 */
906 pci_assign_unassigned_resources();
907
908 /* Record the I/O resources in the PCI controller structure. */
909 for (i = 0; i < num_rc_controllers; i++) {
910 struct pci_controller *controller = &pci_controllers[i];
911 gxio_trio_context_t *trio_context = controller->trio;
912 struct pci_bus *root_bus = pci_controllers[i].root_bus;
913 int ret;
914 int j;
915
916 /*
917 * Skip controllers that are not properly initialized or
918 * have down links.
919 */
920 if (root_bus == NULL)
921 continue;
922
923 /* Configure the max_payload_size values for this domain. */
924 fixup_read_and_payload_sizes(controller);
925
926 /* Alloc a PIO region for PCI memory access for each RC port. */
927 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
928 if (ret < 0) {
929 pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, "
930 "give up\n", controller->trio_index,
931 controller->mac);
932
933 continue;
934 }
935
936 controller->pio_mem_index = ret;
937
938 /*
939 * For PIO MEM, the bus_address_hi parameter is hard-coded 0
940 * because we always assign 32-bit PCI bus BAR ranges.
941 */
942 ret = gxio_trio_init_pio_region_aux(trio_context,
943 controller->pio_mem_index,
944 controller->mac,
945 0,
946 0);
947 if (ret < 0) {
948 pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, "
949 "give up\n", controller->trio_index,
950 controller->mac);
951
952 continue;
953 }
954
955 #ifdef CONFIG_TILE_PCI_IO
956 /*
957 * Alloc a PIO region for PCI I/O space access for each RC port.
958 */
959 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
960 if (ret < 0) {
961 pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, "
962 "give up\n", controller->trio_index,
963 controller->mac);
964
965 continue;
966 }
967
968 controller->pio_io_index = ret;
969
970 /*
971 * For PIO IO, the bus_address_hi parameter is hard-coded 0
972 * because PCI I/O address space is 32-bit.
973 */
974 ret = gxio_trio_init_pio_region_aux(trio_context,
975 controller->pio_io_index,
976 controller->mac,
977 0,
978 HV_TRIO_PIO_FLAG_IO_SPACE);
979 if (ret < 0) {
980 pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, "
981 "give up\n", controller->trio_index,
982 controller->mac);
983
984 continue;
985 }
986 #endif
987
988 /*
989 * Configure a Mem-Map region for each memory controller so
990 * that Linux can map all of its PA space to the PCI bus.
991 * Use the IOMMU to handle hash-for-home memory.
992 */
993 for_each_online_node(j) {
994 unsigned long start_pfn = node_start_pfn[j];
995 unsigned long end_pfn = node_end_pfn[j];
996 unsigned long nr_pages = end_pfn - start_pfn;
997
998 ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0,
999 0);
1000 if (ret < 0) {
1001 pr_err("PCI: Mem-Map alloc failure on TRIO %d "
1002 "mac %d for MC %d, give up\n",
1003 controller->trio_index,
1004 controller->mac, j);
1005
1006 goto alloc_mem_map_failed;
1007 }
1008
1009 controller->mem_maps[j] = ret;
1010
1011 /*
1012 * Initialize the Mem-Map and the I/O MMU so that all
1013 * the physical memory can be accessed by the endpoint
1014 * devices. The base bus address is set to the base CPA
1015 * of this memory controller plus an offset (see pci.h).
1016 * The region's base VA is set to the base CPA. The
1017 * I/O MMU table essentially translates the CPA to
1018 * the real PA. Implicitly, for node 0, we create
1019 * a separate Mem-Map region that serves as the inbound
1020 * window for legacy 32-bit devices. This is a direct
1021 * map of the low 4GB CPA space.
1022 */
1023 ret = gxio_trio_init_memory_map_mmu_aux(trio_context,
1024 controller->mem_maps[j],
1025 start_pfn << PAGE_SHIFT,
1026 nr_pages << PAGE_SHIFT,
1027 trio_context->asid,
1028 controller->mac,
1029 (start_pfn << PAGE_SHIFT) +
1030 TILE_PCI_MEM_MAP_BASE_OFFSET,
1031 j,
1032 GXIO_TRIO_ORDER_MODE_UNORDERED);
1033 if (ret < 0) {
1034 pr_err("PCI: Mem-Map init failure on TRIO %d "
1035 "mac %d for MC %d, give up\n",
1036 controller->trio_index,
1037 controller->mac, j);
1038
1039 goto alloc_mem_map_failed;
1040 }
1041 continue;
1042
1043 alloc_mem_map_failed:
1044 break;
1045 }
1046 }
1047
1048 return 0;
1049 }
1050 subsys_initcall(pcibios_init);
1051
1052 /* No bus fixups needed. */
1053 void pcibios_fixup_bus(struct pci_bus *bus)
1054 {
1055 }
1056
1057 /* Process any "pci=" kernel boot arguments. */
1058 char *__init pcibios_setup(char *str)
1059 {
1060 if (!strcmp(str, "off")) {
1061 pci_probe = 0;
1062 return NULL;
1063 }
1064 return str;
1065 }
1066
1067 /*
1068 * Enable memory address decoding, as appropriate, for the
1069 * device described by the 'dev' struct.
1070 *
1071 * This is called from the generic PCI layer, and can be called
1072 * for bridges or endpoints.
1073 */
1074 int pcibios_enable_device(struct pci_dev *dev, int mask)
1075 {
1076 return pci_enable_resources(dev, mask);
1077 }
1078
1079 /*
1080 * Called for each device after PCI setup is done.
1081 * We initialize the PCI device capabilities conservatively, assuming that
1082 * all devices can only address the 32-bit DMA space. The exception here is
1083 * that the device dma_offset is set to the value that matches the 64-bit
1084 * capable devices. This is OK because dma_offset is not used by legacy
1085 * dma_ops, nor by the hybrid dma_ops's streaming DMAs, which are 64-bit ops.
1086 * This implementation matches the kernel design of setting PCI devices'
1087 * coherent_dma_mask to 0xffffffffull by default, allowing the device drivers
1088 * to skip calling pci_set_consistent_dma_mask(DMA_BIT_MASK(32)).
1089 */
1090 static void pcibios_fixup_final(struct pci_dev *pdev)
1091 {
1092 set_dma_ops(&pdev->dev, gx_legacy_pci_dma_map_ops);
1093 set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET);
1094 pdev->dev.archdata.max_direct_dma_addr =
1095 TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
1096 pdev->dev.coherent_dma_mask = TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
1097 }
1098 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
1099
1100 /* Map a PCI MMIO bus address into VA space. */
1101 void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
1102 {
1103 struct pci_controller *controller = NULL;
1104 resource_size_t bar_start;
1105 resource_size_t bar_end;
1106 resource_size_t offset;
1107 resource_size_t start;
1108 resource_size_t end;
1109 int trio_fd;
1110 int i;
1111
1112 start = phys_addr;
1113 end = phys_addr + size - 1;
1114
1115 /*
1116 * By searching phys_addr in each controller's mem_space, we can
1117 * determine the controller that should accept the PCI memory access.
1118 */
1119 for (i = 0; i < num_rc_controllers; i++) {
1120 /*
1121 * Skip controllers that are not properly initialized or
1122 * have down links.
1123 */
1124 if (pci_controllers[i].root_bus == NULL)
1125 continue;
1126
1127 bar_start = pci_controllers[i].mem_space.start;
1128 bar_end = pci_controllers[i].mem_space.end;
1129
1130 if ((start >= bar_start) && (end <= bar_end)) {
1131 controller = &pci_controllers[i];
1132 break;
1133 }
1134 }
1135
1136 if (controller == NULL)
1137 return NULL;
1138
1139 trio_fd = controller->trio->fd;
1140
1141 /* Convert the resource start to the bus address offset. */
1142 start = phys_addr - controller->mem_offset;
1143
1144 offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
1145
1146 /* We need to keep the PCI bus address's in-page offset in the VA. */
1147 return iorpc_ioremap(trio_fd, offset, size) +
1148 (start & (PAGE_SIZE - 1));
1149 }
1150 EXPORT_SYMBOL(ioremap);
1151
1152 #ifdef CONFIG_TILE_PCI_IO
1153 /* Map a PCI I/O address into VA space. */
1154 void __iomem *ioport_map(unsigned long port, unsigned int size)
1155 {
1156 struct pci_controller *controller = NULL;
1157 resource_size_t bar_start;
1158 resource_size_t bar_end;
1159 resource_size_t offset;
1160 resource_size_t start;
1161 resource_size_t end;
1162 int trio_fd;
1163 int i;
1164
1165 start = port;
1166 end = port + size - 1;
1167
1168 /*
1169 * By searching the port in each controller's io_space, we can
1170 * determine the controller that should accept the PCI I/O access.
1171 */
1172 for (i = 0; i < num_rc_controllers; i++) {
1173 /*
1174 * Skip controllers that are not properly initialized or
1175 * have down links.
1176 */
1177 if (pci_controllers[i].root_bus == NULL)
1178 continue;
1179
1180 bar_start = pci_controllers[i].io_space.start;
1181 bar_end = pci_controllers[i].io_space.end;
1182
1183 if ((start >= bar_start) && (end <= bar_end)) {
1184 controller = &pci_controllers[i];
1185 break;
1186 }
1187 }
1188
1189 if (controller == NULL)
1190 return NULL;
1191
1192 trio_fd = controller->trio->fd;
1193
1194 /* Convert the resource start to the bus address offset. */
1195 port -= controller->io_space.start;
1196
1197 offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port;
1198
1199 /* We need to keep the PCI bus address's in-page offset in the VA. */
1200 return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1));
1201 }
1202 EXPORT_SYMBOL(ioport_map);
1203
1204 void ioport_unmap(void __iomem *addr)
1205 {
1206 iounmap(addr);
1207 }
1208 EXPORT_SYMBOL(ioport_unmap);
1209 #endif
1210
1211 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1212 {
1213 iounmap(addr);
1214 }
1215 EXPORT_SYMBOL(pci_iounmap);
1216
1217 /****************************************************************
1218 *
1219 * Tile PCI config space read/write routines
1220 *
1221 ****************************************************************/
1222
1223 /*
1224 * These are the normal read and write ops
1225 * These are expanded with macros from pci_bus_read_config_byte() etc.
1226 *
1227 * devfn is the combined PCI device & function.
1228 *
1229 * offset is in bytes, from the start of config space for the
1230 * specified bus & device.
1231 */
1232 static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
1233 int size, u32 *val)
1234 {
1235 struct pci_controller *controller = bus->sysdata;
1236 gxio_trio_context_t *trio_context = controller->trio;
1237 int busnum = bus->number & 0xff;
1238 int device = PCI_SLOT(devfn);
1239 int function = PCI_FUNC(devfn);
1240 int config_type = 1;
1241 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1242 void *mmio_addr;
1243
1244 /*
1245 * Map all accesses to the local device on root bus into the
1246 * MMIO space of the MAC. Accesses to the downstream devices
1247 * go to the PIO space.
1248 */
1249 if (pci_is_root_bus(bus)) {
1250 if (device == 0) {
1251 /*
1252 * This is the internal downstream P2P bridge,
1253 * access directly.
1254 */
1255 unsigned int reg_offset;
1256
1257 reg_offset = ((offset & 0xFFF) <<
1258 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1259 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1260 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1261 (controller->mac <<
1262 TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1263
1264 mmio_addr = trio_context->mmio_base_mac + reg_offset;
1265
1266 goto valid_device;
1267
1268 } else {
1269 /*
1270 * We fake an empty device for (device > 0),
1271 * since there is only one device on bus 0.
1272 */
1273 goto invalid_device;
1274 }
1275 }
1276
1277 /*
1278 * Accesses to the directly attached device have to be
1279 * sent as type-0 configs.
1280 */
1281 if (busnum == (controller->first_busno + 1)) {
1282 /*
1283 * There is only one device off of our built-in P2P bridge.
1284 */
1285 if (device != 0)
1286 goto invalid_device;
1287
1288 config_type = 0;
1289 }
1290
1291 cfg_addr.word = 0;
1292 cfg_addr.reg_addr = (offset & 0xFFF);
1293 cfg_addr.fn = function;
1294 cfg_addr.dev = device;
1295 cfg_addr.bus = busnum;
1296 cfg_addr.type = config_type;
1297
1298 /*
1299 * Note that we don't set the mac field in cfg_addr because the
1300 * mapping is per port.
1301 */
1302 mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1303 cfg_addr.word;
1304
1305 valid_device:
1306
1307 switch (size) {
1308 case 4:
1309 *val = __gxio_mmio_read32(mmio_addr);
1310 break;
1311
1312 case 2:
1313 *val = __gxio_mmio_read16(mmio_addr);
1314 break;
1315
1316 case 1:
1317 *val = __gxio_mmio_read8(mmio_addr);
1318 break;
1319
1320 default:
1321 return PCIBIOS_FUNC_NOT_SUPPORTED;
1322 }
1323
1324 TRACE_CFG_RD(size, *val, busnum, device, function, offset);
1325
1326 return 0;
1327
1328 invalid_device:
1329
1330 switch (size) {
1331 case 4:
1332 *val = 0xFFFFFFFF;
1333 break;
1334
1335 case 2:
1336 *val = 0xFFFF;
1337 break;
1338
1339 case 1:
1340 *val = 0xFF;
1341 break;
1342
1343 default:
1344 return PCIBIOS_FUNC_NOT_SUPPORTED;
1345 }
1346
1347 return 0;
1348 }
1349
1350
1351 /*
1352 * See tile_cfg_read() for relevent comments.
1353 * Note that "val" is the value to write, not a pointer to that value.
1354 */
1355 static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
1356 int size, u32 val)
1357 {
1358 struct pci_controller *controller = bus->sysdata;
1359 gxio_trio_context_t *trio_context = controller->trio;
1360 int busnum = bus->number & 0xff;
1361 int device = PCI_SLOT(devfn);
1362 int function = PCI_FUNC(devfn);
1363 int config_type = 1;
1364 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1365 void *mmio_addr;
1366 u32 val_32 = (u32)val;
1367 u16 val_16 = (u16)val;
1368 u8 val_8 = (u8)val;
1369
1370 /*
1371 * Map all accesses to the local device on root bus into the
1372 * MMIO space of the MAC. Accesses to the downstream devices
1373 * go to the PIO space.
1374 */
1375 if (pci_is_root_bus(bus)) {
1376 if (device == 0) {
1377 /*
1378 * This is the internal downstream P2P bridge,
1379 * access directly.
1380 */
1381 unsigned int reg_offset;
1382
1383 reg_offset = ((offset & 0xFFF) <<
1384 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1385 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1386 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1387 (controller->mac <<
1388 TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1389
1390 mmio_addr = trio_context->mmio_base_mac + reg_offset;
1391
1392 goto valid_device;
1393
1394 } else {
1395 /*
1396 * We fake an empty device for (device > 0),
1397 * since there is only one device on bus 0.
1398 */
1399 goto invalid_device;
1400 }
1401 }
1402
1403 /*
1404 * Accesses to the directly attached device have to be
1405 * sent as type-0 configs.
1406 */
1407 if (busnum == (controller->first_busno + 1)) {
1408 /*
1409 * There is only one device off of our built-in P2P bridge.
1410 */
1411 if (device != 0)
1412 goto invalid_device;
1413
1414 config_type = 0;
1415 }
1416
1417 cfg_addr.word = 0;
1418 cfg_addr.reg_addr = (offset & 0xFFF);
1419 cfg_addr.fn = function;
1420 cfg_addr.dev = device;
1421 cfg_addr.bus = busnum;
1422 cfg_addr.type = config_type;
1423
1424 /*
1425 * Note that we don't set the mac field in cfg_addr because the
1426 * mapping is per port.
1427 */
1428 mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1429 cfg_addr.word;
1430
1431 valid_device:
1432
1433 switch (size) {
1434 case 4:
1435 __gxio_mmio_write32(mmio_addr, val_32);
1436 TRACE_CFG_WR(size, val_32, busnum, device, function, offset);
1437 break;
1438
1439 case 2:
1440 __gxio_mmio_write16(mmio_addr, val_16);
1441 TRACE_CFG_WR(size, val_16, busnum, device, function, offset);
1442 break;
1443
1444 case 1:
1445 __gxio_mmio_write8(mmio_addr, val_8);
1446 TRACE_CFG_WR(size, val_8, busnum, device, function, offset);
1447 break;
1448
1449 default:
1450 return PCIBIOS_FUNC_NOT_SUPPORTED;
1451 }
1452
1453 invalid_device:
1454
1455 return 0;
1456 }
1457
1458
1459 static struct pci_ops tile_cfg_ops = {
1460 .read = tile_cfg_read,
1461 .write = tile_cfg_write,
1462 };
1463
1464
1465 /* MSI support starts here. */
1466 static unsigned int tilegx_msi_startup(struct irq_data *d)
1467 {
1468 if (d->msi_desc)
1469 unmask_msi_irq(d);
1470
1471 return 0;
1472 }
1473
1474 static void tilegx_msi_ack(struct irq_data *d)
1475 {
1476 __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
1477 }
1478
1479 static void tilegx_msi_mask(struct irq_data *d)
1480 {
1481 mask_msi_irq(d);
1482 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
1483 }
1484
1485 static void tilegx_msi_unmask(struct irq_data *d)
1486 {
1487 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
1488 unmask_msi_irq(d);
1489 }
1490
1491 static struct irq_chip tilegx_msi_chip = {
1492 .name = "tilegx_msi",
1493 .irq_startup = tilegx_msi_startup,
1494 .irq_ack = tilegx_msi_ack,
1495 .irq_mask = tilegx_msi_mask,
1496 .irq_unmask = tilegx_msi_unmask,
1497
1498 /* TBD: support set_affinity. */
1499 };
1500
1501 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1502 {
1503 struct pci_controller *controller;
1504 gxio_trio_context_t *trio_context;
1505 struct msi_msg msg;
1506 int default_irq;
1507 uint64_t mem_map_base;
1508 uint64_t mem_map_limit;
1509 u64 msi_addr;
1510 int mem_map;
1511 int cpu;
1512 int irq;
1513 int ret;
1514
1515 irq = create_irq();
1516 if (irq < 0)
1517 return irq;
1518
1519 /*
1520 * Since we use a 64-bit Mem-Map to accept the MSI write, we fail
1521 * devices that are not capable of generating a 64-bit message address.
1522 * These devices will fall back to using the legacy interrupts.
1523 * Most PCIe endpoint devices do support 64-bit message addressing.
1524 */
1525 if (desc->msi_attrib.is_64 == 0) {
1526 dev_printk(KERN_INFO, &pdev->dev,
1527 "64-bit MSI message address not supported, "
1528 "falling back to legacy interrupts.\n");
1529
1530 ret = -ENOMEM;
1531 goto is_64_failure;
1532 }
1533
1534 default_irq = desc->msi_attrib.default_irq;
1535 controller = irq_get_handler_data(default_irq);
1536
1537 BUG_ON(!controller);
1538
1539 trio_context = controller->trio;
1540
1541 /*
1542 * Allocate a scatter-queue that will accept the MSI write and
1543 * trigger the TILE-side interrupts. We use the scatter-queue regions
1544 * before the mem map regions, because the latter are needed by more
1545 * applications.
1546 */
1547 mem_map = gxio_trio_alloc_scatter_queues(trio_context, 1, 0, 0);
1548 if (mem_map >= 0) {
1549 TRIO_MAP_SQ_DOORBELL_FMT_t doorbell_template = {{
1550 .pop = 0,
1551 .doorbell = 1,
1552 }};
1553
1554 mem_map += TRIO_NUM_MAP_MEM_REGIONS;
1555 mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
1556 mem_map * MEM_MAP_INTR_REGION_SIZE;
1557 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
1558
1559 msi_addr = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 8;
1560 msg.data = (unsigned int)doorbell_template.word;
1561 } else {
1562 /* SQ regions are out, allocate from map mem regions. */
1563 mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
1564 if (mem_map < 0) {
1565 dev_printk(KERN_INFO, &pdev->dev,
1566 "%s Mem-Map alloc failure. "
1567 "Failed to initialize MSI interrupts. "
1568 "Falling back to legacy interrupts.\n",
1569 desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
1570 ret = -ENOMEM;
1571 goto msi_mem_map_alloc_failure;
1572 }
1573
1574 mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
1575 mem_map * MEM_MAP_INTR_REGION_SIZE;
1576 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
1577
1578 msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 -
1579 TRIO_MAP_MEM_REG_INT0;
1580
1581 msg.data = mem_map;
1582 }
1583
1584 /* We try to distribute different IRQs to different tiles. */
1585 cpu = tile_irq_cpu(irq);
1586
1587 /*
1588 * Now call up to the HV to configure the MSI interrupt and
1589 * set up the IPI binding.
1590 */
1591 ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu),
1592 KERNEL_PL, irq, controller->mac,
1593 mem_map, mem_map_base, mem_map_limit,
1594 trio_context->asid);
1595 if (ret < 0) {
1596 dev_printk(KERN_INFO, &pdev->dev, "HV MSI config failed.\n");
1597
1598 goto hv_msi_config_failure;
1599 }
1600
1601 irq_set_msi_desc(irq, desc);
1602
1603 msg.address_hi = msi_addr >> 32;
1604 msg.address_lo = msi_addr & 0xffffffff;
1605
1606 write_msi_msg(irq, &msg);
1607 irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
1608 irq_set_handler_data(irq, controller);
1609
1610 return 0;
1611
1612 hv_msi_config_failure:
1613 /* Free mem-map */
1614 msi_mem_map_alloc_failure:
1615 is_64_failure:
1616 destroy_irq(irq);
1617 return ret;
1618 }
1619
1620 void arch_teardown_msi_irq(unsigned int irq)
1621 {
1622 destroy_irq(irq);
1623 }
Linux with added FPC-III support