drivers/iio/adc/at91-sama5d2_adc.c

   1 /*
   2  * Atmel ADC driver for SAMA5D2 devices and compatible.
   3  *
   4  * Copyright (C) 2015 Atmel,
   5  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/bitops.h>
  18 #include <linux/clk.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/module.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sched.h>
  25 #include <linux/wait.h>
  26 #include <linux/iio/iio.h>
  27 #include <linux/iio/sysfs.h>
  28 #include <linux/regulator/consumer.h>
  29
  30 /* Control Register */
  31 #define AT91_SAMA5D2_CR         0x00
  32 /* Software Reset */
  33 #define AT91_SAMA5D2_CR_SWRST           BIT(0)
  34 /* Start Conversion */
  35 #define AT91_SAMA5D2_CR_START           BIT(1)
  36 /* Touchscreen Calibration */
  37 #define AT91_SAMA5D2_CR_TSCALIB         BIT(2)
  38 /* Comparison Restart */
  39 #define AT91_SAMA5D2_CR_CMPRST          BIT(4)
  40
  41 /* Mode Register */
  42 #define AT91_SAMA5D2_MR         0x04
  43 /* Trigger Selection */
  44 #define AT91_SAMA5D2_MR_TRGSEL(v)       ((v) << 1)
  45 /* ADTRG */
  46 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0    0
  47 /* TIOA0 */
  48 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1    1
  49 /* TIOA1 */
  50 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2    2
  51 /* TIOA2 */
  52 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3    3
  53 /* PWM event line 0 */
  54 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4    4
  55 /* PWM event line 1 */
  56 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5    5
  57 /* TIOA3 */
  58 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6    6
  59 /* RTCOUT0 */
  60 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7    7
  61 /* Sleep Mode */
  62 #define AT91_SAMA5D2_MR_SLEEP           BIT(5)
  63 /* Fast Wake Up */
  64 #define AT91_SAMA5D2_MR_FWUP            BIT(6)
  65 /* Prescaler Rate Selection */
  66 #define AT91_SAMA5D2_MR_PRESCAL(v)      ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
  67 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET  8
  68 #define AT91_SAMA5D2_MR_PRESCAL_MAX     0xff
  69 #define AT91_SAMA5D2_MR_PRESCAL_MASK    GENMASK(15, 8)
  70 /* Startup Time */
  71 #define AT91_SAMA5D2_MR_STARTUP(v)      ((v) << 16)
  72 #define AT91_SAMA5D2_MR_STARTUP_MASK    GENMASK(19, 16)
  73 /* Analog Change */
  74 #define AT91_SAMA5D2_MR_ANACH           BIT(23)
  75 /* Tracking Time */
  76 #define AT91_SAMA5D2_MR_TRACKTIM(v)     ((v) << 24)
  77 #define AT91_SAMA5D2_MR_TRACKTIM_MAX    0xff
  78 /* Transfer Time */
  79 #define AT91_SAMA5D2_MR_TRANSFER(v)     ((v) << 28)
  80 #define AT91_SAMA5D2_MR_TRANSFER_MAX    0x3
  81 /* Use Sequence Enable */
  82 #define AT91_SAMA5D2_MR_USEQ            BIT(31)
  83
  84 /* Channel Sequence Register 1 */
  85 #define AT91_SAMA5D2_SEQR1      0x08
  86 /* Channel Sequence Register 2 */
  87 #define AT91_SAMA5D2_SEQR2      0x0c
  88 /* Channel Enable Register */
  89 #define AT91_SAMA5D2_CHER       0x10
  90 /* Channel Disable Register */
  91 #define AT91_SAMA5D2_CHDR       0x14
  92 /* Channel Status Register */
  93 #define AT91_SAMA5D2_CHSR       0x18
  94 /* Last Converted Data Register */
  95 #define AT91_SAMA5D2_LCDR       0x20
  96 /* Interrupt Enable Register */
  97 #define AT91_SAMA5D2_IER        0x24
  98 /* Interrupt Disable Register */
  99 #define AT91_SAMA5D2_IDR        0x28
 100 /* Interrupt Mask Register */
 101 #define AT91_SAMA5D2_IMR        0x2c
 102 /* Interrupt Status Register */
 103 #define AT91_SAMA5D2_ISR        0x30
 104 /* Last Channel Trigger Mode Register */
 105 #define AT91_SAMA5D2_LCTMR      0x34
 106 /* Last Channel Compare Window Register */
 107 #define AT91_SAMA5D2_LCCWR      0x38
 108 /* Overrun Status Register */
 109 #define AT91_SAMA5D2_OVER       0x3c
 110 /* Extended Mode Register */
 111 #define AT91_SAMA5D2_EMR        0x40
 112 /* Compare Window Register */
 113 #define AT91_SAMA5D2_CWR        0x44
 114 /* Channel Gain Register */
 115 #define AT91_SAMA5D2_CGR        0x48
 116
 117 /* Channel Offset Register */
 118 #define AT91_SAMA5D2_COR        0x4c
 119 #define AT91_SAMA5D2_COR_DIFF_OFFSET    16
 120
 121 /* Channel Data Register 0 */
 122 #define AT91_SAMA5D2_CDR0       0x50
 123 /* Analog Control Register */
 124 #define AT91_SAMA5D2_ACR        0x94
 125 /* Touchscreen Mode Register */
 126 #define AT91_SAMA5D2_TSMR       0xb0
 127 /* Touchscreen X Position Register */
 128 #define AT91_SAMA5D2_XPOSR      0xb4
 129 /* Touchscreen Y Position Register */
 130 #define AT91_SAMA5D2_YPOSR      0xb8
 131 /* Touchscreen Pressure Register */
 132 #define AT91_SAMA5D2_PRESSR     0xbc
 133 /* Trigger Register */
 134 #define AT91_SAMA5D2_TRGR       0xc0
 135 /* Correction Select Register */
 136 #define AT91_SAMA5D2_COSR       0xd0
 137 /* Correction Value Register */
 138 #define AT91_SAMA5D2_CVR        0xd4
 139 /* Channel Error Correction Register */
 140 #define AT91_SAMA5D2_CECR       0xd8
 141 /* Write Protection Mode Register */
 142 #define AT91_SAMA5D2_WPMR       0xe4
 143 /* Write Protection Status Register */
 144 #define AT91_SAMA5D2_WPSR       0xe8
 145 /* Version Register */
 146 #define AT91_SAMA5D2_VERSION    0xfc
 147
 148 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr)                             \
 149         {                                                               \
 150                 .type = IIO_VOLTAGE,                                    \
 151                 .channel = num,                                         \
 152                 .address = addr,                                        \
 153                 .scan_type = {                                          \
 154                         .sign = 'u',                                    \
 155                         .realbits = 12,                                 \
 156                 },                                                      \
 157                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 158                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 159                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
 160                 .datasheet_name = "CH"#num,                             \
 161                 .indexed = 1,                                           \
 162         }
 163
 164 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr)                         \
 165         {                                                               \
 166                 .type = IIO_VOLTAGE,                                    \
 167                 .differential = 1,                                      \
 168                 .channel = num,                                         \
 169                 .channel2 = num2,                                       \
 170                 .address = addr,                                        \
 171                 .scan_type = {                                          \
 172                         .sign = 's',                                    \
 173                         .realbits = 12,                                 \
 174                 },                                                      \
 175                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 176                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 177                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
 178                 .datasheet_name = "CH"#num"-CH"#num2,                   \
 179                 .indexed = 1,                                           \
 180         }
 181
 182 #define at91_adc_readl(st, reg)         readl_relaxed(st->base + reg)
 183 #define at91_adc_writel(st, reg, val)   writel_relaxed(val, st->base + reg)
 184
 185 struct at91_adc_soc_info {
 186         unsigned                        startup_time;
 187         unsigned                        min_sample_rate;
 188         unsigned                        max_sample_rate;
 189 };
 190
 191 struct at91_adc_state {
 192         void __iomem                    *base;
 193         int                             irq;
 194         struct clk                      *per_clk;
 195         struct regulator                *reg;
 196         struct regulator                *vref;
 197         int                             vref_uv;
 198         const struct iio_chan_spec      *chan;
 199         bool                            conversion_done;
 200         u32                             conversion_value;
 201         struct at91_adc_soc_info        soc_info;
 202         wait_queue_head_t               wq_data_available;
 203         /*
 204          * lock to prevent concurrent 'single conversion' requests through
 205          * sysfs.
 206          */
 207         struct mutex                    lock;
 208 };
 209
 210 static const struct iio_chan_spec at91_adc_channels[] = {
 211         AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
 212         AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
 213         AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
 214         AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
 215         AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
 216         AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
 217         AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
 218         AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
 219         AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
 220         AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
 221         AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
 222         AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
 223         AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
 224         AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
 225         AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
 226         AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
 227         AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
 228         AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
 229 };
 230
 231 static unsigned at91_adc_startup_time(unsigned startup_time_min,
 232                                       unsigned adc_clk_khz)
 233 {
 234         const unsigned startup_lookup[] = {
 235                   0,   8,  16,  24,
 236                  64,  80,  96, 112,
 237                 512, 576, 640, 704,
 238                 768, 832, 896, 960
 239                 };
 240         unsigned ticks_min, i;
 241
 242         /*
 243          * Since the adc frequency is checked before, there is no reason
 244          * to not meet the startup time constraint.
 245          */
 246
 247         ticks_min = startup_time_min * adc_clk_khz / 1000;
 248         for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
 249                 if (startup_lookup[i] > ticks_min)
 250                         break;
 251
 252         return i;
 253 }
 254
 255 static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq)
 256 {
 257         struct iio_dev *indio_dev = iio_priv_to_dev(st);
 258         unsigned f_per, prescal, startup, mr;
 259
 260         f_per = clk_get_rate(st->per_clk);
 261         prescal = (f_per / (2 * freq)) - 1;
 262
 263         startup = at91_adc_startup_time(st->soc_info.startup_time,
 264                                         freq / 1000);
 265
 266         mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
 267         mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
 268         mr |= AT91_SAMA5D2_MR_STARTUP(startup);
 269         mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
 270         at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
 271
 272         dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
 273                 freq, startup, prescal);
 274 }
 275
 276 static unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
 277 {
 278         unsigned f_adc, f_per = clk_get_rate(st->per_clk);
 279         unsigned mr, prescal;
 280
 281         mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
 282         prescal = (mr >> AT91_SAMA5D2_MR_PRESCAL_OFFSET)
 283                   & AT91_SAMA5D2_MR_PRESCAL_MAX;
 284         f_adc = f_per / (2 * (prescal + 1));
 285
 286         return f_adc;
 287 }
 288
 289 static irqreturn_t at91_adc_interrupt(int irq, void *private)
 290 {
 291         struct iio_dev *indio = private;
 292         struct at91_adc_state *st = iio_priv(indio);
 293         u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
 294         u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
 295
 296         if (status & imr) {
 297                 st->conversion_value = at91_adc_readl(st, st->chan->address);
 298                 st->conversion_done = true;
 299                 wake_up_interruptible(&st->wq_data_available);
 300                 return IRQ_HANDLED;
 301         }
 302
 303         return IRQ_NONE;
 304 }
 305
 306 static int at91_adc_read_raw(struct iio_dev *indio_dev,
 307                              struct iio_chan_spec const *chan,
 308                              int *val, int *val2, long mask)
 309 {
 310         struct at91_adc_state *st = iio_priv(indio_dev);
 311         u32 cor = 0;
 312         int ret;
 313
 314         switch (mask) {
 315         case IIO_CHAN_INFO_RAW:
 316                 mutex_lock(&st->lock);
 317
 318                 st->chan = chan;
 319
 320                 if (chan->differential)
 321                         cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
 322                               AT91_SAMA5D2_COR_DIFF_OFFSET;
 323
 324                 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
 325                 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
 326                 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
 327                 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
 328
 329                 ret = wait_event_interruptible_timeout(st->wq_data_available,
 330                                                        st->conversion_done,
 331                                                        msecs_to_jiffies(1000));
 332                 if (ret == 0)
 333                         ret = -ETIMEDOUT;
 334
 335                 if (ret > 0) {
 336                         *val = st->conversion_value;
 337                         if (chan->scan_type.sign == 's')
 338                                 *val = sign_extend32(*val, 11);
 339                         ret = IIO_VAL_INT;
 340                         st->conversion_done = false;
 341                 }
 342
 343                 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
 344                 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
 345
 346                 mutex_unlock(&st->lock);
 347                 return ret;
 348
 349         case IIO_CHAN_INFO_SCALE:
 350                 *val = st->vref_uv / 1000;
 351                 if (chan->differential)
 352                         *val *= 2;
 353                 *val2 = chan->scan_type.realbits;
 354                 return IIO_VAL_FRACTIONAL_LOG2;
 355
 356         case IIO_CHAN_INFO_SAMP_FREQ:
 357                 *val = at91_adc_get_sample_freq(st);
 358                 return IIO_VAL_INT;
 359
 360         default:
 361                 return -EINVAL;
 362         }
 363 }
 364
 365 static int at91_adc_write_raw(struct iio_dev *indio_dev,
 366                               struct iio_chan_spec const *chan,
 367                               int val, int val2, long mask)
 368 {
 369         struct at91_adc_state *st = iio_priv(indio_dev);
 370
 371         if (mask != IIO_CHAN_INFO_SAMP_FREQ)
 372                 return -EINVAL;
 373
 374         if (val < st->soc_info.min_sample_rate ||
 375             val > st->soc_info.max_sample_rate)
 376                 return -EINVAL;
 377
 378         at91_adc_setup_samp_freq(st, val);
 379
 380         return 0;
 381 }
 382
 383 static const struct iio_info at91_adc_info = {
 384         .read_raw = &at91_adc_read_raw,
 385         .write_raw = &at91_adc_write_raw,
 386         .driver_module = THIS_MODULE,
 387 };
 388
 389 static int at91_adc_probe(struct platform_device *pdev)
 390 {
 391         struct iio_dev *indio_dev;
 392         struct at91_adc_state *st;
 393         struct resource *res;
 394         int ret;
 395
 396         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
 397         if (!indio_dev)
 398                 return -ENOMEM;
 399
 400         indio_dev->dev.parent = &pdev->dev;
 401         indio_dev->name = dev_name(&pdev->dev);
 402         indio_dev->modes = INDIO_DIRECT_MODE;
 403         indio_dev->info = &at91_adc_info;
 404         indio_dev->channels = at91_adc_channels;
 405         indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
 406
 407         st = iio_priv(indio_dev);
 408
 409         ret = of_property_read_u32(pdev->dev.of_node,
 410                                    "atmel,min-sample-rate-hz",
 411                                    &st->soc_info.min_sample_rate);
 412         if (ret) {
 413                 dev_err(&pdev->dev,
 414                         "invalid or missing value for atmel,min-sample-rate-hz\n");
 415                 return ret;
 416         }
 417
 418         ret = of_property_read_u32(pdev->dev.of_node,
 419                                    "atmel,max-sample-rate-hz",
 420                                    &st->soc_info.max_sample_rate);
 421         if (ret) {
 422                 dev_err(&pdev->dev,
 423                         "invalid or missing value for atmel,max-sample-rate-hz\n");
 424                 return ret;
 425         }
 426
 427         ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
 428                                    &st->soc_info.startup_time);
 429         if (ret) {
 430                 dev_err(&pdev->dev,
 431                         "invalid or missing value for atmel,startup-time-ms\n");
 432                 return ret;
 433         }
 434
 435         init_waitqueue_head(&st->wq_data_available);
 436         mutex_init(&st->lock);
 437
 438         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 439         if (!res)
 440                 return -EINVAL;
 441
 442         st->base = devm_ioremap_resource(&pdev->dev, res);
 443         if (IS_ERR(st->base))
 444                 return PTR_ERR(st->base);
 445
 446         st->irq = platform_get_irq(pdev, 0);
 447         if (st->irq <= 0) {
 448                 if (!st->irq)
 449                         st->irq = -ENXIO;
 450
 451                 return st->irq;
 452         }
 453
 454         st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
 455         if (IS_ERR(st->per_clk))
 456                 return PTR_ERR(st->per_clk);
 457
 458         st->reg = devm_regulator_get(&pdev->dev, "vddana");
 459         if (IS_ERR(st->reg))
 460                 return PTR_ERR(st->reg);
 461
 462         st->vref = devm_regulator_get(&pdev->dev, "vref");
 463         if (IS_ERR(st->vref))
 464                 return PTR_ERR(st->vref);
 465
 466         ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
 467                                pdev->dev.driver->name, indio_dev);
 468         if (ret)
 469                 return ret;
 470
 471         ret = regulator_enable(st->reg);
 472         if (ret)
 473                 return ret;
 474
 475         ret = regulator_enable(st->vref);
 476         if (ret)
 477                 goto reg_disable;
 478
 479         st->vref_uv = regulator_get_voltage(st->vref);
 480         if (st->vref_uv <= 0) {
 481                 ret = -EINVAL;
 482                 goto vref_disable;
 483         }
 484
 485         at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
 486         at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
 487         /*
 488          * Transfer field must be set to 2 according to the datasheet and
 489          * allows different analog settings for each channel.
 490          */
 491         at91_adc_writel(st, AT91_SAMA5D2_MR,
 492                         AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
 493
 494         at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate);
 495
 496         ret = clk_prepare_enable(st->per_clk);
 497         if (ret)
 498                 goto vref_disable;
 499
 500         platform_set_drvdata(pdev, indio_dev);
 501
 502         ret = iio_device_register(indio_dev);
 503         if (ret < 0)
 504                 goto per_clk_disable_unprepare;
 505
 506         dev_info(&pdev->dev, "version: %x\n",
 507                  readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
 508
 509         return 0;
 510
 511 per_clk_disable_unprepare:
 512         clk_disable_unprepare(st->per_clk);
 513 vref_disable:
 514         regulator_disable(st->vref);
 515 reg_disable:
 516         regulator_disable(st->reg);
 517         return ret;
 518 }
 519
 520 static int at91_adc_remove(struct platform_device *pdev)
 521 {
 522         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 523         struct at91_adc_state *st = iio_priv(indio_dev);
 524
 525         iio_device_unregister(indio_dev);
 526
 527         clk_disable_unprepare(st->per_clk);
 528
 529         regulator_disable(st->vref);
 530         regulator_disable(st->reg);
 531
 532         return 0;
 533 }
 534
 535 static const struct of_device_id at91_adc_dt_match[] = {
 536         {
 537                 .compatible = "atmel,sama5d2-adc",
 538         }, {
 539                 /* sentinel */
 540         }
 541 };
 542 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
 543
 544 static struct platform_driver at91_adc_driver = {
 545         .probe = at91_adc_probe,
 546         .remove = at91_adc_remove,
 547         .driver = {
 548                 .name = "at91-sama5d2_adc",
 549                 .of_match_table = at91_adc_dt_match,
 550         },
 551 };
 552 module_platform_driver(at91_adc_driver)
 553
 554 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
 555 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
 556 MODULE_LICENSE("GPL v2");