2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
40 #include "nuvoton-cir.h"
42 static void nvt_clear_cir_wake_fifo(struct nvt_dev
*nvt
);
44 static const struct nvt_chip nvt_chips
[] = {
45 { "w83667hg", NVT_W83667HG
},
46 { "NCT6775F", NVT_6775F
},
47 { "NCT6776F", NVT_6776F
},
48 { "NCT6779D", NVT_6779D
},
51 static inline bool is_w83667hg(struct nvt_dev
*nvt
)
53 return nvt
->chip_ver
== NVT_W83667HG
;
56 /* write val to config reg */
57 static inline void nvt_cr_write(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
59 outb(reg
, nvt
->cr_efir
);
60 outb(val
, nvt
->cr_efdr
);
63 /* read val from config reg */
64 static inline u8
nvt_cr_read(struct nvt_dev
*nvt
, u8 reg
)
66 outb(reg
, nvt
->cr_efir
);
67 return inb(nvt
->cr_efdr
);
70 /* update config register bit without changing other bits */
71 static inline void nvt_set_reg_bit(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
73 u8 tmp
= nvt_cr_read(nvt
, reg
) | val
;
74 nvt_cr_write(nvt
, tmp
, reg
);
77 /* clear config register bit without changing other bits */
78 static inline void nvt_clear_reg_bit(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
80 u8 tmp
= nvt_cr_read(nvt
, reg
) & ~val
;
81 nvt_cr_write(nvt
, tmp
, reg
);
84 /* enter extended function mode */
85 static inline int nvt_efm_enable(struct nvt_dev
*nvt
)
87 if (!request_muxed_region(nvt
->cr_efir
, 2, NVT_DRIVER_NAME
))
90 /* Enabling Extended Function Mode explicitly requires writing 2x */
91 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
92 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
97 /* exit extended function mode */
98 static inline void nvt_efm_disable(struct nvt_dev
*nvt
)
100 outb(EFER_EFM_DISABLE
, nvt
->cr_efir
);
102 release_region(nvt
->cr_efir
, 2);
106 * When you want to address a specific logical device, write its logical
107 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
108 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
110 static inline void nvt_select_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
112 nvt_cr_write(nvt
, ldev
, CR_LOGICAL_DEV_SEL
);
115 /* select and enable logical device with setting EFM mode*/
116 static inline void nvt_enable_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
119 nvt_select_logical_dev(nvt
, ldev
);
120 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
121 nvt_efm_disable(nvt
);
124 /* select and disable logical device with setting EFM mode*/
125 static inline void nvt_disable_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
128 nvt_select_logical_dev(nvt
, ldev
);
129 nvt_cr_write(nvt
, LOGICAL_DEV_DISABLE
, CR_LOGICAL_DEV_EN
);
130 nvt_efm_disable(nvt
);
133 /* write val to cir config register */
134 static inline void nvt_cir_reg_write(struct nvt_dev
*nvt
, u8 val
, u8 offset
)
136 outb(val
, nvt
->cir_addr
+ offset
);
139 /* read val from cir config register */
140 static u8
nvt_cir_reg_read(struct nvt_dev
*nvt
, u8 offset
)
142 return inb(nvt
->cir_addr
+ offset
);
145 /* write val to cir wake register */
146 static inline void nvt_cir_wake_reg_write(struct nvt_dev
*nvt
,
149 outb(val
, nvt
->cir_wake_addr
+ offset
);
152 /* read val from cir wake config register */
153 static u8
nvt_cir_wake_reg_read(struct nvt_dev
*nvt
, u8 offset
)
155 return inb(nvt
->cir_wake_addr
+ offset
);
158 /* don't override io address if one is set already */
159 static void nvt_set_ioaddr(struct nvt_dev
*nvt
, unsigned long *ioaddr
)
161 unsigned long old_addr
;
163 old_addr
= nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8;
164 old_addr
|= nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
);
169 nvt_cr_write(nvt
, *ioaddr
>> 8, CR_CIR_BASE_ADDR_HI
);
170 nvt_cr_write(nvt
, *ioaddr
& 0xff, CR_CIR_BASE_ADDR_LO
);
174 static ssize_t
wakeup_data_show(struct device
*dev
,
175 struct device_attribute
*attr
,
178 struct rc_dev
*rc_dev
= to_rc_dev(dev
);
179 struct nvt_dev
*nvt
= rc_dev
->priv
;
180 int fifo_len
, duration
;
185 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
187 fifo_len
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
);
188 fifo_len
= min(fifo_len
, WAKEUP_MAX_SIZE
);
190 /* go to first element to be read */
191 while (nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
))
192 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
);
194 for (i
= 0; i
< fifo_len
; i
++) {
195 duration
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
);
196 duration
= (duration
& BUF_LEN_MASK
) * SAMPLE_PERIOD
;
197 buf_len
+= snprintf(buf
+ buf_len
, PAGE_SIZE
- buf_len
,
200 buf_len
+= snprintf(buf
+ buf_len
, PAGE_SIZE
- buf_len
, "\n");
202 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
207 static ssize_t
wakeup_data_store(struct device
*dev
,
208 struct device_attribute
*attr
,
209 const char *buf
, size_t len
)
211 struct rc_dev
*rc_dev
= to_rc_dev(dev
);
212 struct nvt_dev
*nvt
= rc_dev
->priv
;
214 u8 tolerance
, config
, wake_buf
[WAKEUP_MAX_SIZE
];
220 argv
= argv_split(GFP_KERNEL
, buf
, &count
);
223 if (!count
|| count
> WAKEUP_MAX_SIZE
) {
228 for (i
= 0; i
< count
; i
++) {
229 ret
= kstrtouint(argv
[i
], 10, &val
);
232 val
= DIV_ROUND_CLOSEST(val
, SAMPLE_PERIOD
);
233 if (!val
|| val
> 0x7f) {
238 /* sequence must start with a pulse */
240 wake_buf
[i
] |= BUF_PULSE_BIT
;
243 /* hardcode the tolerance to 10% */
244 tolerance
= DIV_ROUND_UP(count
, 10);
246 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
248 nvt_clear_cir_wake_fifo(nvt
);
249 nvt_cir_wake_reg_write(nvt
, count
, CIR_WAKE_FIFO_CMP_DEEP
);
250 nvt_cir_wake_reg_write(nvt
, tolerance
, CIR_WAKE_FIFO_CMP_TOL
);
252 config
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
);
254 /* enable writes to wake fifo */
255 nvt_cir_wake_reg_write(nvt
, config
| CIR_WAKE_IRCON_MODE1
,
258 for (i
= 0; i
< count
; i
++)
259 nvt_cir_wake_reg_write(nvt
, wake_buf
[i
], CIR_WAKE_WR_FIFO_DATA
);
261 nvt_cir_wake_reg_write(nvt
, config
, CIR_WAKE_IRCON
);
263 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
270 static DEVICE_ATTR_RW(wakeup_data
);
272 /* dump current cir register contents */
273 static void cir_dump_regs(struct nvt_dev
*nvt
)
276 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
278 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME
);
279 pr_info(" * CR CIR ACTIVE : 0x%x\n",
280 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
281 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
282 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
283 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
284 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
285 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
287 nvt_efm_disable(nvt
);
289 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME
);
290 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRCON
));
291 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRSTS
));
292 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IREN
));
293 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_RXFCONT
));
294 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CP
));
295 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CC
));
296 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCH
));
297 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCL
));
298 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FIFOCON
));
299 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFIFOSTS
));
300 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SRXFIFO
));
301 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_TXFCONT
));
302 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_STXFIFO
));
303 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCH
));
304 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCL
));
305 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFSM
));
308 /* dump current cir wake register contents */
309 static void cir_wake_dump_regs(struct nvt_dev
*nvt
)
314 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
316 pr_info("%s: Dump CIR WAKE logical device registers:\n",
318 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
319 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
320 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
321 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
322 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
323 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
324 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
326 nvt_efm_disable(nvt
);
328 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME
);
329 pr_info(" * IRCON: 0x%x\n",
330 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
));
331 pr_info(" * IRSTS: 0x%x\n",
332 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRSTS
));
333 pr_info(" * IREN: 0x%x\n",
334 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IREN
));
335 pr_info(" * FIFO CMP DEEP: 0x%x\n",
336 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_DEEP
));
337 pr_info(" * FIFO CMP TOL: 0x%x\n",
338 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_TOL
));
339 pr_info(" * FIFO COUNT: 0x%x\n",
340 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
));
341 pr_info(" * SLCH: 0x%x\n",
342 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCH
));
343 pr_info(" * SLCL: 0x%x\n",
344 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCL
));
345 pr_info(" * FIFOCON: 0x%x\n",
346 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
));
347 pr_info(" * SRXFSTS: 0x%x\n",
348 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SRXFSTS
));
349 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
350 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SAMPLE_RX_FIFO
));
351 pr_info(" * WR FIFO DATA: 0x%x\n",
352 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_WR_FIFO_DATA
));
353 pr_info(" * RD FIFO ONLY: 0x%x\n",
354 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
355 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
356 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
));
357 pr_info(" * FIFO IGNORE: 0x%x\n",
358 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_IGNORE
));
359 pr_info(" * IRFSM: 0x%x\n",
360 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRFSM
));
362 fifo_len
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
);
363 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME
, fifo_len
);
364 pr_info("* Contents =");
365 for (i
= 0; i
< fifo_len
; i
++)
367 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
371 static inline const char *nvt_find_chip(struct nvt_dev
*nvt
, int id
)
375 for (i
= 0; i
< ARRAY_SIZE(nvt_chips
); i
++)
376 if ((id
& SIO_ID_MASK
) == nvt_chips
[i
].chip_ver
) {
377 nvt
->chip_ver
= nvt_chips
[i
].chip_ver
;
378 return nvt_chips
[i
].name
;
385 /* detect hardware features */
386 static int nvt_hw_detect(struct nvt_dev
*nvt
)
388 const char *chip_name
;
393 /* Check if we're wired for the alternate EFER setup */
394 nvt
->chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
395 if (nvt
->chip_major
== 0xff) {
396 nvt_efm_disable(nvt
);
397 nvt
->cr_efir
= CR_EFIR2
;
398 nvt
->cr_efdr
= CR_EFDR2
;
400 nvt
->chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
402 nvt
->chip_minor
= nvt_cr_read(nvt
, CR_CHIP_ID_LO
);
404 nvt_efm_disable(nvt
);
406 chip_id
= nvt
->chip_major
<< 8 | nvt
->chip_minor
;
407 if (chip_id
== NVT_INVALID
) {
408 dev_err(&nvt
->pdev
->dev
,
409 "No device found on either EFM port\n");
413 chip_name
= nvt_find_chip(nvt
, chip_id
);
415 /* warn, but still let the driver load, if we don't know this chip */
417 dev_warn(&nvt
->pdev
->dev
,
418 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
419 nvt
->chip_major
, nvt
->chip_minor
);
421 dev_info(&nvt
->pdev
->dev
,
422 "found %s or compatible: chip id: 0x%02x 0x%02x",
423 chip_name
, nvt
->chip_major
, nvt
->chip_minor
);
428 static void nvt_cir_ldev_init(struct nvt_dev
*nvt
)
430 u8 val
, psreg
, psmask
, psval
;
432 if (is_w83667hg(nvt
)) {
433 psreg
= CR_MULTIFUNC_PIN_SEL
;
434 psmask
= MULTIFUNC_PIN_SEL_MASK
;
435 psval
= MULTIFUNC_ENABLE_CIR
| MULTIFUNC_ENABLE_CIRWB
;
437 psreg
= CR_OUTPUT_PIN_SEL
;
438 psmask
= OUTPUT_PIN_SEL_MASK
;
439 psval
= OUTPUT_ENABLE_CIR
| OUTPUT_ENABLE_CIRWB
;
442 /* output pin selection: enable CIR, with WB sensor enabled */
443 val
= nvt_cr_read(nvt
, psreg
);
446 nvt_cr_write(nvt
, val
, psreg
);
448 /* Select CIR logical device */
449 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
451 nvt_set_ioaddr(nvt
, &nvt
->cir_addr
);
453 nvt_cr_write(nvt
, nvt
->cir_irq
, CR_CIR_IRQ_RSRC
);
455 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
456 nvt
->cir_addr
, nvt
->cir_irq
);
459 static void nvt_cir_wake_ldev_init(struct nvt_dev
*nvt
)
461 /* Select ACPI logical device and anable it */
462 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
463 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
465 /* Enable CIR Wake via PSOUT# (Pin60) */
466 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
468 /* enable pme interrupt of cir wakeup event */
469 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
471 /* Select CIR Wake logical device */
472 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
474 nvt_set_ioaddr(nvt
, &nvt
->cir_wake_addr
);
476 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx",
480 /* clear out the hardware's cir rx fifo */
481 static void nvt_clear_cir_fifo(struct nvt_dev
*nvt
)
483 u8 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
484 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_RXFIFOCLR
, CIR_FIFOCON
);
487 /* clear out the hardware's cir wake rx fifo */
488 static void nvt_clear_cir_wake_fifo(struct nvt_dev
*nvt
)
492 config
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
);
494 /* clearing wake fifo works in learning mode only */
495 nvt_cir_wake_reg_write(nvt
, config
& ~CIR_WAKE_IRCON_MODE0
,
498 val
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
);
499 nvt_cir_wake_reg_write(nvt
, val
| CIR_WAKE_FIFOCON_RXFIFOCLR
,
502 nvt_cir_wake_reg_write(nvt
, config
, CIR_WAKE_IRCON
);
505 /* clear out the hardware's cir tx fifo */
506 static void nvt_clear_tx_fifo(struct nvt_dev
*nvt
)
510 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
511 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_TXFIFOCLR
, CIR_FIFOCON
);
514 /* enable RX Trigger Level Reach and Packet End interrupts */
515 static void nvt_set_cir_iren(struct nvt_dev
*nvt
)
519 iren
= CIR_IREN_RTR
| CIR_IREN_PE
| CIR_IREN_RFO
;
520 nvt_cir_reg_write(nvt
, iren
, CIR_IREN
);
523 static void nvt_cir_regs_init(struct nvt_dev
*nvt
)
525 /* set sample limit count (PE interrupt raised when reached) */
526 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
>> 8, CIR_SLCH
);
527 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
& 0xff, CIR_SLCL
);
529 /* set fifo irq trigger levels */
530 nvt_cir_reg_write(nvt
, CIR_FIFOCON_TX_TRIGGER_LEV
|
531 CIR_FIFOCON_RX_TRIGGER_LEV
, CIR_FIFOCON
);
534 * Enable TX and RX, specify carrier on = low, off = high, and set
535 * sample period (currently 50us)
537 nvt_cir_reg_write(nvt
,
538 CIR_IRCON_TXEN
| CIR_IRCON_RXEN
|
539 CIR_IRCON_RXINV
| CIR_IRCON_SAMPLE_PERIOD_SEL
,
542 /* clear hardware rx and tx fifos */
543 nvt_clear_cir_fifo(nvt
);
544 nvt_clear_tx_fifo(nvt
);
546 /* clear any and all stray interrupts */
547 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
549 /* and finally, enable interrupts */
550 nvt_set_cir_iren(nvt
);
552 /* enable the CIR logical device */
553 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
556 static void nvt_cir_wake_regs_init(struct nvt_dev
*nvt
)
559 * Disable RX, set specific carrier on = low, off = high,
560 * and sample period (currently 50us)
562 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
|
563 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
564 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
567 /* clear any and all stray interrupts */
568 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
570 /* enable the CIR WAKE logical device */
571 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
574 static void nvt_enable_wake(struct nvt_dev
*nvt
)
580 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
581 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
582 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
584 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
585 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
587 nvt_efm_disable(nvt
);
589 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
591 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
| CIR_WAKE_IRCON_RXEN
|
592 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
593 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
595 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
596 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IREN
);
598 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
601 #if 0 /* Currently unused */
602 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
603 static u32
nvt_rx_carrier_detect(struct nvt_dev
*nvt
)
605 u32 count
, carrier
, duration
= 0;
608 count
= nvt_cir_reg_read(nvt
, CIR_FCCL
) |
609 nvt_cir_reg_read(nvt
, CIR_FCCH
) << 8;
611 for (i
= 0; i
< nvt
->pkts
; i
++) {
612 if (nvt
->buf
[i
] & BUF_PULSE_BIT
)
613 duration
+= nvt
->buf
[i
] & BUF_LEN_MASK
;
616 duration
*= SAMPLE_PERIOD
;
618 if (!count
|| !duration
) {
619 dev_notice(&nvt
->pdev
->dev
,
620 "Unable to determine carrier! (c:%u, d:%u)",
625 carrier
= MS_TO_NS(count
) / duration
;
627 if ((carrier
> MAX_CARRIER
) || (carrier
< MIN_CARRIER
))
628 nvt_dbg("WTF? Carrier frequency out of range!");
630 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
631 carrier
, count
, duration
);
637 * set carrier frequency
639 * set carrier on 2 registers: CP & CC
640 * always set CP as 0x81
641 * set CC by SPEC, CC = 3MHz/carrier - 1
643 static int nvt_set_tx_carrier(struct rc_dev
*dev
, u32 carrier
)
645 struct nvt_dev
*nvt
= dev
->priv
;
651 nvt_cir_reg_write(nvt
, 1, CIR_CP
);
652 val
= 3000000 / (carrier
) - 1;
653 nvt_cir_reg_write(nvt
, val
& 0xff, CIR_CC
);
655 nvt_dbg("cp: 0x%x cc: 0x%x\n",
656 nvt_cir_reg_read(nvt
, CIR_CP
), nvt_cir_reg_read(nvt
, CIR_CC
));
664 * 1) clean TX fifo first (handled by AP)
665 * 2) copy data from user space
666 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
667 * 4) send 9 packets to TX FIFO to open TTR
668 * in interrupt_handler:
669 * 5) send all data out
670 * go back to write():
671 * 6) disable TX interrupts, re-enable RX interupts
673 * The key problem of this function is user space data may larger than
674 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
675 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
676 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
677 * set TXFCONT as 0xff, until buf_count less than 0xff.
679 static int nvt_tx_ir(struct rc_dev
*dev
, unsigned *txbuf
, unsigned n
)
681 struct nvt_dev
*nvt
= dev
->priv
;
687 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
689 ret
= min((unsigned)(TX_BUF_LEN
/ sizeof(unsigned)), n
);
690 nvt
->tx
.buf_count
= (ret
* sizeof(unsigned));
692 memcpy(nvt
->tx
.buf
, txbuf
, nvt
->tx
.buf_count
);
694 nvt
->tx
.cur_buf_num
= 0;
696 /* save currently enabled interrupts */
697 iren
= nvt_cir_reg_read(nvt
, CIR_IREN
);
699 /* now disable all interrupts, save TFU & TTR */
700 nvt_cir_reg_write(nvt
, CIR_IREN_TFU
| CIR_IREN_TTR
, CIR_IREN
);
702 nvt
->tx
.tx_state
= ST_TX_REPLY
;
704 nvt_cir_reg_write(nvt
, CIR_FIFOCON_TX_TRIGGER_LEV_8
|
705 CIR_FIFOCON_RXFIFOCLR
, CIR_FIFOCON
);
707 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
708 for (i
= 0; i
< 9; i
++)
709 nvt_cir_reg_write(nvt
, 0x01, CIR_STXFIFO
);
711 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
713 wait_event(nvt
->tx
.queue
, nvt
->tx
.tx_state
== ST_TX_REQUEST
);
715 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
716 nvt
->tx
.tx_state
= ST_TX_NONE
;
717 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
719 /* restore enabled interrupts to prior state */
720 nvt_cir_reg_write(nvt
, iren
, CIR_IREN
);
725 /* dump contents of the last rx buffer we got from the hw rx fifo */
726 static void nvt_dump_rx_buf(struct nvt_dev
*nvt
)
730 printk(KERN_DEBUG
"%s (len %d): ", __func__
, nvt
->pkts
);
731 for (i
= 0; (i
< nvt
->pkts
) && (i
< RX_BUF_LEN
); i
++)
732 printk(KERN_CONT
"0x%02x ", nvt
->buf
[i
]);
733 printk(KERN_CONT
"\n");
737 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
738 * trigger decode when appropriate.
740 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
741 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
742 * (default 50us) intervals for that pulse/space. A discrete signal is
743 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
744 * to signal more IR coming (repeats) or end of IR, respectively. We store
745 * sample data in the raw event kfifo until we see 0x7<something> (except f)
746 * or 0x80, at which time, we trigger a decode operation.
748 static void nvt_process_rx_ir_data(struct nvt_dev
*nvt
)
750 DEFINE_IR_RAW_EVENT(rawir
);
754 nvt_dbg_verbose("%s firing", __func__
);
757 nvt_dump_rx_buf(nvt
);
759 nvt_dbg_verbose("Processing buffer of len %d", nvt
->pkts
);
761 for (i
= 0; i
< nvt
->pkts
; i
++) {
762 sample
= nvt
->buf
[i
];
764 rawir
.pulse
= ((sample
& BUF_PULSE_BIT
) != 0);
765 rawir
.duration
= US_TO_NS((sample
& BUF_LEN_MASK
)
768 nvt_dbg("Storing %s with duration %d",
769 rawir
.pulse
? "pulse" : "space", rawir
.duration
);
771 ir_raw_event_store_with_filter(nvt
->rdev
, &rawir
);
774 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
775 * indicates end of IR signal, but new data incoming. In both
776 * cases, it means we're ready to call ir_raw_event_handle
778 if ((sample
== BUF_PULSE_BIT
) && (i
+ 1 < nvt
->pkts
)) {
779 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
780 ir_raw_event_handle(nvt
->rdev
);
786 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
787 ir_raw_event_handle(nvt
->rdev
);
789 nvt_dbg_verbose("%s done", __func__
);
792 static void nvt_handle_rx_fifo_overrun(struct nvt_dev
*nvt
)
794 dev_warn(&nvt
->pdev
->dev
, "RX FIFO overrun detected, flushing data!");
797 nvt_clear_cir_fifo(nvt
);
798 ir_raw_event_reset(nvt
->rdev
);
801 /* copy data from hardware rx fifo into driver buffer */
802 static void nvt_get_rx_ir_data(struct nvt_dev
*nvt
)
808 /* Get count of how many bytes to read from RX FIFO */
809 fifocount
= nvt_cir_reg_read(nvt
, CIR_RXFCONT
);
811 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount
);
815 /* This should never happen, but lets check anyway... */
816 if (b_idx
+ fifocount
> RX_BUF_LEN
) {
817 nvt_process_rx_ir_data(nvt
);
821 /* Read fifocount bytes from CIR Sample RX FIFO register */
822 for (i
= 0; i
< fifocount
; i
++) {
823 val
= nvt_cir_reg_read(nvt
, CIR_SRXFIFO
);
824 nvt
->buf
[b_idx
+ i
] = val
;
827 nvt
->pkts
+= fifocount
;
828 nvt_dbg("%s: pkts now %d", __func__
, nvt
->pkts
);
830 nvt_process_rx_ir_data(nvt
);
833 static void nvt_cir_log_irqs(u8 status
, u8 iren
)
835 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
837 status
& CIR_IRSTS_RDR
? " RDR" : "",
838 status
& CIR_IRSTS_RTR
? " RTR" : "",
839 status
& CIR_IRSTS_PE
? " PE" : "",
840 status
& CIR_IRSTS_RFO
? " RFO" : "",
841 status
& CIR_IRSTS_TE
? " TE" : "",
842 status
& CIR_IRSTS_TTR
? " TTR" : "",
843 status
& CIR_IRSTS_TFU
? " TFU" : "",
844 status
& CIR_IRSTS_GH
? " GH" : "",
845 status
& ~(CIR_IRSTS_RDR
| CIR_IRSTS_RTR
| CIR_IRSTS_PE
|
846 CIR_IRSTS_RFO
| CIR_IRSTS_TE
| CIR_IRSTS_TTR
|
847 CIR_IRSTS_TFU
| CIR_IRSTS_GH
) ? " ?" : "");
850 static bool nvt_cir_tx_inactive(struct nvt_dev
*nvt
)
855 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
856 tx_state
= nvt
->tx
.tx_state
;
857 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
859 return tx_state
== ST_TX_NONE
;
862 /* interrupt service routine for incoming and outgoing CIR data */
863 static irqreturn_t
nvt_cir_isr(int irq
, void *data
)
865 struct nvt_dev
*nvt
= data
;
869 nvt_dbg_verbose("%s firing", __func__
);
871 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
874 * Get IR Status register contents. Write 1 to ack/clear
876 * bit: reg name - description
877 * 7: CIR_IRSTS_RDR - RX Data Ready
878 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
879 * 5: CIR_IRSTS_PE - Packet End
880 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
881 * 3: CIR_IRSTS_TE - TX FIFO Empty
882 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
883 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
884 * 0: CIR_IRSTS_GH - Min Length Detected
886 status
= nvt_cir_reg_read(nvt
, CIR_IRSTS
);
887 iren
= nvt_cir_reg_read(nvt
, CIR_IREN
);
889 /* IRQ may be shared with CIR WAKE, therefore check for each
890 * status bit whether the related interrupt source is enabled
892 if (!(status
& iren
)) {
893 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
894 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__
);
898 /* ack/clear all irq flags we've got */
899 nvt_cir_reg_write(nvt
, status
, CIR_IRSTS
);
900 nvt_cir_reg_write(nvt
, 0, CIR_IRSTS
);
902 nvt_cir_log_irqs(status
, iren
);
904 if (status
& CIR_IRSTS_RFO
)
905 nvt_handle_rx_fifo_overrun(nvt
);
907 else if (status
& (CIR_IRSTS_RTR
| CIR_IRSTS_PE
)) {
908 /* We only do rx if not tx'ing */
909 if (nvt_cir_tx_inactive(nvt
))
910 nvt_get_rx_ir_data(nvt
);
913 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
915 if (status
& CIR_IRSTS_TE
)
916 nvt_clear_tx_fifo(nvt
);
918 if (status
& CIR_IRSTS_TTR
) {
919 unsigned int pos
, count
;
922 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
924 pos
= nvt
->tx
.cur_buf_num
;
925 count
= nvt
->tx
.buf_count
;
927 /* Write data into the hardware tx fifo while pos < count */
929 nvt_cir_reg_write(nvt
, nvt
->tx
.buf
[pos
], CIR_STXFIFO
);
930 nvt
->tx
.cur_buf_num
++;
931 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
933 tmp
= nvt_cir_reg_read(nvt
, CIR_IREN
);
934 nvt_cir_reg_write(nvt
, tmp
& ~CIR_IREN_TTR
, CIR_IREN
);
937 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
941 if (status
& CIR_IRSTS_TFU
) {
942 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
943 if (nvt
->tx
.tx_state
== ST_TX_REPLY
) {
944 nvt
->tx
.tx_state
= ST_TX_REQUEST
;
945 wake_up(&nvt
->tx
.queue
);
947 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
950 nvt_dbg_verbose("%s done", __func__
);
954 static void nvt_disable_cir(struct nvt_dev
*nvt
)
958 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
960 /* disable CIR interrupts */
961 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
963 /* clear any and all pending interrupts */
964 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
966 /* clear all function enable flags */
967 nvt_cir_reg_write(nvt
, 0, CIR_IRCON
);
969 /* clear hardware rx and tx fifos */
970 nvt_clear_cir_fifo(nvt
);
971 nvt_clear_tx_fifo(nvt
);
973 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
975 /* disable the CIR logical device */
976 nvt_disable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
979 static int nvt_open(struct rc_dev
*dev
)
981 struct nvt_dev
*nvt
= dev
->priv
;
984 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
986 /* set function enable flags */
987 nvt_cir_reg_write(nvt
, CIR_IRCON_TXEN
| CIR_IRCON_RXEN
|
988 CIR_IRCON_RXINV
| CIR_IRCON_SAMPLE_PERIOD_SEL
,
991 /* clear all pending interrupts */
992 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
994 /* enable interrupts */
995 nvt_set_cir_iren(nvt
);
997 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
999 /* enable the CIR logical device */
1000 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
1005 static void nvt_close(struct rc_dev
*dev
)
1007 struct nvt_dev
*nvt
= dev
->priv
;
1009 nvt_disable_cir(nvt
);
1012 /* Allocate memory, probe hardware, and initialize everything */
1013 static int nvt_probe(struct pnp_dev
*pdev
, const struct pnp_device_id
*dev_id
)
1015 struct nvt_dev
*nvt
;
1016 struct rc_dev
*rdev
;
1019 nvt
= devm_kzalloc(&pdev
->dev
, sizeof(struct nvt_dev
), GFP_KERNEL
);
1023 /* input device for IR remote (and tx) */
1024 rdev
= rc_allocate_device();
1026 goto exit_free_dev_rdev
;
1029 /* activate pnp device */
1030 if (pnp_activate_dev(pdev
) < 0) {
1031 dev_err(&pdev
->dev
, "Could not activate PNP device!\n");
1032 goto exit_free_dev_rdev
;
1035 /* validate pnp resources */
1036 if (!pnp_port_valid(pdev
, 0) ||
1037 pnp_port_len(pdev
, 0) < CIR_IOREG_LENGTH
) {
1038 dev_err(&pdev
->dev
, "IR PNP Port not valid!\n");
1039 goto exit_free_dev_rdev
;
1042 if (!pnp_irq_valid(pdev
, 0)) {
1043 dev_err(&pdev
->dev
, "PNP IRQ not valid!\n");
1044 goto exit_free_dev_rdev
;
1047 if (!pnp_port_valid(pdev
, 1) ||
1048 pnp_port_len(pdev
, 1) < CIR_IOREG_LENGTH
) {
1049 dev_err(&pdev
->dev
, "Wake PNP Port not valid!\n");
1050 goto exit_free_dev_rdev
;
1053 nvt
->cir_addr
= pnp_port_start(pdev
, 0);
1054 nvt
->cir_irq
= pnp_irq(pdev
, 0);
1056 nvt
->cir_wake_addr
= pnp_port_start(pdev
, 1);
1058 nvt
->cr_efir
= CR_EFIR
;
1059 nvt
->cr_efdr
= CR_EFDR
;
1061 spin_lock_init(&nvt
->nvt_lock
);
1062 spin_lock_init(&nvt
->tx
.lock
);
1064 pnp_set_drvdata(pdev
, nvt
);
1067 init_waitqueue_head(&nvt
->tx
.queue
);
1069 ret
= nvt_hw_detect(nvt
);
1071 goto exit_free_dev_rdev
;
1073 /* Initialize CIR & CIR Wake Logical Devices */
1074 nvt_efm_enable(nvt
);
1075 nvt_cir_ldev_init(nvt
);
1076 nvt_cir_wake_ldev_init(nvt
);
1077 nvt_efm_disable(nvt
);
1080 * Initialize CIR & CIR Wake Config Registers
1081 * and enable logical devices
1083 nvt_cir_regs_init(nvt
);
1084 nvt_cir_wake_regs_init(nvt
);
1086 /* Set up the rc device */
1088 rdev
->driver_type
= RC_DRIVER_IR_RAW
;
1089 rdev
->allowed_protocols
= RC_BIT_ALL
;
1090 rdev
->open
= nvt_open
;
1091 rdev
->close
= nvt_close
;
1092 rdev
->tx_ir
= nvt_tx_ir
;
1093 rdev
->s_tx_carrier
= nvt_set_tx_carrier
;
1094 rdev
->input_name
= "Nuvoton w836x7hg Infrared Remote Transceiver";
1095 rdev
->input_phys
= "nuvoton/cir0";
1096 rdev
->input_id
.bustype
= BUS_HOST
;
1097 rdev
->input_id
.vendor
= PCI_VENDOR_ID_WINBOND2
;
1098 rdev
->input_id
.product
= nvt
->chip_major
;
1099 rdev
->input_id
.version
= nvt
->chip_minor
;
1100 rdev
->dev
.parent
= &pdev
->dev
;
1101 rdev
->driver_name
= NVT_DRIVER_NAME
;
1102 rdev
->map_name
= RC_MAP_RC6_MCE
;
1103 rdev
->timeout
= MS_TO_NS(100);
1104 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1105 rdev
->rx_resolution
= US_TO_NS(CIR_SAMPLE_PERIOD
);
1107 rdev
->min_timeout
= XYZ
;
1108 rdev
->max_timeout
= XYZ
;
1110 rdev
->tx_resolution
= XYZ
;
1114 ret
= rc_register_device(rdev
);
1116 goto exit_free_dev_rdev
;
1119 /* now claim resources */
1120 if (!devm_request_region(&pdev
->dev
, nvt
->cir_addr
,
1121 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
))
1122 goto exit_unregister_device
;
1124 if (devm_request_irq(&pdev
->dev
, nvt
->cir_irq
, nvt_cir_isr
,
1125 IRQF_SHARED
, NVT_DRIVER_NAME
, (void *)nvt
))
1126 goto exit_unregister_device
;
1128 if (!devm_request_region(&pdev
->dev
, nvt
->cir_wake_addr
,
1129 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
"-wake"))
1130 goto exit_unregister_device
;
1132 ret
= device_create_file(&rdev
->dev
, &dev_attr_wakeup_data
);
1134 goto exit_unregister_device
;
1136 device_init_wakeup(&pdev
->dev
, true);
1138 dev_notice(&pdev
->dev
, "driver has been successfully loaded\n");
1141 cir_wake_dump_regs(nvt
);
1146 exit_unregister_device
:
1147 rc_unregister_device(rdev
);
1150 rc_free_device(rdev
);
1155 static void nvt_remove(struct pnp_dev
*pdev
)
1157 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1159 device_remove_file(&nvt
->rdev
->dev
, &dev_attr_wakeup_data
);
1161 nvt_disable_cir(nvt
);
1163 /* enable CIR Wake (for IR power-on) */
1164 nvt_enable_wake(nvt
);
1166 rc_unregister_device(nvt
->rdev
);
1169 static int nvt_suspend(struct pnp_dev
*pdev
, pm_message_t state
)
1171 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1172 unsigned long flags
;
1174 nvt_dbg("%s called", __func__
);
1176 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
1177 nvt
->tx
.tx_state
= ST_TX_NONE
;
1178 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
1180 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
1182 /* disable all CIR interrupts */
1183 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
1185 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
1187 /* disable cir logical dev */
1188 nvt_disable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
1190 /* make sure wake is enabled */
1191 nvt_enable_wake(nvt
);
1196 static int nvt_resume(struct pnp_dev
*pdev
)
1198 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1200 nvt_dbg("%s called", __func__
);
1202 nvt_cir_regs_init(nvt
);
1203 nvt_cir_wake_regs_init(nvt
);
1208 static void nvt_shutdown(struct pnp_dev
*pdev
)
1210 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1212 nvt_enable_wake(nvt
);
1215 static const struct pnp_device_id nvt_ids
[] = {
1216 { "WEC0530", 0 }, /* CIR */
1217 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1221 static struct pnp_driver nvt_driver
= {
1222 .name
= NVT_DRIVER_NAME
,
1223 .id_table
= nvt_ids
,
1224 .flags
= PNP_DRIVER_RES_DO_NOT_CHANGE
,
1226 .remove
= nvt_remove
,
1227 .suspend
= nvt_suspend
,
1228 .resume
= nvt_resume
,
1229 .shutdown
= nvt_shutdown
,
1232 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
1233 MODULE_PARM_DESC(debug
, "Enable debugging output");
1235 MODULE_DEVICE_TABLE(pnp
, nvt_ids
);
1236 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1238 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1239 MODULE_LICENSE("GPL");
1241 module_pnp_driver(nvt_driver
);