drivers/gpu/drm/amd/include/vi_structs.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef VI_STRUCTS_H_
  25 #define VI_STRUCTS_H_
  26
  27 struct vi_sdma_mqd {
  28         uint32_t sdmax_rlcx_rb_cntl;
  29         uint32_t sdmax_rlcx_rb_base;
  30         uint32_t sdmax_rlcx_rb_base_hi;
  31         uint32_t sdmax_rlcx_rb_rptr;
  32         uint32_t sdmax_rlcx_rb_wptr;
  33         uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
  34         uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
  35         uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
  36         uint32_t sdmax_rlcx_rb_rptr_addr_hi;
  37         uint32_t sdmax_rlcx_rb_rptr_addr_lo;
  38         uint32_t sdmax_rlcx_ib_cntl;
  39         uint32_t sdmax_rlcx_ib_rptr;
  40         uint32_t sdmax_rlcx_ib_offset;
  41         uint32_t sdmax_rlcx_ib_base_lo;
  42         uint32_t sdmax_rlcx_ib_base_hi;
  43         uint32_t sdmax_rlcx_ib_size;
  44         uint32_t sdmax_rlcx_skip_cntl;
  45         uint32_t sdmax_rlcx_context_status;
  46         uint32_t sdmax_rlcx_doorbell;
  47         uint32_t sdmax_rlcx_virtual_addr;
  48         uint32_t sdmax_rlcx_ape1_cntl;
  49         uint32_t sdmax_rlcx_doorbell_log;
  50         uint32_t reserved_22;
  51         uint32_t reserved_23;
  52         uint32_t reserved_24;
  53         uint32_t reserved_25;
  54         uint32_t reserved_26;
  55         uint32_t reserved_27;
  56         uint32_t reserved_28;
  57         uint32_t reserved_29;
  58         uint32_t reserved_30;
  59         uint32_t reserved_31;
  60         uint32_t reserved_32;
  61         uint32_t reserved_33;
  62         uint32_t reserved_34;
  63         uint32_t reserved_35;
  64         uint32_t reserved_36;
  65         uint32_t reserved_37;
  66         uint32_t reserved_38;
  67         uint32_t reserved_39;
  68         uint32_t reserved_40;
  69         uint32_t reserved_41;
  70         uint32_t reserved_42;
  71         uint32_t reserved_43;
  72         uint32_t reserved_44;
  73         uint32_t reserved_45;
  74         uint32_t reserved_46;
  75         uint32_t reserved_47;
  76         uint32_t reserved_48;
  77         uint32_t reserved_49;
  78         uint32_t reserved_50;
  79         uint32_t reserved_51;
  80         uint32_t reserved_52;
  81         uint32_t reserved_53;
  82         uint32_t reserved_54;
  83         uint32_t reserved_55;
  84         uint32_t reserved_56;
  85         uint32_t reserved_57;
  86         uint32_t reserved_58;
  87         uint32_t reserved_59;
  88         uint32_t reserved_60;
  89         uint32_t reserved_61;
  90         uint32_t reserved_62;
  91         uint32_t reserved_63;
  92         uint32_t reserved_64;
  93         uint32_t reserved_65;
  94         uint32_t reserved_66;
  95         uint32_t reserved_67;
  96         uint32_t reserved_68;
  97         uint32_t reserved_69;
  98         uint32_t reserved_70;
  99         uint32_t reserved_71;
 100         uint32_t reserved_72;
 101         uint32_t reserved_73;
 102         uint32_t reserved_74;
 103         uint32_t reserved_75;
 104         uint32_t reserved_76;
 105         uint32_t reserved_77;
 106         uint32_t reserved_78;
 107         uint32_t reserved_79;
 108         uint32_t reserved_80;
 109         uint32_t reserved_81;
 110         uint32_t reserved_82;
 111         uint32_t reserved_83;
 112         uint32_t reserved_84;
 113         uint32_t reserved_85;
 114         uint32_t reserved_86;
 115         uint32_t reserved_87;
 116         uint32_t reserved_88;
 117         uint32_t reserved_89;
 118         uint32_t reserved_90;
 119         uint32_t reserved_91;
 120         uint32_t reserved_92;
 121         uint32_t reserved_93;
 122         uint32_t reserved_94;
 123         uint32_t reserved_95;
 124         uint32_t reserved_96;
 125         uint32_t reserved_97;
 126         uint32_t reserved_98;
 127         uint32_t reserved_99;
 128         uint32_t reserved_100;
 129         uint32_t reserved_101;
 130         uint32_t reserved_102;
 131         uint32_t reserved_103;
 132         uint32_t reserved_104;
 133         uint32_t reserved_105;
 134         uint32_t reserved_106;
 135         uint32_t reserved_107;
 136         uint32_t reserved_108;
 137         uint32_t reserved_109;
 138         uint32_t reserved_110;
 139         uint32_t reserved_111;
 140         uint32_t reserved_112;
 141         uint32_t reserved_113;
 142         uint32_t reserved_114;
 143         uint32_t reserved_115;
 144         uint32_t reserved_116;
 145         uint32_t reserved_117;
 146         uint32_t reserved_118;
 147         uint32_t reserved_119;
 148         uint32_t reserved_120;
 149         uint32_t reserved_121;
 150         uint32_t reserved_122;
 151         uint32_t reserved_123;
 152         uint32_t reserved_124;
 153         uint32_t reserved_125;
 154         uint32_t reserved_126;
 155         uint32_t reserved_127;
 156 };
 157
 158 struct vi_mqd {
 159         uint32_t header;
 160         uint32_t compute_dispatch_initiator;
 161         uint32_t compute_dim_x;
 162         uint32_t compute_dim_y;
 163         uint32_t compute_dim_z;
 164         uint32_t compute_start_x;
 165         uint32_t compute_start_y;
 166         uint32_t compute_start_z;
 167         uint32_t compute_num_thread_x;
 168         uint32_t compute_num_thread_y;
 169         uint32_t compute_num_thread_z;
 170         uint32_t compute_pipelinestat_enable;
 171         uint32_t compute_perfcount_enable;
 172         uint32_t compute_pgm_lo;
 173         uint32_t compute_pgm_hi;
 174         uint32_t compute_tba_lo;
 175         uint32_t compute_tba_hi;
 176         uint32_t compute_tma_lo;
 177         uint32_t compute_tma_hi;
 178         uint32_t compute_pgm_rsrc1;
 179         uint32_t compute_pgm_rsrc2;
 180         uint32_t compute_vmid;
 181         uint32_t compute_resource_limits;
 182         uint32_t compute_static_thread_mgmt_se0;
 183         uint32_t compute_static_thread_mgmt_se1;
 184         uint32_t compute_tmpring_size;
 185         uint32_t compute_static_thread_mgmt_se2;
 186         uint32_t compute_static_thread_mgmt_se3;
 187         uint32_t compute_restart_x;
 188         uint32_t compute_restart_y;
 189         uint32_t compute_restart_z;
 190         uint32_t compute_thread_trace_enable;
 191         uint32_t compute_misc_reserved;
 192         uint32_t compute_dispatch_id;
 193         uint32_t compute_threadgroup_id;
 194         uint32_t compute_relaunch;
 195         uint32_t compute_wave_restore_addr_lo;
 196         uint32_t compute_wave_restore_addr_hi;
 197         uint32_t compute_wave_restore_control;
 198         uint32_t reserved_39;
 199         uint32_t reserved_40;
 200         uint32_t reserved_41;
 201         uint32_t reserved_42;
 202         uint32_t reserved_43;
 203         uint32_t reserved_44;
 204         uint32_t reserved_45;
 205         uint32_t reserved_46;
 206         uint32_t reserved_47;
 207         uint32_t reserved_48;
 208         uint32_t reserved_49;
 209         uint32_t reserved_50;
 210         uint32_t reserved_51;
 211         uint32_t reserved_52;
 212         uint32_t reserved_53;
 213         uint32_t reserved_54;
 214         uint32_t reserved_55;
 215         uint32_t reserved_56;
 216         uint32_t reserved_57;
 217         uint32_t reserved_58;
 218         uint32_t reserved_59;
 219         uint32_t reserved_60;
 220         uint32_t reserved_61;
 221         uint32_t reserved_62;
 222         uint32_t reserved_63;
 223         uint32_t reserved_64;
 224         uint32_t compute_user_data_0;
 225         uint32_t compute_user_data_1;
 226         uint32_t compute_user_data_2;
 227         uint32_t compute_user_data_3;
 228         uint32_t compute_user_data_4;
 229         uint32_t compute_user_data_5;
 230         uint32_t compute_user_data_6;
 231         uint32_t compute_user_data_7;
 232         uint32_t compute_user_data_8;
 233         uint32_t compute_user_data_9;
 234         uint32_t compute_user_data_10;
 235         uint32_t compute_user_data_11;
 236         uint32_t compute_user_data_12;
 237         uint32_t compute_user_data_13;
 238         uint32_t compute_user_data_14;
 239         uint32_t compute_user_data_15;
 240         uint32_t cp_compute_csinvoc_count_lo;
 241         uint32_t cp_compute_csinvoc_count_hi;
 242         uint32_t reserved_83;
 243         uint32_t reserved_84;
 244         uint32_t reserved_85;
 245         uint32_t cp_mqd_query_time_lo;
 246         uint32_t cp_mqd_query_time_hi;
 247         uint32_t cp_mqd_connect_start_time_lo;
 248         uint32_t cp_mqd_connect_start_time_hi;
 249         uint32_t cp_mqd_connect_end_time_lo;
 250         uint32_t cp_mqd_connect_end_time_hi;
 251         uint32_t cp_mqd_connect_end_wf_count;
 252         uint32_t cp_mqd_connect_end_pq_rptr;
 253         uint32_t cp_mqd_connect_end_pq_wptr;
 254         uint32_t cp_mqd_connect_end_ib_rptr;
 255         uint32_t reserved_96;
 256         uint32_t reserved_97;
 257         uint32_t cp_mqd_save_start_time_lo;
 258         uint32_t cp_mqd_save_start_time_hi;
 259         uint32_t cp_mqd_save_end_time_lo;
 260         uint32_t cp_mqd_save_end_time_hi;
 261         uint32_t cp_mqd_restore_start_time_lo;
 262         uint32_t cp_mqd_restore_start_time_hi;
 263         uint32_t cp_mqd_restore_end_time_lo;
 264         uint32_t cp_mqd_restore_end_time_hi;
 265         uint32_t reserved_106;
 266         uint32_t reserved_107;
 267         uint32_t gds_cs_ctxsw_cnt0;
 268         uint32_t gds_cs_ctxsw_cnt1;
 269         uint32_t gds_cs_ctxsw_cnt2;
 270         uint32_t gds_cs_ctxsw_cnt3;
 271         uint32_t reserved_112;
 272         uint32_t reserved_113;
 273         uint32_t cp_pq_exe_status_lo;
 274         uint32_t cp_pq_exe_status_hi;
 275         uint32_t cp_packet_id_lo;
 276         uint32_t cp_packet_id_hi;
 277         uint32_t cp_packet_exe_status_lo;
 278         uint32_t cp_packet_exe_status_hi;
 279         uint32_t gds_save_base_addr_lo;
 280         uint32_t gds_save_base_addr_hi;
 281         uint32_t gds_save_mask_lo;
 282         uint32_t gds_save_mask_hi;
 283         uint32_t ctx_save_base_addr_lo;
 284         uint32_t ctx_save_base_addr_hi;
 285         uint32_t reserved_126;
 286         uint32_t reserved_127;
 287         uint32_t cp_mqd_base_addr_lo;
 288         uint32_t cp_mqd_base_addr_hi;
 289         uint32_t cp_hqd_active;
 290         uint32_t cp_hqd_vmid;
 291         uint32_t cp_hqd_persistent_state;
 292         uint32_t cp_hqd_pipe_priority;
 293         uint32_t cp_hqd_queue_priority;
 294         uint32_t cp_hqd_quantum;
 295         uint32_t cp_hqd_pq_base_lo;
 296         uint32_t cp_hqd_pq_base_hi;
 297         uint32_t cp_hqd_pq_rptr;
 298         uint32_t cp_hqd_pq_rptr_report_addr_lo;
 299         uint32_t cp_hqd_pq_rptr_report_addr_hi;
 300         uint32_t cp_hqd_pq_wptr_poll_addr_lo;
 301         uint32_t cp_hqd_pq_wptr_poll_addr_hi;
 302         uint32_t cp_hqd_pq_doorbell_control;
 303         uint32_t cp_hqd_pq_wptr;
 304         uint32_t cp_hqd_pq_control;
 305         uint32_t cp_hqd_ib_base_addr_lo;
 306         uint32_t cp_hqd_ib_base_addr_hi;
 307         uint32_t cp_hqd_ib_rptr;
 308         uint32_t cp_hqd_ib_control;
 309         uint32_t cp_hqd_iq_timer;
 310         uint32_t cp_hqd_iq_rptr;
 311         uint32_t cp_hqd_dequeue_request;
 312         uint32_t cp_hqd_dma_offload;
 313         uint32_t cp_hqd_sema_cmd;
 314         uint32_t cp_hqd_msg_type;
 315         uint32_t cp_hqd_atomic0_preop_lo;
 316         uint32_t cp_hqd_atomic0_preop_hi;
 317         uint32_t cp_hqd_atomic1_preop_lo;
 318         uint32_t cp_hqd_atomic1_preop_hi;
 319         uint32_t cp_hqd_hq_status0;
 320         uint32_t cp_hqd_hq_control0;
 321         uint32_t cp_mqd_control;
 322         uint32_t cp_hqd_hq_status1;
 323         uint32_t cp_hqd_hq_control1;
 324         uint32_t cp_hqd_eop_base_addr_lo;
 325         uint32_t cp_hqd_eop_base_addr_hi;
 326         uint32_t cp_hqd_eop_control;
 327         uint32_t cp_hqd_eop_rptr;
 328         uint32_t cp_hqd_eop_wptr;
 329         uint32_t cp_hqd_eop_done_events;
 330         uint32_t cp_hqd_ctx_save_base_addr_lo;
 331         uint32_t cp_hqd_ctx_save_base_addr_hi;
 332         uint32_t cp_hqd_ctx_save_control;
 333         uint32_t cp_hqd_cntl_stack_offset;
 334         uint32_t cp_hqd_cntl_stack_size;
 335         uint32_t cp_hqd_wg_state_offset;
 336         uint32_t cp_hqd_ctx_save_size;
 337         uint32_t cp_hqd_gds_resource_state;
 338         uint32_t cp_hqd_error;
 339         uint32_t cp_hqd_eop_wptr_mem;
 340         uint32_t cp_hqd_eop_dones;
 341         uint32_t reserved_182;
 342         uint32_t reserved_183;
 343         uint32_t reserved_184;
 344         uint32_t reserved_185;
 345         uint32_t reserved_186;
 346         uint32_t reserved_187;
 347         uint32_t reserved_188;
 348         uint32_t reserved_189;
 349         uint32_t reserved_190;
 350         uint32_t reserved_191;
 351         uint32_t iqtimer_pkt_header;
 352         uint32_t iqtimer_pkt_dw0;
 353         uint32_t iqtimer_pkt_dw1;
 354         uint32_t iqtimer_pkt_dw2;
 355         uint32_t iqtimer_pkt_dw3;
 356         uint32_t iqtimer_pkt_dw4;
 357         uint32_t iqtimer_pkt_dw5;
 358         uint32_t iqtimer_pkt_dw6;
 359         uint32_t iqtimer_pkt_dw7;
 360         uint32_t iqtimer_pkt_dw8;
 361         uint32_t iqtimer_pkt_dw9;
 362         uint32_t iqtimer_pkt_dw10;
 363         uint32_t iqtimer_pkt_dw11;
 364         uint32_t iqtimer_pkt_dw12;
 365         uint32_t iqtimer_pkt_dw13;
 366         uint32_t iqtimer_pkt_dw14;
 367         uint32_t iqtimer_pkt_dw15;
 368         uint32_t iqtimer_pkt_dw16;
 369         uint32_t iqtimer_pkt_dw17;
 370         uint32_t iqtimer_pkt_dw18;
 371         uint32_t iqtimer_pkt_dw19;
 372         uint32_t iqtimer_pkt_dw20;
 373         uint32_t iqtimer_pkt_dw21;
 374         uint32_t iqtimer_pkt_dw22;
 375         uint32_t iqtimer_pkt_dw23;
 376         uint32_t iqtimer_pkt_dw24;
 377         uint32_t iqtimer_pkt_dw25;
 378         uint32_t iqtimer_pkt_dw26;
 379         uint32_t iqtimer_pkt_dw27;
 380         uint32_t iqtimer_pkt_dw28;
 381         uint32_t iqtimer_pkt_dw29;
 382         uint32_t iqtimer_pkt_dw30;
 383         uint32_t iqtimer_pkt_dw31;
 384         uint32_t reserved_225;
 385         uint32_t reserved_226;
 386         uint32_t reserved_227;
 387         uint32_t set_resources_header;
 388         uint32_t set_resources_dw1;
 389         uint32_t set_resources_dw2;
 390         uint32_t set_resources_dw3;
 391         uint32_t set_resources_dw4;
 392         uint32_t set_resources_dw5;
 393         uint32_t set_resources_dw6;
 394         uint32_t set_resources_dw7;
 395         uint32_t reserved_236;
 396         uint32_t reserved_237;
 397         uint32_t reserved_238;
 398         uint32_t reserved_239;
 399         uint32_t queue_doorbell_id0;
 400         uint32_t queue_doorbell_id1;
 401         uint32_t queue_doorbell_id2;
 402         uint32_t queue_doorbell_id3;
 403         uint32_t queue_doorbell_id4;
 404         uint32_t queue_doorbell_id5;
 405         uint32_t queue_doorbell_id6;
 406         uint32_t queue_doorbell_id7;
 407         uint32_t queue_doorbell_id8;
 408         uint32_t queue_doorbell_id9;
 409         uint32_t queue_doorbell_id10;
 410         uint32_t queue_doorbell_id11;
 411         uint32_t queue_doorbell_id12;
 412         uint32_t queue_doorbell_id13;
 413         uint32_t queue_doorbell_id14;
 414         uint32_t queue_doorbell_id15;
 415 };
 416
 417 #endif /* VI_STRUCTS_H_ */