drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24
  25 #ifndef _FIJI_PP_SMC_H_
  26 #define _FIJI_PP_SMC_H_
  27
  28 #pragma pack(push, 1)
  29
  30 #define PPSMC_SWSTATE_FLAG_DC                           0x01
  31 #define PPSMC_SWSTATE_FLAG_UVD                          0x02
  32 #define PPSMC_SWSTATE_FLAG_VCE                          0x04
  33
  34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
  35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
  36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff
  37
  38 #define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01
  39 #define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02
  40 #define PPSMC_SYSTEMFLAG_GDDR5                          0x04
  41
  42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08
  43
  44 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10
  45 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20
  46
  47 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
  48 #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
  49
  50 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
  51 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
  52
  53 /* Defines for DPM 2.0 */
  54 #define PPSMC_DPM2FLAGS_TDPCLMP                         0x01
  55 #define PPSMC_DPM2FLAGS_PWRSHFT                         0x02
  56 #define PPSMC_DPM2FLAGS_OCP                             0x04
  57
  58 /* Defines for display watermark level */
  59 #define PPSMC_DISPLAY_WATERMARK_LOW                     0
  60 #define PPSMC_DISPLAY_WATERMARK_HIGH                    1
  61
  62 /* In the HW performance level's state flags: */
  63 #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    0x01
  64 #define PPSMC_STATEFLAG_POWERBOOST         0x02
  65 #define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
  66 #define PPSMC_STATEFLAG_POWERSHIFT         0x08
  67 #define PPSMC_STATEFLAG_SLOW_READ_MARGIN   0x10
  68 #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
  69 #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40
  70
  71 /* Fan control algorithm: */
  72 #define FDO_MODE_HARDWARE 0
  73 #define FDO_MODE_PIECE_WISE_LINEAR 1
  74
  75 enum FAN_CONTROL {
  76   FAN_CONTROL_FUZZY,
  77   FAN_CONTROL_TABLE
  78 };
  79
  80 /* Gemini Modes*/
  81 #define PPSMC_GeminiModeNone   0  /*Single GPU board*/
  82 #define PPSMC_GeminiModeMaster 1  /*Master GPU on a Gemini board*/
  83 #define PPSMC_GeminiModeSlave  2  /*Slave GPU on a Gemini board*/
  84
  85
  86 /* Return codes for driver to SMC communication. */
  87 #define PPSMC_Result_OK             ((uint16_t)0x01)
  88 #define PPSMC_Result_NoMore         ((uint16_t)0x02)
  89
  90 #define PPSMC_Result_NotNow         ((uint16_t)0x03)
  91
  92 #define PPSMC_Result_Failed         ((uint16_t)0xFF)
  93 #define PPSMC_Result_UnknownCmd     ((uint16_t)0xFE)
  94 #define PPSMC_Result_UnknownVT      ((uint16_t)0xFD)
  95
  96 #define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
  97
  98
  99 #define PPSMC_MSG_Halt                      ((uint16_t)0x10)
 100 #define PPSMC_MSG_Resume                    ((uint16_t)0x11)
 101 #define PPSMC_MSG_EnableDPMLevel            ((uint16_t)0x12)
 102 #define PPSMC_MSG_ZeroLevelsDisabled        ((uint16_t)0x13)
 103 #define PPSMC_MSG_OneLevelsDisabled         ((uint16_t)0x14)
 104 #define PPSMC_MSG_TwoLevelsDisabled         ((uint16_t)0x15)
 105 #define PPSMC_MSG_EnableThermalInterrupt    ((uint16_t)0x16)
 106 #define PPSMC_MSG_RunningOnAC               ((uint16_t)0x17)
 107 #define PPSMC_MSG_LevelUp                   ((uint16_t)0x18)
 108 #define PPSMC_MSG_LevelDown                 ((uint16_t)0x19)
 109 #define PPSMC_MSG_ResetDPMCounters          ((uint16_t)0x1a)
 110 #define PPSMC_MSG_SwitchToSwState           ((uint16_t)0x20)
 111
 112 #define PPSMC_MSG_SwitchToSwStateLast       ((uint16_t)0x3f)
 113 #define PPSMC_MSG_SwitchToInitialState      ((uint16_t)0x40)
 114 #define PPSMC_MSG_NoForcedLevel             ((uint16_t)0x41)
 115 #define PPSMC_MSG_ForceHigh                 ((uint16_t)0x42)
 116 #define PPSMC_MSG_ForceMediumOrHigh         ((uint16_t)0x43)
 117
 118 #define PPSMC_MSG_SwitchToMinimumPower      ((uint16_t)0x51)
 119 #define PPSMC_MSG_ResumeFromMinimumPower    ((uint16_t)0x52)
 120 #define PPSMC_MSG_EnableCac                 ((uint16_t)0x53)
 121 #define PPSMC_MSG_DisableCac                ((uint16_t)0x54)
 122 #define PPSMC_DPMStateHistoryStart          ((uint16_t)0x55)
 123 #define PPSMC_DPMStateHistoryStop           ((uint16_t)0x56)
 124 #define PPSMC_CACHistoryStart               ((uint16_t)0x57)
 125 #define PPSMC_CACHistoryStop                ((uint16_t)0x58)
 126 #define PPSMC_TDPClampingActive             ((uint16_t)0x59)
 127 #define PPSMC_TDPClampingInactive           ((uint16_t)0x5A)
 128 #define PPSMC_StartFanControl               ((uint16_t)0x5B)
 129 #define PPSMC_StopFanControl                ((uint16_t)0x5C)
 130 #define PPSMC_NoDisplay                     ((uint16_t)0x5D)
 131 #define PPSMC_HasDisplay                    ((uint16_t)0x5E)
 132 #define PPSMC_MSG_UVDPowerOFF               ((uint16_t)0x60)
 133 #define PPSMC_MSG_UVDPowerON                ((uint16_t)0x61)
 134 #define PPSMC_MSG_EnableULV                 ((uint16_t)0x62)
 135 #define PPSMC_MSG_DisableULV                ((uint16_t)0x63)
 136 #define PPSMC_MSG_EnterULV                  ((uint16_t)0x64)
 137 #define PPSMC_MSG_ExitULV                   ((uint16_t)0x65)
 138 #define PPSMC_PowerShiftActive              ((uint16_t)0x6A)
 139 #define PPSMC_PowerShiftInactive            ((uint16_t)0x6B)
 140 #define PPSMC_OCPActive                     ((uint16_t)0x6C)
 141 #define PPSMC_OCPInactive                   ((uint16_t)0x6D)
 142 #define PPSMC_CACLongTermAvgEnable          ((uint16_t)0x6E)
 143 #define PPSMC_CACLongTermAvgDisable         ((uint16_t)0x6F)
 144 #define PPSMC_MSG_InferredStateSweep_Start  ((uint16_t)0x70)
 145 #define PPSMC_MSG_InferredStateSweep_Stop   ((uint16_t)0x71)
 146 #define PPSMC_MSG_SwitchToLowestInfState    ((uint16_t)0x72)
 147 #define PPSMC_MSG_SwitchToNonInfState       ((uint16_t)0x73)
 148 #define PPSMC_MSG_AllStateSweep_Start       ((uint16_t)0x74)
 149 #define PPSMC_MSG_AllStateSweep_Stop        ((uint16_t)0x75)
 150 #define PPSMC_MSG_SwitchNextLowerInfState   ((uint16_t)0x76)
 151 #define PPSMC_MSG_SwitchNextHigherInfState  ((uint16_t)0x77)
 152 #define PPSMC_MSG_MclkRetrainingTest        ((uint16_t)0x78)
 153 #define PPSMC_MSG_ForceTDPClamping          ((uint16_t)0x79)
 154 #define PPSMC_MSG_CollectCAC_PowerCorreln   ((uint16_t)0x7A)
 155 #define PPSMC_MSG_CollectCAC_WeightCalib    ((uint16_t)0x7B)
 156 #define PPSMC_MSG_CollectCAC_SQonly         ((uint16_t)0x7C)
 157 #define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
 158
 159 #define PPSMC_MSG_ExtremitiesTest_Start     ((uint16_t)0x7E)
 160 #define PPSMC_MSG_ExtremitiesTest_Stop      ((uint16_t)0x7F)
 161 #define PPSMC_FlushDataCache                ((uint16_t)0x80)
 162 #define PPSMC_FlushInstrCache               ((uint16_t)0x81)
 163
 164 #define PPSMC_MSG_SetEnabledLevels          ((uint16_t)0x82)
 165 #define PPSMC_MSG_SetForcedLevels           ((uint16_t)0x83)
 166
 167 #define PPSMC_MSG_ResetToDefaults           ((uint16_t)0x84)
 168
 169 #define PPSMC_MSG_SetForcedLevelsAndJump      ((uint16_t)0x85)
 170 #define PPSMC_MSG_SetCACHistoryMode           ((uint16_t)0x86)
 171 #define PPSMC_MSG_EnableDTE                   ((uint16_t)0x87)
 172 #define PPSMC_MSG_DisableDTE                  ((uint16_t)0x88)
 173
 174 #define PPSMC_MSG_SmcSpaceSetAddress          ((uint16_t)0x89)
 175
 176 #define PPSMC_MSG_BREAK                       ((uint16_t)0xF8)
 177
 178 /* Trinity Specific Messages*/
 179 #define PPSMC_MSG_Test                        ((uint16_t) 0x100)
 180 #define PPSMC_MSG_DPM_Voltage_Pwrmgt          ((uint16_t) 0x101)
 181 #define PPSMC_MSG_DPM_Config                  ((uint16_t) 0x102)
 182 #define PPSMC_MSG_PM_Controller_Start         ((uint16_t) 0x103)
 183 #define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)
 184 #define PPSMC_MSG_PG_PowerDownSIMD            ((uint16_t) 0x105)
 185 #define PPSMC_MSG_PG_PowerUpSIMD              ((uint16_t) 0x106)
 186 #define PPSMC_MSG_PM_Controller_Stop          ((uint16_t) 0x107)
 187 #define PPSMC_MSG_PG_SIMD_Config              ((uint16_t) 0x108)
 188 #define PPSMC_MSG_Voltage_Cntl_Enable         ((uint16_t) 0x109)
 189 #define PPSMC_MSG_Thermal_Cntl_Enable         ((uint16_t) 0x10a)
 190 #define PPSMC_MSG_Reset_Service               ((uint16_t) 0x10b)
 191 #define PPSMC_MSG_VCEPowerOFF                 ((uint16_t) 0x10e)
 192 #define PPSMC_MSG_VCEPowerON                  ((uint16_t) 0x10f)
 193 #define PPSMC_MSG_DPM_Disable_VCE_HS          ((uint16_t) 0x110)
 194 #define PPSMC_MSG_DPM_Enable_VCE_HS           ((uint16_t) 0x111)
 195 #define PPSMC_MSG_DPM_N_LevelsDisabled        ((uint16_t) 0x112)
 196 #define PPSMC_MSG_DCEPowerOFF                 ((uint16_t) 0x113)
 197 #define PPSMC_MSG_DCEPowerON                  ((uint16_t) 0x114)
 198 #define PPSMC_MSG_PCIE_DDIPowerDown           ((uint16_t) 0x117)
 199 #define PPSMC_MSG_PCIE_DDIPowerUp             ((uint16_t) 0x118)
 200 #define PPSMC_MSG_PCIE_CascadePLLPowerDown    ((uint16_t) 0x119)
 201 #define PPSMC_MSG_PCIE_CascadePLLPowerUp      ((uint16_t) 0x11a)
 202 #define PPSMC_MSG_SYSPLLPowerOff              ((uint16_t) 0x11b)
 203 #define PPSMC_MSG_SYSPLLPowerOn               ((uint16_t) 0x11c)
 204 #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
 205 #define PPSMC_MSG_DCE_AllowVoltageAdjustment  ((uint16_t) 0x11e)
 206 #define PPSMC_MSG_DISPLAYPHYStatusNotify      ((uint16_t) 0x11f)
 207 #define PPSMC_MSG_EnableBAPM                  ((uint16_t) 0x120)
 208 #define PPSMC_MSG_DisableBAPM                 ((uint16_t) 0x121)
 209 #define PPSMC_MSG_Spmi_Enable                 ((uint16_t) 0x122)
 210 #define PPSMC_MSG_Spmi_Timer                  ((uint16_t) 0x123)
 211 #define PPSMC_MSG_LCLK_DPM_Config             ((uint16_t) 0x124)
 212 #define PPSMC_MSG_VddNB_Request               ((uint16_t) 0x125)
 213 #define PPSMC_MSG_PCIE_DDIPhyPowerDown        ((uint32_t) 0x126)
 214 #define PPSMC_MSG_PCIE_DDIPhyPowerUp          ((uint32_t) 0x127)
 215 #define PPSMC_MSG_MCLKDPM_Config              ((uint16_t) 0x128)
 216
 217 #define PPSMC_MSG_UVDDPM_Config               ((uint16_t) 0x129)
 218 #define PPSMC_MSG_VCEDPM_Config               ((uint16_t) 0x12A)
 219 #define PPSMC_MSG_ACPDPM_Config               ((uint16_t) 0x12B)
 220 #define PPSMC_MSG_SAMUDPM_Config              ((uint16_t) 0x12C)
 221 #define PPSMC_MSG_UVDDPM_SetEnabledMask       ((uint16_t) 0x12D)
 222 #define PPSMC_MSG_VCEDPM_SetEnabledMask       ((uint16_t) 0x12E)
 223 #define PPSMC_MSG_ACPDPM_SetEnabledMask       ((uint16_t) 0x12F)
 224 #define PPSMC_MSG_SAMUDPM_SetEnabledMask      ((uint16_t) 0x130)
 225 #define PPSMC_MSG_MCLKDPM_ForceState          ((uint16_t) 0x131)
 226 #define PPSMC_MSG_MCLKDPM_NoForcedLevel       ((uint16_t) 0x132)
 227 #define PPSMC_MSG_Thermal_Cntl_Disable        ((uint16_t) 0x133)
 228 #define PPSMC_MSG_SetTDPLimit                 ((uint16_t) 0x134)
 229 #define PPSMC_MSG_Voltage_Cntl_Disable        ((uint16_t) 0x135)
 230 #define PPSMC_MSG_PCIeDPM_Enable              ((uint16_t) 0x136)
 231 #define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0x137)
 232 #define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0x138)
 233 #define PPSMC_MSG_SAMPowerOFF                 ((uint16_t) 0x139)
 234 #define PPSMC_MSG_SAMPowerON                  ((uint16_t) 0x13a)
 235 #define PPSMC_MSG_SDMAPowerOFF                ((uint16_t) 0x13b)
 236 #define PPSMC_MSG_SDMAPowerON                 ((uint16_t) 0x13c)
 237 #define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
 238 #define PPSMC_MSG_IOMMUPowerOFF               ((uint16_t) 0x13e)
 239 #define PPSMC_MSG_IOMMUPowerON                ((uint16_t) 0x13f)
 240 #define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
 241 #define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
 242 #define PPSMC_MSG_NBDPM_ForceNominal          ((uint16_t) 0x142)
 243 #define PPSMC_MSG_NBDPM_ForcePerformance      ((uint16_t) 0x143)
 244 #define PPSMC_MSG_NBDPM_UnForce               ((uint16_t) 0x144)
 245 #define PPSMC_MSG_SCLKDPM_SetEnabledMask      ((uint16_t) 0x145)
 246 #define PPSMC_MSG_MCLKDPM_SetEnabledMask      ((uint16_t) 0x146)
 247 #define PPSMC_MSG_PCIeDPM_ForceLevel          ((uint16_t) 0x147)
 248 #define PPSMC_MSG_PCIeDPM_UnForceLevel        ((uint16_t) 0x148)
 249 #define PPSMC_MSG_EnableACDCGPIOInterrupt     ((uint16_t) 0x149)
 250 #define PPSMC_MSG_EnableVRHotGPIOInterrupt    ((uint16_t) 0x14a)
 251 #define PPSMC_MSG_SwitchToAC                  ((uint16_t) 0x14b)
 252
 253 #define PPSMC_MSG_XDMAPowerOFF                ((uint16_t) 0x14c)
 254 #define PPSMC_MSG_XDMAPowerON                 ((uint16_t) 0x14d)
 255
 256 #define PPSMC_MSG_DPM_Enable                  ((uint16_t) 0x14e)
 257 #define PPSMC_MSG_DPM_Disable                 ((uint16_t) 0x14f)
 258 #define PPSMC_MSG_MCLKDPM_Enable              ((uint16_t) 0x150)
 259 #define PPSMC_MSG_MCLKDPM_Disable             ((uint16_t) 0x151)
 260 #define PPSMC_MSG_LCLKDPM_Enable              ((uint16_t) 0x152)
 261 #define PPSMC_MSG_LCLKDPM_Disable             ((uint16_t) 0x153)
 262 #define PPSMC_MSG_UVDDPM_Enable               ((uint16_t) 0x154)
 263 #define PPSMC_MSG_UVDDPM_Disable              ((uint16_t) 0x155)
 264 #define PPSMC_MSG_SAMUDPM_Enable              ((uint16_t) 0x156)
 265 #define PPSMC_MSG_SAMUDPM_Disable             ((uint16_t) 0x157)
 266 #define PPSMC_MSG_ACPDPM_Enable               ((uint16_t) 0x158)
 267 #define PPSMC_MSG_ACPDPM_Disable              ((uint16_t) 0x159)
 268 #define PPSMC_MSG_VCEDPM_Enable               ((uint16_t) 0x15a)
 269 #define PPSMC_MSG_VCEDPM_Disable              ((uint16_t) 0x15b)
 270 #define PPSMC_MSG_LCLKDPM_SetEnabledMask      ((uint16_t) 0x15c)
 271 #define PPSMC_MSG_DPM_FPS_Mode                ((uint16_t) 0x15d)
 272 #define PPSMC_MSG_DPM_Activity_Mode           ((uint16_t) 0x15e)
 273 #define PPSMC_MSG_VddC_Request                ((uint16_t) 0x15f)
 274 #define PPSMC_MSG_MCLKDPM_GetEnabledMask      ((uint16_t) 0x160)
 275 #define PPSMC_MSG_LCLKDPM_GetEnabledMask      ((uint16_t) 0x161)
 276 #define PPSMC_MSG_SCLKDPM_GetEnabledMask      ((uint16_t) 0x162)
 277 #define PPSMC_MSG_UVDDPM_GetEnabledMask       ((uint16_t) 0x163)
 278 #define PPSMC_MSG_SAMUDPM_GetEnabledMask      ((uint16_t) 0x164)
 279 #define PPSMC_MSG_ACPDPM_GetEnabledMask       ((uint16_t) 0x165)
 280 #define PPSMC_MSG_VCEDPM_GetEnabledMask       ((uint16_t) 0x166)
 281 #define PPSMC_MSG_PCIeDPM_SetEnabledMask      ((uint16_t) 0x167)
 282 #define PPSMC_MSG_PCIeDPM_GetEnabledMask      ((uint16_t) 0x168)
 283 #define PPSMC_MSG_TDCLimitEnable              ((uint16_t) 0x169)
 284 #define PPSMC_MSG_TDCLimitDisable             ((uint16_t) 0x16a)
 285 #define PPSMC_MSG_DPM_AutoRotate_Mode         ((uint16_t) 0x16b)
 286 #define PPSMC_MSG_DISPCLK_FROM_FCH            ((uint16_t) 0x16c)
 287 #define PPSMC_MSG_DISPCLK_FROM_DFS            ((uint16_t) 0x16d)
 288 #define PPSMC_MSG_DPREFCLK_FROM_FCH           ((uint16_t) 0x16e)
 289 #define PPSMC_MSG_DPREFCLK_FROM_DFS           ((uint16_t) 0x16f)
 290 #define PPSMC_MSG_PmStatusLogStart            ((uint16_t) 0x170)
 291 #define PPSMC_MSG_PmStatusLogSample           ((uint16_t) 0x171)
 292 #define PPSMC_MSG_SCLK_AutoDPM_ON             ((uint16_t) 0x172)
 293 #define PPSMC_MSG_MCLK_AutoDPM_ON             ((uint16_t) 0x173)
 294 #define PPSMC_MSG_LCLK_AutoDPM_ON             ((uint16_t) 0x174)
 295 #define PPSMC_MSG_UVD_AutoDPM_ON              ((uint16_t) 0x175)
 296 #define PPSMC_MSG_SAMU_AutoDPM_ON             ((uint16_t) 0x176)
 297 #define PPSMC_MSG_ACP_AutoDPM_ON              ((uint16_t) 0x177)
 298 #define PPSMC_MSG_VCE_AutoDPM_ON              ((uint16_t) 0x178)
 299 #define PPSMC_MSG_PCIe_AutoDPM_ON             ((uint16_t) 0x179)
 300 #define PPSMC_MSG_MASTER_AutoDPM_ON           ((uint16_t) 0x17a)
 301 #define PPSMC_MSG_MASTER_AutoDPM_OFF          ((uint16_t) 0x17b)
 302 #define PPSMC_MSG_DYNAMICDISPPHYPOWER         ((uint16_t) 0x17c)
 303 #define PPSMC_MSG_CAC_COLLECTION_ON           ((uint16_t) 0x17d)
 304 #define PPSMC_MSG_CAC_COLLECTION_OFF          ((uint16_t) 0x17e)
 305 #define PPSMC_MSG_CAC_CORRELATION_ON          ((uint16_t) 0x17f)
 306 #define PPSMC_MSG_CAC_CORRELATION_OFF         ((uint16_t) 0x180)
 307 #define PPSMC_MSG_PM_STATUS_TO_DRAM_ON        ((uint16_t) 0x181)
 308 #define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF       ((uint16_t) 0x182)
 309 #define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT     ((uint16_t) 0x184)
 310 #define PPSMC_MSG_PkgPwrLimitEnable           ((uint16_t) 0x185)
 311 #define PPSMC_MSG_PkgPwrLimitDisable          ((uint16_t) 0x186)
 312 #define PPSMC_MSG_PkgPwrSetLimit              ((uint16_t) 0x187)
 313 #define PPSMC_MSG_OverDriveSetTargetTdp       ((uint16_t) 0x188)
 314 #define PPSMC_MSG_SCLKDPM_FreezeLevel         ((uint16_t) 0x189)
 315 #define PPSMC_MSG_SCLKDPM_UnfreezeLevel       ((uint16_t) 0x18A)
 316 #define PPSMC_MSG_MCLKDPM_FreezeLevel         ((uint16_t) 0x18B)
 317 #define PPSMC_MSG_MCLKDPM_UnfreezeLevel       ((uint16_t) 0x18C)
 318 #define PPSMC_MSG_START_DRAM_LOGGING          ((uint16_t) 0x18D)
 319 #define PPSMC_MSG_STOP_DRAM_LOGGING           ((uint16_t) 0x18E)
 320 #define PPSMC_MSG_MASTER_DeepSleep_ON         ((uint16_t) 0x18F)
 321 #define PPSMC_MSG_MASTER_DeepSleep_OFF        ((uint16_t) 0x190)
 322 #define PPSMC_MSG_Remove_DC_Clamp             ((uint16_t) 0x191)
 323 #define PPSMC_MSG_DisableACDCGPIOInterrupt    ((uint16_t) 0x192)
 324 #define PPSMC_MSG_OverrideVoltageControl_SetVddc       ((uint16_t) 0x193)
 325 #define PPSMC_MSG_OverrideVoltageControl_SetVddci      ((uint16_t) 0x194)
 326 #define PPSMC_MSG_SetVidOffset_1              ((uint16_t) 0x195)
 327 #define PPSMC_MSG_SetVidOffset_2              ((uint16_t) 0x207)
 328 #define PPSMC_MSG_GetVidOffset_1              ((uint16_t) 0x196)
 329 #define PPSMC_MSG_GetVidOffset_2              ((uint16_t) 0x208)
 330 #define PPSMC_MSG_THERMAL_OVERDRIVE_Enable    ((uint16_t) 0x197)
 331 #define PPSMC_MSG_THERMAL_OVERDRIVE_Disable   ((uint16_t) 0x198)
 332 #define PPSMC_MSG_SetTjMax                    ((uint16_t) 0x199)
 333 #define PPSMC_MSG_SetFanPwmMax                ((uint16_t) 0x19A)
 334 #define PPSMC_MSG_WaitForMclkSwitchFinish     ((uint16_t) 0x19B)
 335 #define PPSMC_MSG_ENABLE_THERMAL_DPM          ((uint16_t) 0x19C)
 336 #define PPSMC_MSG_DISABLE_THERMAL_DPM         ((uint16_t) 0x19D)
 337
 338 #define PPSMC_MSG_API_GetSclkFrequency        ((uint16_t) 0x200)
 339 #define PPSMC_MSG_API_GetMclkFrequency        ((uint16_t) 0x201)
 340 #define PPSMC_MSG_API_GetSclkBusy             ((uint16_t) 0x202)
 341 #define PPSMC_MSG_API_GetMclkBusy             ((uint16_t) 0x203)
 342 #define PPSMC_MSG_API_GetAsicPower            ((uint16_t) 0x204)
 343 #define PPSMC_MSG_SetFanRpmMax                ((uint16_t) 0x205)
 344 #define PPSMC_MSG_SetFanSclkTarget            ((uint16_t) 0x206)
 345 #define PPSMC_MSG_SetFanMinPwm                ((uint16_t) 0x209)
 346 #define PPSMC_MSG_SetFanTemperatureTarget     ((uint16_t) 0x20A)
 347
 348 #define PPSMC_MSG_BACO_StartMonitor           ((uint16_t) 0x240)
 349 #define PPSMC_MSG_BACO_Cancel                 ((uint16_t) 0x241)
 350 #define PPSMC_MSG_EnableVddGfx                ((uint16_t) 0x242)
 351 #define PPSMC_MSG_DisableVddGfx               ((uint16_t) 0x243)
 352 #define PPSMC_MSG_UcodeAddressLow             ((uint16_t) 0x244)
 353 #define PPSMC_MSG_UcodeAddressHigh            ((uint16_t) 0x245)
 354 #define PPSMC_MSG_UcodeLoadStatus             ((uint16_t) 0x246)
 355
 356 #define PPSMC_MSG_DRV_DRAM_ADDR_HI            ((uint16_t) 0x250)
 357 #define PPSMC_MSG_DRV_DRAM_ADDR_LO            ((uint16_t) 0x251)
 358 #define PPSMC_MSG_SMU_DRAM_ADDR_HI            ((uint16_t) 0x252)
 359 #define PPSMC_MSG_SMU_DRAM_ADDR_LO            ((uint16_t) 0x253)
 360 #define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x254)
 361 #define PPSMC_MSG_PowerStateNotify            ((uint16_t) 0x255)
 362 #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI      ((uint16_t) 0x256)
 363 #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO      ((uint16_t) 0x257)
 364 #define PPSMC_MSG_VBIOS_DRAM_ADDR_HI          ((uint16_t) 0x258)
 365 #define PPSMC_MSG_VBIOS_DRAM_ADDR_LO          ((uint16_t) 0x259)
 366 #define PPSMC_MSG_LoadVBios                   ((uint16_t) 0x25A)
 367 #define PPSMC_MSG_GetUcodeVersion             ((uint16_t) 0x25B)
 368 #define DMCUSMC_MSG_PSREntry                  ((uint16_t) 0x25C)
 369 #define DMCUSMC_MSG_PSRExit                   ((uint16_t) 0x25D)
 370 #define PPSMC_MSG_EnableClockGatingFeature    ((uint16_t) 0x260)
 371 #define PPSMC_MSG_DisableClockGatingFeature   ((uint16_t) 0x261)
 372 #define PPSMC_MSG_IsDeviceRunning             ((uint16_t) 0x262)
 373 #define PPSMC_MSG_LoadMetaData                ((uint16_t) 0x263)
 374 #define PPSMC_MSG_TMON_AutoCaliberate_Enable  ((uint16_t) 0x264)
 375 #define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
 376 #define PPSMC_MSG_GetTelemetry1Slope          ((uint16_t) 0x266)
 377 #define PPSMC_MSG_GetTelemetry1Offset         ((uint16_t) 0x267)
 378 #define PPSMC_MSG_GetTelemetry2Slope          ((uint16_t) 0x268)
 379 #define PPSMC_MSG_GetTelemetry2Offset         ((uint16_t) 0x269)
 380 #define PPSMC_MSG_EnableAvfs                  ((uint16_t) 0x26A)
 381 #define PPSMC_MSG_DisableAvfs                 ((uint16_t) 0x26B)
 382 #define PPSMC_MSG_PerformBtc                  ((uint16_t) 0x26C)
 383 #define PPSMC_MSG_GetHbmCode                  ((uint16_t) 0x26D)
 384 #define PPSMC_MSG_GetVrVddcTemperature        ((uint16_t) 0x26E)
 385 #define PPSMC_MSG_GetVrMvddTemperature        ((uint16_t) 0x26F)
 386 #define PPSMC_MSG_GetLiquidTemperature        ((uint16_t) 0x270)
 387 #define PPSMC_MSG_GetPlxTemperature           ((uint16_t) 0x271)
 388 #define PPSMC_MSG_RequestI2CControl           ((uint16_t) 0x272)
 389 #define PPSMC_MSG_ReleaseI2CControl           ((uint16_t) 0x273)
 390 #define PPSMC_MSG_LedConfig                   ((uint16_t) 0x274)
 391 #define PPSMC_MSG_SetHbmFanCode               ((uint16_t) 0x275)
 392 #define PPSMC_MSG_SetHbmThrottleCode          ((uint16_t) 0x276)
 393
 394 #define PPSMC_MSG_GetEnabledPsm               ((uint16_t) 0x400)
 395 #define PPSMC_MSG_AgmStartPsm                 ((uint16_t) 0x401)
 396 #define PPSMC_MSG_AgmReadPsm                  ((uint16_t) 0x402)
 397 #define PPSMC_MSG_AgmResetPsm                 ((uint16_t) 0x403)
 398 #define PPSMC_MSG_ReadVftCell                 ((uint16_t) 0x404)
 399
 400 /* AVFS Only - Remove Later */
 401 #define PPSMC_MSG_VftTableIsValid             ((uint16_t) 0x666)
 402
 403 /* If the SMC firmware has an event status soft register this is what the individual bits mean.*/
 404 #define PPSMC_EVENT_STATUS_THERMAL          0x00000001
 405 #define PPSMC_EVENT_STATUS_REGULATORHOT     0x00000002
 406 #define PPSMC_EVENT_STATUS_DC               0x00000004
 407
 408 typedef uint16_t PPSMC_Msg;
 409
 410 #pragma pack(pop)
 411
 412 #endif