drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef _POLARIS10_SMUMANAGER_H
  25 #define _POLARIS10_SMUMANAGER_H
  26
  27
  28 #include <pp_endian.h>
  29 #include "smu74.h"
  30 #include "smu74_discrete.h"
  31 #include "smu7_smumgr.h"
  32
  33 #define SMC_RAM_END 0x40000
  34
  35 struct polaris10_avfs {
  36         enum AVFS_BTC_STATUS avfs_btc_status;
  37         uint32_t           avfs_btc_param;
  38 };
  39
  40 struct polaris10_pt_defaults {
  41         uint8_t   SviLoadLineEn;
  42         uint8_t   SviLoadLineVddC;
  43         uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
  44         uint8_t   TDC_MAWt;
  45         uint8_t   TdcWaterfallCtl;
  46         uint8_t   DTEAmbientTempBase;
  47
  48         uint32_t  DisplayCac;
  49         uint32_t  BAPM_TEMP_GRADIENT;
  50         uint16_t  BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
  51         uint16_t  BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
  52 };
  53
  54
  55
  56 struct polaris10_range_table {
  57         uint32_t trans_lower_frequency; /* in 10khz */
  58         uint32_t trans_upper_frequency;
  59 };
  60
  61 struct polaris10_smumgr {
  62         struct smu7_smumgr smu7_data;
  63         uint8_t protected_mode;
  64         struct polaris10_avfs  avfs;
  65         SMU74_Discrete_DpmTable              smc_state_table;
  66         struct SMU74_Discrete_Ulv            ulv_setting;
  67         struct SMU74_Discrete_PmFuses  power_tune_table;
  68         struct polaris10_range_table                range_table[NUM_SCLK_RANGE];
  69         const struct polaris10_pt_defaults       *power_tune_defaults;
  70         uint32_t                   activity_target[SMU74_MAX_LEVELS_GRAPHICS];
  71         uint32_t                   bif_sclk_table[SMU74_MAX_LEVELS_LINK];
  72 };
  73
  74
  75 #endif