drivers/gpu/drm/arc/arcpgu_crtc.c

   1 /*
   2  * ARC PGU DRM driver.
   3  *
   4  * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_fb_cma_helper.h>
  20 #include <drm/drm_gem_cma_helper.h>
  21 #include <drm/drm_plane_helper.h>
  22 #include <linux/clk.h>
  23 #include <linux/platform_data/simplefb.h>
  24
  25 #include "arcpgu.h"
  26 #include "arcpgu_regs.h"
  27
  28 #define ENCODE_PGU_XY(x, y)     ((((x) - 1) << 16) | ((y) - 1))
  29
  30 static struct simplefb_format supported_formats[] = {
  31         { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
  32         { "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
  33 };
  34
  35 static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
  36 {
  37         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  38         const struct drm_framebuffer *fb = crtc->primary->state->fb;
  39         uint32_t pixel_format = fb->format->format;
  40         struct simplefb_format *format = NULL;
  41         int i;
  42
  43         for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
  44                 if (supported_formats[i].fourcc == pixel_format)
  45                         format = &supported_formats[i];
  46         }
  47
  48         if (WARN_ON(!format))
  49                 return;
  50
  51         if (format->fourcc == DRM_FORMAT_RGB888)
  52                 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
  53                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
  54                                            ARCPGU_MODE_RGB888_MASK);
  55
  56 }
  57
  58 static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
  59         .destroy = drm_crtc_cleanup,
  60         .set_config = drm_atomic_helper_set_config,
  61         .page_flip = drm_atomic_helper_page_flip,
  62         .reset = drm_atomic_helper_crtc_reset,
  63         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  64         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  65 };
  66
  67 static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
  68 {
  69         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  70         struct drm_display_mode *m = &crtc->state->adjusted_mode;
  71         u32 val;
  72
  73         arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
  74                       ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
  75
  76         arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
  77                       ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
  78                                     m->crtc_hsync_end - m->crtc_hdisplay));
  79
  80         arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
  81                       ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
  82                                     m->crtc_vsync_end - m->crtc_vdisplay));
  83
  84         arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
  85                       ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
  86                                     m->crtc_vblank_end - m->crtc_vblank_start));
  87
  88         val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
  89
  90         if (m->flags & DRM_MODE_FLAG_PVSYNC)
  91                 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
  92         else
  93                 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
  94
  95         if (m->flags & DRM_MODE_FLAG_PHSYNC)
  96                 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
  97         else
  98                 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
  99
 100         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
 101         arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
 102         arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
 103
 104         arc_pgu_set_pxl_fmt(crtc);
 105
 106         clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
 107 }
 108
 109 static void arc_pgu_crtc_enable(struct drm_crtc *crtc)
 110 {
 111         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 112
 113         clk_prepare_enable(arcpgu->clk);
 114         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 115                       arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
 116                       ARCPGU_CTRL_ENABLE_MASK);
 117 }
 118
 119 static void arc_pgu_crtc_disable(struct drm_crtc *crtc)
 120 {
 121         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 122
 123         if (!crtc->primary->fb)
 124                 return;
 125
 126         clk_disable_unprepare(arcpgu->clk);
 127         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 128                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
 129                               ~ARCPGU_CTRL_ENABLE_MASK);
 130 }
 131
 132 static int arc_pgu_crtc_atomic_check(struct drm_crtc *crtc,
 133                                      struct drm_crtc_state *state)
 134 {
 135         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 136         struct drm_display_mode *mode = &state->adjusted_mode;
 137         long rate, clk_rate = mode->clock * 1000;
 138
 139         rate = clk_round_rate(arcpgu->clk, clk_rate);
 140         if (rate != clk_rate)
 141                 return -EINVAL;
 142
 143         return 0;
 144 }
 145
 146 static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
 147                                       struct drm_crtc_state *state)
 148 {
 149         struct drm_pending_vblank_event *event = crtc->state->event;
 150
 151         if (event) {
 152                 crtc->state->event = NULL;
 153
 154                 spin_lock_irq(&crtc->dev->event_lock);
 155                 drm_crtc_send_vblank_event(crtc, event);
 156                 spin_unlock_irq(&crtc->dev->event_lock);
 157         }
 158 }
 159
 160 static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
 161         .mode_set       = drm_helper_crtc_mode_set,
 162         .mode_set_base  = drm_helper_crtc_mode_set_base,
 163         .mode_set_nofb  = arc_pgu_crtc_mode_set_nofb,
 164         .enable         = arc_pgu_crtc_enable,
 165         .disable        = arc_pgu_crtc_disable,
 166         .prepare        = arc_pgu_crtc_disable,
 167         .commit         = arc_pgu_crtc_enable,
 168         .atomic_check   = arc_pgu_crtc_atomic_check,
 169         .atomic_begin   = arc_pgu_crtc_atomic_begin,
 170 };
 171
 172 static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
 173                                         struct drm_plane_state *state)
 174 {
 175         struct arcpgu_drm_private *arcpgu;
 176         struct drm_gem_cma_object *gem;
 177
 178         if (!plane->state->crtc || !plane->state->fb)
 179                 return;
 180
 181         arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
 182         gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
 183         arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
 184 }
 185
 186 static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
 187         .atomic_update = arc_pgu_plane_atomic_update,
 188 };
 189
 190 static void arc_pgu_plane_destroy(struct drm_plane *plane)
 191 {
 192         drm_plane_helper_disable(plane);
 193         drm_plane_cleanup(plane);
 194 }
 195
 196 static const struct drm_plane_funcs arc_pgu_plane_funcs = {
 197         .update_plane           = drm_atomic_helper_update_plane,
 198         .disable_plane          = drm_atomic_helper_disable_plane,
 199         .destroy                = arc_pgu_plane_destroy,
 200         .reset                  = drm_atomic_helper_plane_reset,
 201         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 202         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 203 };
 204
 205 static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
 206 {
 207         struct arcpgu_drm_private *arcpgu = drm->dev_private;
 208         struct drm_plane *plane = NULL;
 209         u32 formats[ARRAY_SIZE(supported_formats)], i;
 210         int ret;
 211
 212         plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
 213         if (!plane)
 214                 return ERR_PTR(-ENOMEM);
 215
 216         for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
 217                 formats[i] = supported_formats[i].fourcc;
 218
 219         ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
 220                                        formats, ARRAY_SIZE(formats),
 221                                        DRM_PLANE_TYPE_PRIMARY, NULL);
 222         if (ret)
 223                 return ERR_PTR(ret);
 224
 225         drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
 226         arcpgu->plane = plane;
 227
 228         return plane;
 229 }
 230
 231 int arc_pgu_setup_crtc(struct drm_device *drm)
 232 {
 233         struct arcpgu_drm_private *arcpgu = drm->dev_private;
 234         struct drm_plane *primary;
 235         int ret;
 236
 237         primary = arc_pgu_plane_init(drm);
 238         if (IS_ERR(primary))
 239                 return PTR_ERR(primary);
 240
 241         ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
 242                                         &arc_pgu_crtc_funcs, NULL);
 243         if (ret) {
 244                 arc_pgu_plane_destroy(primary);
 245                 return ret;
 246         }
 247
 248         drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
 249         return 0;
 250 }