2 * Copyright 2012 Red Hat
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License version 2. See the file COPYING in the main
6 * directory of this archive for more details.
8 * Authors: Matthew Garrett
11 #ifndef __CIRRUS_DRV_H__
12 #define __CIRRUS_DRV_H__
14 #include <video/vga.h>
16 #include <drm/drm_encoder.h>
17 #include <drm/drm_fb_helper.h>
19 #include <drm/ttm/ttm_bo_api.h>
20 #include <drm/ttm/ttm_bo_driver.h>
21 #include <drm/ttm/ttm_placement.h>
22 #include <drm/ttm/ttm_memory.h>
23 #include <drm/ttm/ttm_module.h>
25 #include <drm/drm_gem.h>
27 #define DRIVER_AUTHOR "Matthew Garrett"
29 #define DRIVER_NAME "cirrus"
30 #define DRIVER_DESC "qemu Cirrus emulation"
31 #define DRIVER_DATE "20110418"
33 #define DRIVER_MAJOR 1
34 #define DRIVER_MINOR 0
35 #define DRIVER_PATCHLEVEL 0
37 #define CIRRUSFB_CONN_LIMIT 1
39 #define RREG8(reg) ioread8(((void __iomem *)cdev->rmmio) + (reg))
40 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)cdev->rmmio) + (reg))
41 #define RREG32(reg) ioread32(((void __iomem *)cdev->rmmio) + (reg))
42 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)cdev->rmmio) + (reg))
47 #define WREG_SEQ(reg, v) \
49 WREG8(SEQ_INDEX, reg); \
53 #define CRT_INDEX 0x14
56 #define WREG_CRT(reg, v) \
58 WREG8(CRT_INDEX, reg); \
65 #define WREG_GFX(reg, v) \
67 WREG8(GFX_INDEX, reg); \
72 * Cirrus has a "hidden" DAC register that can be accessed by writing to
73 * the pixel mask register to reset the state, then reading from the register
74 * four times. The next write will then pass to the DAC
76 #define VGA_DAC_MASK 0x6
80 RREG8(VGA_DAC_MASK); \
81 RREG8(VGA_DAC_MASK); \
82 RREG8(VGA_DAC_MASK); \
83 RREG8(VGA_DAC_MASK); \
84 WREG8(VGA_DAC_MASK, v); \
88 #define CIRRUS_MAX_FB_HEIGHT 4096
89 #define CIRRUS_MAX_FB_WIDTH 4096
91 #define CIRRUS_DPMS_CLEARED (-1)
93 #define to_cirrus_crtc(x) container_of(x, struct cirrus_crtc, base)
94 #define to_cirrus_encoder(x) container_of(x, struct cirrus_encoder, base)
95 #define to_cirrus_framebuffer(x) container_of(x, struct cirrus_framebuffer, base)
99 u8 lut_r
[256], lut_g
[256], lut_b
[256];
105 struct cirrus_mode_info
{
106 bool mode_config_initialized
;
107 struct cirrus_crtc
*crtc
;
108 /* pointer to fbdev info structure */
109 struct cirrus_fbdev
*gfbdev
;
112 struct cirrus_encoder
{
113 struct drm_encoder base
;
117 struct cirrus_connector
{
118 struct drm_connector base
;
121 struct cirrus_framebuffer
{
122 struct drm_framebuffer base
;
123 struct drm_gem_object
*obj
;
127 resource_size_t vram_size
;
128 resource_size_t vram_base
;
131 struct cirrus_device
{
132 struct drm_device
*dev
;
135 resource_size_t rmmio_base
;
136 resource_size_t rmmio_size
;
140 struct cirrus_mode_info mode_info
;
146 struct drm_global_reference mem_global_ref
;
147 struct ttm_bo_global_ref bo_global_ref
;
148 struct ttm_bo_device bdev
;
154 struct cirrus_fbdev
{
155 struct drm_fb_helper helper
;
156 struct cirrus_framebuffer gfb
;
159 int x1
, y1
, x2
, y2
; /* dirty rect */
160 spinlock_t dirty_lock
;
164 struct ttm_buffer_object bo
;
165 struct ttm_placement placement
;
166 struct ttm_bo_kmap_obj kmap
;
167 struct drm_gem_object gem
;
168 struct ttm_place placements
[3];
171 #define gem_to_cirrus_bo(gobj) container_of((gobj), struct cirrus_bo, gem)
173 static inline struct cirrus_bo
*
174 cirrus_bo(struct ttm_buffer_object
*bo
)
176 return container_of(bo
, struct cirrus_bo
, bo
);
180 #define to_cirrus_obj(x) container_of(x, struct cirrus_gem_object, base)
181 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
184 void cirrus_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
185 u16 blue
, int regno
);
186 void cirrus_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
187 u16
*blue
, int regno
);
191 int cirrus_device_init(struct cirrus_device
*cdev
,
192 struct drm_device
*ddev
,
193 struct pci_dev
*pdev
,
195 void cirrus_device_fini(struct cirrus_device
*cdev
);
196 void cirrus_gem_free_object(struct drm_gem_object
*obj
);
197 int cirrus_dumb_mmap_offset(struct drm_file
*file
,
198 struct drm_device
*dev
,
201 int cirrus_gem_create(struct drm_device
*dev
,
202 u32 size
, bool iskernel
,
203 struct drm_gem_object
**obj
);
204 int cirrus_dumb_create(struct drm_file
*file
,
205 struct drm_device
*dev
,
206 struct drm_mode_create_dumb
*args
);
208 int cirrus_framebuffer_init(struct drm_device
*dev
,
209 struct cirrus_framebuffer
*gfb
,
210 const struct drm_mode_fb_cmd2
*mode_cmd
,
211 struct drm_gem_object
*obj
);
213 bool cirrus_check_framebuffer(struct cirrus_device
*cdev
, int width
, int height
,
216 /* cirrus_display.c */
217 int cirrus_modeset_init(struct cirrus_device
*cdev
);
218 void cirrus_modeset_fini(struct cirrus_device
*cdev
);
221 int cirrus_fbdev_init(struct cirrus_device
*cdev
);
222 void cirrus_fbdev_fini(struct cirrus_device
*cdev
);
227 void cirrus_driver_irq_preinstall(struct drm_device
*dev
);
228 int cirrus_driver_irq_postinstall(struct drm_device
*dev
);
229 void cirrus_driver_irq_uninstall(struct drm_device
*dev
);
230 irqreturn_t
cirrus_driver_irq_handler(int irq
, void *arg
);
233 int cirrus_driver_load(struct drm_device
*dev
, unsigned long flags
);
234 void cirrus_driver_unload(struct drm_device
*dev
);
235 extern struct drm_ioctl_desc cirrus_ioctls
[];
236 extern int cirrus_max_ioctl
;
238 int cirrus_mm_init(struct cirrus_device
*cirrus
);
239 void cirrus_mm_fini(struct cirrus_device
*cirrus
);
240 void cirrus_ttm_placement(struct cirrus_bo
*bo
, int domain
);
241 int cirrus_bo_create(struct drm_device
*dev
, int size
, int align
,
242 uint32_t flags
, struct cirrus_bo
**pcirrusbo
);
243 int cirrus_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
245 static inline int cirrus_bo_reserve(struct cirrus_bo
*bo
, bool no_wait
)
249 ret
= ttm_bo_reserve(&bo
->bo
, true, no_wait
, NULL
);
251 if (ret
!= -ERESTARTSYS
&& ret
!= -EBUSY
)
252 DRM_ERROR("reserve failed %p\n", bo
);
258 static inline void cirrus_bo_unreserve(struct cirrus_bo
*bo
)
260 ttm_bo_unreserve(&bo
->bo
);
263 int cirrus_bo_push_sysram(struct cirrus_bo
*bo
);
264 int cirrus_bo_pin(struct cirrus_bo
*bo
, u32 pl_flag
, u64
*gpu_addr
);
266 extern int cirrus_bpp
;
268 #endif /* __CIRRUS_DRV_H__ */