drm/exynos: Stop using drm_framebuffer_unregister_private
[linux/fpc-iii.git] / drivers / gpu / drm / etnaviv / common.xml.h
blobe881482b5971d16ee2539307f6bf41746fc4dbef
1 #ifndef COMMON_XML
2 #define COMMON_XML
4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
10 The rules-ng-ng source files this header was generated from are:
11 - state_hi.xml ( 24309 bytes, from 2015-12-12 09:02:53)
12 - common.xml ( 18379 bytes, from 2015-12-12 09:02:53)
14 Copyright (C) 2015
18 #define PIPE_ID_PIPE_3D 0x00000000
19 #define PIPE_ID_PIPE_2D 0x00000001
20 #define SYNC_RECIPIENT_FE 0x00000001
21 #define SYNC_RECIPIENT_RA 0x00000005
22 #define SYNC_RECIPIENT_PE 0x00000007
23 #define SYNC_RECIPIENT_DE 0x0000000b
24 #define SYNC_RECIPIENT_VG 0x0000000f
25 #define SYNC_RECIPIENT_TESSELATOR 0x00000010
26 #define SYNC_RECIPIENT_VG2 0x00000011
27 #define SYNC_RECIPIENT_TESSELATOR2 0x00000012
28 #define SYNC_RECIPIENT_VG3 0x00000013
29 #define SYNC_RECIPIENT_TESSELATOR3 0x00000014
30 #define ENDIAN_MODE_NO_SWAP 0x00000000
31 #define ENDIAN_MODE_SWAP_16 0x00000001
32 #define ENDIAN_MODE_SWAP_32 0x00000002
33 #define chipModel_GC200 0x00000200
34 #define chipModel_GC300 0x00000300
35 #define chipModel_GC320 0x00000320
36 #define chipModel_GC328 0x00000328
37 #define chipModel_GC350 0x00000350
38 #define chipModel_GC355 0x00000355
39 #define chipModel_GC400 0x00000400
40 #define chipModel_GC410 0x00000410
41 #define chipModel_GC420 0x00000420
42 #define chipModel_GC428 0x00000428
43 #define chipModel_GC450 0x00000450
44 #define chipModel_GC500 0x00000500
45 #define chipModel_GC520 0x00000520
46 #define chipModel_GC530 0x00000530
47 #define chipModel_GC600 0x00000600
48 #define chipModel_GC700 0x00000700
49 #define chipModel_GC800 0x00000800
50 #define chipModel_GC860 0x00000860
51 #define chipModel_GC880 0x00000880
52 #define chipModel_GC1000 0x00001000
53 #define chipModel_GC1500 0x00001500
54 #define chipModel_GC2000 0x00002000
55 #define chipModel_GC2100 0x00002100
56 #define chipModel_GC2200 0x00002200
57 #define chipModel_GC2500 0x00002500
58 #define chipModel_GC3000 0x00003000
59 #define chipModel_GC4000 0x00004000
60 #define chipModel_GC5000 0x00005000
61 #define chipModel_GC5200 0x00005200
62 #define chipModel_GC6400 0x00006400
63 #define RGBA_BITS_R 0x00000001
64 #define RGBA_BITS_G 0x00000002
65 #define RGBA_BITS_B 0x00000004
66 #define RGBA_BITS_A 0x00000008
67 #define chipFeatures_FAST_CLEAR 0x00000001
68 #define chipFeatures_SPECIAL_ANTI_ALIASING 0x00000002
69 #define chipFeatures_PIPE_3D 0x00000004
70 #define chipFeatures_DXT_TEXTURE_COMPRESSION 0x00000008
71 #define chipFeatures_DEBUG_MODE 0x00000010
72 #define chipFeatures_Z_COMPRESSION 0x00000020
73 #define chipFeatures_YUV420_SCALER 0x00000040
74 #define chipFeatures_MSAA 0x00000080
75 #define chipFeatures_DC 0x00000100
76 #define chipFeatures_PIPE_2D 0x00000200
77 #define chipFeatures_ETC1_TEXTURE_COMPRESSION 0x00000400
78 #define chipFeatures_FAST_SCALER 0x00000800
79 #define chipFeatures_HIGH_DYNAMIC_RANGE 0x00001000
80 #define chipFeatures_YUV420_TILER 0x00002000
81 #define chipFeatures_MODULE_CG 0x00004000
82 #define chipFeatures_MIN_AREA 0x00008000
83 #define chipFeatures_NO_EARLY_Z 0x00010000
84 #define chipFeatures_NO_422_TEXTURE 0x00020000
85 #define chipFeatures_BUFFER_INTERLEAVING 0x00040000
86 #define chipFeatures_BYTE_WRITE_2D 0x00080000
87 #define chipFeatures_NO_SCALER 0x00100000
88 #define chipFeatures_YUY2_AVERAGING 0x00200000
89 #define chipFeatures_HALF_PE_CACHE 0x00400000
90 #define chipFeatures_HALF_TX_CACHE 0x00800000
91 #define chipFeatures_YUY2_RENDER_TARGET 0x01000000
92 #define chipFeatures_MEM32 0x02000000
93 #define chipFeatures_PIPE_VG 0x04000000
94 #define chipFeatures_VGTS 0x08000000
95 #define chipFeatures_FE20 0x10000000
96 #define chipFeatures_BYTE_WRITE_3D 0x20000000
97 #define chipFeatures_RS_YUV_TARGET 0x40000000
98 #define chipFeatures_32_BIT_INDICES 0x80000000
99 #define chipMinorFeatures0_FLIP_Y 0x00000001
100 #define chipMinorFeatures0_DUAL_RETURN_BUS 0x00000002
101 #define chipMinorFeatures0_ENDIANNESS_CONFIG 0x00000004
102 #define chipMinorFeatures0_TEXTURE_8K 0x00000008
103 #define chipMinorFeatures0_CORRECT_TEXTURE_CONVERTER 0x00000010
104 #define chipMinorFeatures0_SPECIAL_MSAA_LOD 0x00000020
105 #define chipMinorFeatures0_FAST_CLEAR_FLUSH 0x00000040
106 #define chipMinorFeatures0_2DPE20 0x00000080
107 #define chipMinorFeatures0_CORRECT_AUTO_DISABLE 0x00000100
108 #define chipMinorFeatures0_RENDERTARGET_8K 0x00000200
109 #define chipMinorFeatures0_2BITPERTILE 0x00000400
110 #define chipMinorFeatures0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED 0x00000800
111 #define chipMinorFeatures0_SUPER_TILED 0x00001000
112 #define chipMinorFeatures0_VG_20 0x00002000
113 #define chipMinorFeatures0_TS_EXTENDED_COMMANDS 0x00004000
114 #define chipMinorFeatures0_COMPRESSION_FIFO_FIXED 0x00008000
115 #define chipMinorFeatures0_HAS_SIGN_FLOOR_CEIL 0x00010000
116 #define chipMinorFeatures0_VG_FILTER 0x00020000
117 #define chipMinorFeatures0_VG_21 0x00040000
118 #define chipMinorFeatures0_SHADER_HAS_W 0x00080000
119 #define chipMinorFeatures0_HAS_SQRT_TRIG 0x00100000
120 #define chipMinorFeatures0_MORE_MINOR_FEATURES 0x00200000
121 #define chipMinorFeatures0_MC20 0x00400000
122 #define chipMinorFeatures0_MSAA_SIDEBAND 0x00800000
123 #define chipMinorFeatures0_BUG_FIXES0 0x01000000
124 #define chipMinorFeatures0_VAA 0x02000000
125 #define chipMinorFeatures0_BYPASS_IN_MSAA 0x04000000
126 #define chipMinorFeatures0_HZ 0x08000000
127 #define chipMinorFeatures0_NEW_TEXTURE 0x10000000
128 #define chipMinorFeatures0_2D_A8_TARGET 0x20000000
129 #define chipMinorFeatures0_CORRECT_STENCIL 0x40000000
130 #define chipMinorFeatures0_ENHANCE_VR 0x80000000
131 #define chipMinorFeatures1_RSUV_SWIZZLE 0x00000001
132 #define chipMinorFeatures1_V2_COMPRESSION 0x00000002
133 #define chipMinorFeatures1_VG_DOUBLE_BUFFER 0x00000004
134 #define chipMinorFeatures1_EXTRA_EVENT_STATES 0x00000008
135 #define chipMinorFeatures1_NO_STRIPING_NEEDED 0x00000010
136 #define chipMinorFeatures1_TEXTURE_STRIDE 0x00000020
137 #define chipMinorFeatures1_BUG_FIXES3 0x00000040
138 #define chipMinorFeatures1_AUTO_DISABLE 0x00000080
139 #define chipMinorFeatures1_AUTO_RESTART_TS 0x00000100
140 #define chipMinorFeatures1_DISABLE_PE_GATING 0x00000200
141 #define chipMinorFeatures1_L2_WINDOWING 0x00000400
142 #define chipMinorFeatures1_HALF_FLOAT 0x00000800
143 #define chipMinorFeatures1_PIXEL_DITHER 0x00001000
144 #define chipMinorFeatures1_TWO_STENCIL_REFERENCE 0x00002000
145 #define chipMinorFeatures1_EXTENDED_PIXEL_FORMAT 0x00004000
146 #define chipMinorFeatures1_CORRECT_MIN_MAX_DEPTH 0x00008000
147 #define chipMinorFeatures1_2D_DITHER 0x00010000
148 #define chipMinorFeatures1_BUG_FIXES5 0x00020000
149 #define chipMinorFeatures1_NEW_2D 0x00040000
150 #define chipMinorFeatures1_NEW_FP 0x00080000
151 #define chipMinorFeatures1_TEXTURE_HALIGN 0x00100000
152 #define chipMinorFeatures1_NON_POWER_OF_TWO 0x00200000
153 #define chipMinorFeatures1_LINEAR_TEXTURE_SUPPORT 0x00400000
154 #define chipMinorFeatures1_HALTI0 0x00800000
155 #define chipMinorFeatures1_CORRECT_OVERFLOW_VG 0x01000000
156 #define chipMinorFeatures1_NEGATIVE_LOG_FIX 0x02000000
157 #define chipMinorFeatures1_RESOLVE_OFFSET 0x04000000
158 #define chipMinorFeatures1_OK_TO_GATE_AXI_CLOCK 0x08000000
159 #define chipMinorFeatures1_MMU_VERSION 0x10000000
160 #define chipMinorFeatures1_WIDE_LINE 0x20000000
161 #define chipMinorFeatures1_BUG_FIXES6 0x40000000
162 #define chipMinorFeatures1_FC_FLUSH_STALL 0x80000000
163 #define chipMinorFeatures2_LINE_LOOP 0x00000001
164 #define chipMinorFeatures2_LOGIC_OP 0x00000002
165 #define chipMinorFeatures2_UNK2 0x00000004
166 #define chipMinorFeatures2_SUPERTILED_TEXTURE 0x00000008
167 #define chipMinorFeatures2_UNK4 0x00000010
168 #define chipMinorFeatures2_RECT_PRIMITIVE 0x00000020
169 #define chipMinorFeatures2_COMPOSITION 0x00000040
170 #define chipMinorFeatures2_CORRECT_AUTO_DISABLE_COUNT 0x00000080
171 #define chipMinorFeatures2_UNK8 0x00000100
172 #define chipMinorFeatures2_UNK9 0x00000200
173 #define chipMinorFeatures2_UNK10 0x00000400
174 #define chipMinorFeatures2_HALTI1 0x00000800
175 #define chipMinorFeatures2_UNK12 0x00001000
176 #define chipMinorFeatures2_UNK13 0x00002000
177 #define chipMinorFeatures2_UNK14 0x00004000
178 #define chipMinorFeatures2_EXTRA_TEXTURE_STATE 0x00008000
179 #define chipMinorFeatures2_FULL_DIRECTFB 0x00010000
180 #define chipMinorFeatures2_2D_TILING 0x00020000
181 #define chipMinorFeatures2_THREAD_WALKER_IN_PS 0x00040000
182 #define chipMinorFeatures2_TILE_FILLER 0x00080000
183 #define chipMinorFeatures2_UNK20 0x00100000
184 #define chipMinorFeatures2_2D_MULTI_SOURCE_BLIT 0x00200000
185 #define chipMinorFeatures2_UNK22 0x00400000
186 #define chipMinorFeatures2_UNK23 0x00800000
187 #define chipMinorFeatures2_UNK24 0x01000000
188 #define chipMinorFeatures2_MIXED_STREAMS 0x02000000
189 #define chipMinorFeatures2_2D_420_L2CACHE 0x04000000
190 #define chipMinorFeatures2_UNK27 0x08000000
191 #define chipMinorFeatures2_2D_NO_INDEX8_BRUSH 0x10000000
192 #define chipMinorFeatures2_TEXTURE_TILED_READ 0x20000000
193 #define chipMinorFeatures2_UNK30 0x40000000
194 #define chipMinorFeatures2_UNK31 0x80000000
195 #define chipMinorFeatures3_ROTATION_STALL_FIX 0x00000001
196 #define chipMinorFeatures3_UNK1 0x00000002
197 #define chipMinorFeatures3_2D_MULTI_SOURCE_BLT_EX 0x00000004
198 #define chipMinorFeatures3_UNK3 0x00000008
199 #define chipMinorFeatures3_UNK4 0x00000010
200 #define chipMinorFeatures3_UNK5 0x00000020
201 #define chipMinorFeatures3_UNK6 0x00000040
202 #define chipMinorFeatures3_UNK7 0x00000080
203 #define chipMinorFeatures3_FAST_MSAA 0x00000100
204 #define chipMinorFeatures3_UNK9 0x00000200
205 #define chipMinorFeatures3_BUG_FIXES10 0x00000400
206 #define chipMinorFeatures3_UNK11 0x00000800
207 #define chipMinorFeatures3_BUG_FIXES11 0x00001000
208 #define chipMinorFeatures3_UNK13 0x00002000
209 #define chipMinorFeatures3_UNK14 0x00004000
210 #define chipMinorFeatures3_UNK15 0x00008000
211 #define chipMinorFeatures3_UNK16 0x00010000
212 #define chipMinorFeatures3_UNK17 0x00020000
213 #define chipMinorFeatures3_ACE 0x00040000
214 #define chipMinorFeatures3_UNK19 0x00080000
215 #define chipMinorFeatures3_UNK20 0x00100000
216 #define chipMinorFeatures3_UNK21 0x00200000
217 #define chipMinorFeatures3_UNK22 0x00400000
218 #define chipMinorFeatures3_UNK23 0x00800000
219 #define chipMinorFeatures3_UNK24 0x01000000
220 #define chipMinorFeatures3_UNK25 0x02000000
221 #define chipMinorFeatures3_NEW_HZ 0x04000000
222 #define chipMinorFeatures3_UNK27 0x08000000
223 #define chipMinorFeatures3_UNK28 0x10000000
224 #define chipMinorFeatures3_UNK29 0x20000000
225 #define chipMinorFeatures3_UNK30 0x40000000
226 #define chipMinorFeatures3_UNK31 0x80000000
227 #define chipMinorFeatures4_UNK0 0x00000001
228 #define chipMinorFeatures4_UNK1 0x00000002
229 #define chipMinorFeatures4_UNK2 0x00000004
230 #define chipMinorFeatures4_UNK3 0x00000008
231 #define chipMinorFeatures4_UNK4 0x00000010
232 #define chipMinorFeatures4_UNK5 0x00000020
233 #define chipMinorFeatures4_UNK6 0x00000040
234 #define chipMinorFeatures4_UNK7 0x00000080
235 #define chipMinorFeatures4_UNK8 0x00000100
236 #define chipMinorFeatures4_UNK9 0x00000200
237 #define chipMinorFeatures4_UNK10 0x00000400
238 #define chipMinorFeatures4_UNK11 0x00000800
239 #define chipMinorFeatures4_UNK12 0x00001000
240 #define chipMinorFeatures4_UNK13 0x00002000
241 #define chipMinorFeatures4_UNK14 0x00004000
242 #define chipMinorFeatures4_UNK15 0x00008000
243 #define chipMinorFeatures4_HALTI2 0x00010000
244 #define chipMinorFeatures4_UNK17 0x00020000
245 #define chipMinorFeatures4_SMALL_MSAA 0x00040000
246 #define chipMinorFeatures4_UNK19 0x00080000
247 #define chipMinorFeatures4_UNK20 0x00100000
248 #define chipMinorFeatures4_UNK21 0x00200000
249 #define chipMinorFeatures4_UNK22 0x00400000
250 #define chipMinorFeatures4_UNK23 0x00800000
251 #define chipMinorFeatures4_UNK24 0x01000000
252 #define chipMinorFeatures4_UNK25 0x02000000
253 #define chipMinorFeatures4_UNK26 0x04000000
254 #define chipMinorFeatures4_UNK27 0x08000000
255 #define chipMinorFeatures4_UNK28 0x10000000
256 #define chipMinorFeatures4_UNK29 0x20000000
257 #define chipMinorFeatures4_UNK30 0x40000000
258 #define chipMinorFeatures4_UNK31 0x80000000
259 #define chipMinorFeatures5_UNK0 0x00000001
260 #define chipMinorFeatures5_UNK1 0x00000002
261 #define chipMinorFeatures5_UNK2 0x00000004
262 #define chipMinorFeatures5_UNK3 0x00000008
263 #define chipMinorFeatures5_UNK4 0x00000010
264 #define chipMinorFeatures5_UNK5 0x00000020
265 #define chipMinorFeatures5_UNK6 0x00000040
266 #define chipMinorFeatures5_UNK7 0x00000080
267 #define chipMinorFeatures5_UNK8 0x00000100
268 #define chipMinorFeatures5_HALTI3 0x00000200
269 #define chipMinorFeatures5_UNK10 0x00000400
270 #define chipMinorFeatures5_UNK11 0x00000800
271 #define chipMinorFeatures5_UNK12 0x00001000
272 #define chipMinorFeatures5_UNK13 0x00002000
273 #define chipMinorFeatures5_UNK14 0x00004000
274 #define chipMinorFeatures5_UNK15 0x00008000
275 #define chipMinorFeatures5_UNK16 0x00010000
276 #define chipMinorFeatures5_UNK17 0x00020000
277 #define chipMinorFeatures5_UNK18 0x00040000
278 #define chipMinorFeatures5_UNK19 0x00080000
279 #define chipMinorFeatures5_UNK20 0x00100000
280 #define chipMinorFeatures5_UNK21 0x00200000
281 #define chipMinorFeatures5_UNK22 0x00400000
282 #define chipMinorFeatures5_UNK23 0x00800000
283 #define chipMinorFeatures5_UNK24 0x01000000
284 #define chipMinorFeatures5_UNK25 0x02000000
285 #define chipMinorFeatures5_UNK26 0x04000000
286 #define chipMinorFeatures5_UNK27 0x08000000
287 #define chipMinorFeatures5_UNK28 0x10000000
288 #define chipMinorFeatures5_UNK29 0x20000000
289 #define chipMinorFeatures5_UNK30 0x40000000
290 #define chipMinorFeatures5_UNK31 0x80000000
292 #endif /* COMMON_XML */