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drm/exynos: Stop using drm_framebuffer_unregister_private
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
blobc66e90571031de456df9303818f10fcbf3e210c9
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/uaccess.h>
32
33 #include <drm/drmP.h>
34 #include <drm/i915_drm.h>
35
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39 #include "intel_frontbuffer.h"
40
41 #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */
42
43 #define __EXEC_OBJECT_HAS_PIN (1<<31)
44 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
45 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
46 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
47 #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */
48
49 #define BATCH_OFFSET_BIAS (256*1024)
50
51 struct i915_execbuffer_params {
52 struct drm_device *dev;
53 struct drm_file *file;
54 struct i915_vma *batch;
55 u32 dispatch_flags;
56 u32 args_batch_start_offset;
57 struct intel_engine_cs *engine;
58 struct i915_gem_context *ctx;
59 struct drm_i915_gem_request *request;
60 };
61
62 struct eb_vmas {
63 struct drm_i915_private *i915;
64 struct list_head vmas;
65 int and;
66 union {
67 struct i915_vma *lut[0];
68 struct hlist_head buckets[0];
69 };
70 };
71
72 static struct eb_vmas *
73 eb_create(struct drm_i915_private *i915,
74 struct drm_i915_gem_execbuffer2 *args)
75 {
76 struct eb_vmas *eb = NULL;
77
78 if (args->flags & I915_EXEC_HANDLE_LUT) {
79 unsigned size = args->buffer_count;
80 size *= sizeof(struct i915_vma *);
81 size += sizeof(struct eb_vmas);
82 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
83 }
84
85 if (eb == NULL) {
86 unsigned size = args->buffer_count;
87 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
88 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
89 while (count > 2*size)
90 count >>= 1;
91 eb = kzalloc(count*sizeof(struct hlist_head) +
92 sizeof(struct eb_vmas),
93 GFP_TEMPORARY);
94 if (eb == NULL)
95 return eb;
96
97 eb->and = count - 1;
98 } else
99 eb->and = -args->buffer_count;
100
101 eb->i915 = i915;
102 INIT_LIST_HEAD(&eb->vmas);
103 return eb;
104 }
105
106 static void
107 eb_reset(struct eb_vmas *eb)
108 {
109 if (eb->and >= 0)
110 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
111 }
112
113 static struct i915_vma *
114 eb_get_batch(struct eb_vmas *eb)
115 {
116 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
117
118 /*
119 * SNA is doing fancy tricks with compressing batch buffers, which leads
120 * to negative relocation deltas. Usually that works out ok since the
121 * relocate address is still positive, except when the batch is placed
122 * very low in the GTT. Ensure this doesn't happen.
123 *
124 * Note that actual hangs have only been observed on gen7, but for
125 * paranoia do it everywhere.
126 */
127 if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
128 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
129
130 return vma;
131 }
132
133 static int
134 eb_lookup_vmas(struct eb_vmas *eb,
135 struct drm_i915_gem_exec_object2 *exec,
136 const struct drm_i915_gem_execbuffer2 *args,
137 struct i915_address_space *vm,
138 struct drm_file *file)
139 {
140 struct drm_i915_gem_object *obj;
141 struct list_head objects;
142 int i, ret;
143
144 INIT_LIST_HEAD(&objects);
145 spin_lock(&file->table_lock);
146 /* Grab a reference to the object and release the lock so we can lookup
147 * or create the VMA without using GFP_ATOMIC */
148 for (i = 0; i < args->buffer_count; i++) {
149 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
150 if (obj == NULL) {
151 spin_unlock(&file->table_lock);
152 DRM_DEBUG("Invalid object handle %d at index %d\n",
153 exec[i].handle, i);
154 ret = -ENOENT;
155 goto err;
156 }
157
158 if (!list_empty(&obj->obj_exec_link)) {
159 spin_unlock(&file->table_lock);
160 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
161 obj, exec[i].handle, i);
162 ret = -EINVAL;
163 goto err;
164 }
165
166 i915_gem_object_get(obj);
167 list_add_tail(&obj->obj_exec_link, &objects);
168 }
169 spin_unlock(&file->table_lock);
170
171 i = 0;
172 while (!list_empty(&objects)) {
173 struct i915_vma *vma;
174
175 obj = list_first_entry(&objects,
176 struct drm_i915_gem_object,
177 obj_exec_link);
178
179 /*
180 * NOTE: We can leak any vmas created here when something fails
181 * later on. But that's no issue since vma_unbind can deal with
182 * vmas which are not actually bound. And since only
183 * lookup_or_create exists as an interface to get at the vma
184 * from the (obj, vm) we don't run the risk of creating
185 * duplicated vmas for the same vm.
186 */
187 vma = i915_vma_instance(obj, vm, NULL);
188 if (unlikely(IS_ERR(vma))) {
189 DRM_DEBUG("Failed to lookup VMA\n");
190 ret = PTR_ERR(vma);
191 goto err;
192 }
193
194 /* Transfer ownership from the objects list to the vmas list. */
195 list_add_tail(&vma->exec_list, &eb->vmas);
196 list_del_init(&obj->obj_exec_link);
197
198 vma->exec_entry = &exec[i];
199 if (eb->and < 0) {
200 eb->lut[i] = vma;
201 } else {
202 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
203 vma->exec_handle = handle;
204 hlist_add_head(&vma->exec_node,
205 &eb->buckets[handle & eb->and]);
206 }
207 ++i;
208 }
209
210 return 0;
211
212
213 err:
214 while (!list_empty(&objects)) {
215 obj = list_first_entry(&objects,
216 struct drm_i915_gem_object,
217 obj_exec_link);
218 list_del_init(&obj->obj_exec_link);
219 i915_gem_object_put(obj);
220 }
221 /*
222 * Objects already transfered to the vmas list will be unreferenced by
223 * eb_destroy.
224 */
225
226 return ret;
227 }
228
229 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
230 {
231 if (eb->and < 0) {
232 if (handle >= -eb->and)
233 return NULL;
234 return eb->lut[handle];
235 } else {
236 struct hlist_head *head;
237 struct i915_vma *vma;
238
239 head = &eb->buckets[handle & eb->and];
240 hlist_for_each_entry(vma, head, exec_node) {
241 if (vma->exec_handle == handle)
242 return vma;
243 }
244 return NULL;
245 }
246 }
247
248 static void
249 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
250 {
251 struct drm_i915_gem_exec_object2 *entry;
252
253 if (!drm_mm_node_allocated(&vma->node))
254 return;
255
256 entry = vma->exec_entry;
257
258 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
259 i915_vma_unpin_fence(vma);
260
261 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
262 __i915_vma_unpin(vma);
263
264 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
265 }
266
267 static void eb_destroy(struct eb_vmas *eb)
268 {
269 while (!list_empty(&eb->vmas)) {
270 struct i915_vma *vma;
271
272 vma = list_first_entry(&eb->vmas,
273 struct i915_vma,
274 exec_list);
275 list_del_init(&vma->exec_list);
276 i915_gem_execbuffer_unreserve_vma(vma);
277 vma->exec_entry = NULL;
278 i915_vma_put(vma);
279 }
280 kfree(eb);
281 }
282
283 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
284 {
285 if (!i915_gem_object_has_struct_page(obj))
286 return false;
287
288 if (DBG_USE_CPU_RELOC)
289 return DBG_USE_CPU_RELOC > 0;
290
291 return (HAS_LLC(to_i915(obj->base.dev)) ||
292 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
293 obj->cache_level != I915_CACHE_NONE);
294 }
295
296 /* Used to convert any address to canonical form.
297 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
298 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
299 * addresses to be in a canonical form:
300 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
301 * canonical form [63:48] == [47]."
302 */
303 #define GEN8_HIGH_ADDRESS_BIT 47
304 static inline uint64_t gen8_canonical_addr(uint64_t address)
305 {
306 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
307 }
308
309 static inline uint64_t gen8_noncanonical_addr(uint64_t address)
310 {
311 return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
312 }
313
314 static inline uint64_t
315 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
316 uint64_t target_offset)
317 {
318 return gen8_canonical_addr((int)reloc->delta + target_offset);
319 }
320
321 struct reloc_cache {
322 struct drm_i915_private *i915;
323 struct drm_mm_node node;
324 unsigned long vaddr;
325 unsigned int page;
326 bool use_64bit_reloc;
327 };
328
329 static void reloc_cache_init(struct reloc_cache *cache,
330 struct drm_i915_private *i915)
331 {
332 cache->page = -1;
333 cache->vaddr = 0;
334 cache->i915 = i915;
335 /* Must be a variable in the struct to allow GCC to unroll. */
336 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
337 cache->node.allocated = false;
338 }
339
340 static inline void *unmask_page(unsigned long p)
341 {
342 return (void *)(uintptr_t)(p & PAGE_MASK);
343 }
344
345 static inline unsigned int unmask_flags(unsigned long p)
346 {
347 return p & ~PAGE_MASK;
348 }
349
350 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
351
352 static void reloc_cache_fini(struct reloc_cache *cache)
353 {
354 void *vaddr;
355
356 if (!cache->vaddr)
357 return;
358
359 vaddr = unmask_page(cache->vaddr);
360 if (cache->vaddr & KMAP) {
361 if (cache->vaddr & CLFLUSH_AFTER)
362 mb();
363
364 kunmap_atomic(vaddr);
365 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
366 } else {
367 wmb();
368 io_mapping_unmap_atomic((void __iomem *)vaddr);
369 if (cache->node.allocated) {
370 struct i915_ggtt *ggtt = &cache->i915->ggtt;
371
372 ggtt->base.clear_range(&ggtt->base,
373 cache->node.start,
374 cache->node.size);
375 drm_mm_remove_node(&cache->node);
376 } else {
377 i915_vma_unpin((struct i915_vma *)cache->node.mm);
378 }
379 }
380 }
381
382 static void *reloc_kmap(struct drm_i915_gem_object *obj,
383 struct reloc_cache *cache,
384 int page)
385 {
386 void *vaddr;
387
388 if (cache->vaddr) {
389 kunmap_atomic(unmask_page(cache->vaddr));
390 } else {
391 unsigned int flushes;
392 int ret;
393
394 ret = i915_gem_obj_prepare_shmem_write(obj, &flushes);
395 if (ret)
396 return ERR_PTR(ret);
397
398 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
399 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
400
401 cache->vaddr = flushes | KMAP;
402 cache->node.mm = (void *)obj;
403 if (flushes)
404 mb();
405 }
406
407 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
408 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
409 cache->page = page;
410
411 return vaddr;
412 }
413
414 static void *reloc_iomap(struct drm_i915_gem_object *obj,
415 struct reloc_cache *cache,
416 int page)
417 {
418 struct i915_ggtt *ggtt = &cache->i915->ggtt;
419 unsigned long offset;
420 void *vaddr;
421
422 if (cache->vaddr) {
423 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
424 } else {
425 struct i915_vma *vma;
426 int ret;
427
428 if (use_cpu_reloc(obj))
429 return NULL;
430
431 ret = i915_gem_object_set_to_gtt_domain(obj, true);
432 if (ret)
433 return ERR_PTR(ret);
434
435 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
436 PIN_MAPPABLE | PIN_NONBLOCK);
437 if (IS_ERR(vma)) {
438 memset(&cache->node, 0, sizeof(cache->node));
439 ret = drm_mm_insert_node_in_range_generic
440 (&ggtt->base.mm, &cache->node,
441 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
442 0, ggtt->mappable_end,
443 DRM_MM_SEARCH_DEFAULT,
444 DRM_MM_CREATE_DEFAULT);
445 if (ret) /* no inactive aperture space, use cpu reloc */
446 return NULL;
447 } else {
448 ret = i915_vma_put_fence(vma);
449 if (ret) {
450 i915_vma_unpin(vma);
451 return ERR_PTR(ret);
452 }
453
454 cache->node.start = vma->node.start;
455 cache->node.mm = (void *)vma;
456 }
457 }
458
459 offset = cache->node.start;
460 if (cache->node.allocated) {
461 wmb();
462 ggtt->base.insert_page(&ggtt->base,
463 i915_gem_object_get_dma_address(obj, page),
464 offset, I915_CACHE_NONE, 0);
465 } else {
466 offset += page << PAGE_SHIFT;
467 }
468
469 vaddr = (void __force *) io_mapping_map_atomic_wc(&cache->i915->ggtt.mappable, offset);
470 cache->page = page;
471 cache->vaddr = (unsigned long)vaddr;
472
473 return vaddr;
474 }
475
476 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
477 struct reloc_cache *cache,
478 int page)
479 {
480 void *vaddr;
481
482 if (cache->page == page) {
483 vaddr = unmask_page(cache->vaddr);
484 } else {
485 vaddr = NULL;
486 if ((cache->vaddr & KMAP) == 0)
487 vaddr = reloc_iomap(obj, cache, page);
488 if (!vaddr)
489 vaddr = reloc_kmap(obj, cache, page);
490 }
491
492 return vaddr;
493 }
494
495 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
496 {
497 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
498 if (flushes & CLFLUSH_BEFORE) {
499 clflushopt(addr);
500 mb();
501 }
502
503 *addr = value;
504
505 /* Writes to the same cacheline are serialised by the CPU
506 * (including clflush). On the write path, we only require
507 * that it hits memory in an orderly fashion and place
508 * mb barriers at the start and end of the relocation phase
509 * to ensure ordering of clflush wrt to the system.
510 */
511 if (flushes & CLFLUSH_AFTER)
512 clflushopt(addr);
513 } else
514 *addr = value;
515 }
516
517 static int
518 relocate_entry(struct drm_i915_gem_object *obj,
519 const struct drm_i915_gem_relocation_entry *reloc,
520 struct reloc_cache *cache,
521 u64 target_offset)
522 {
523 u64 offset = reloc->offset;
524 bool wide = cache->use_64bit_reloc;
525 void *vaddr;
526
527 target_offset = relocation_target(reloc, target_offset);
528 repeat:
529 vaddr = reloc_vaddr(obj, cache, offset >> PAGE_SHIFT);
530 if (IS_ERR(vaddr))
531 return PTR_ERR(vaddr);
532
533 clflush_write32(vaddr + offset_in_page(offset),
534 lower_32_bits(target_offset),
535 cache->vaddr);
536
537 if (wide) {
538 offset += sizeof(u32);
539 target_offset >>= 32;
540 wide = false;
541 goto repeat;
542 }
543
544 return 0;
545 }
546
547 static int
548 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
549 struct eb_vmas *eb,
550 struct drm_i915_gem_relocation_entry *reloc,
551 struct reloc_cache *cache)
552 {
553 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
554 struct drm_gem_object *target_obj;
555 struct drm_i915_gem_object *target_i915_obj;
556 struct i915_vma *target_vma;
557 uint64_t target_offset;
558 int ret;
559
560 /* we've already hold a reference to all valid objects */
561 target_vma = eb_get_vma(eb, reloc->target_handle);
562 if (unlikely(target_vma == NULL))
563 return -ENOENT;
564 target_i915_obj = target_vma->obj;
565 target_obj = &target_vma->obj->base;
566
567 target_offset = gen8_canonical_addr(target_vma->node.start);
568
569 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
570 * pipe_control writes because the gpu doesn't properly redirect them
571 * through the ppgtt for non_secure batchbuffers. */
572 if (unlikely(IS_GEN6(dev_priv) &&
573 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
574 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
575 PIN_GLOBAL);
576 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
577 return ret;
578 }
579
580 /* Validate that the target is in a valid r/w GPU domain */
581 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
582 DRM_DEBUG("reloc with multiple write domains: "
583 "obj %p target %d offset %d "
584 "read %08x write %08x",
585 obj, reloc->target_handle,
586 (int) reloc->offset,
587 reloc->read_domains,
588 reloc->write_domain);
589 return -EINVAL;
590 }
591 if (unlikely((reloc->write_domain | reloc->read_domains)
592 & ~I915_GEM_GPU_DOMAINS)) {
593 DRM_DEBUG("reloc with read/write non-GPU domains: "
594 "obj %p target %d offset %d "
595 "read %08x write %08x",
596 obj, reloc->target_handle,
597 (int) reloc->offset,
598 reloc->read_domains,
599 reloc->write_domain);
600 return -EINVAL;
601 }
602
603 target_obj->pending_read_domains |= reloc->read_domains;
604 target_obj->pending_write_domain |= reloc->write_domain;
605
606 /* If the relocation already has the right value in it, no
607 * more work needs to be done.
608 */
609 if (target_offset == reloc->presumed_offset)
610 return 0;
611
612 /* Check that the relocation address is valid... */
613 if (unlikely(reloc->offset >
614 obj->base.size - (cache->use_64bit_reloc ? 8 : 4))) {
615 DRM_DEBUG("Relocation beyond object bounds: "
616 "obj %p target %d offset %d size %d.\n",
617 obj, reloc->target_handle,
618 (int) reloc->offset,
619 (int) obj->base.size);
620 return -EINVAL;
621 }
622 if (unlikely(reloc->offset & 3)) {
623 DRM_DEBUG("Relocation not 4-byte aligned: "
624 "obj %p target %d offset %d.\n",
625 obj, reloc->target_handle,
626 (int) reloc->offset);
627 return -EINVAL;
628 }
629
630 ret = relocate_entry(obj, reloc, cache, target_offset);
631 if (ret)
632 return ret;
633
634 /* and update the user's relocation entry */
635 reloc->presumed_offset = target_offset;
636 return 0;
637 }
638
639 static int
640 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
641 struct eb_vmas *eb)
642 {
643 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
644 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
645 struct drm_i915_gem_relocation_entry __user *user_relocs;
646 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
647 struct reloc_cache cache;
648 int remain, ret = 0;
649
650 user_relocs = u64_to_user_ptr(entry->relocs_ptr);
651 reloc_cache_init(&cache, eb->i915);
652
653 remain = entry->relocation_count;
654 while (remain) {
655 struct drm_i915_gem_relocation_entry *r = stack_reloc;
656 unsigned long unwritten;
657 unsigned int count;
658
659 count = min_t(unsigned int, remain, ARRAY_SIZE(stack_reloc));
660 remain -= count;
661
662 /* This is the fast path and we cannot handle a pagefault
663 * whilst holding the struct mutex lest the user pass in the
664 * relocations contained within a mmaped bo. For in such a case
665 * we, the page fault handler would call i915_gem_fault() and
666 * we would try to acquire the struct mutex again. Obviously
667 * this is bad and so lockdep complains vehemently.
668 */
669 pagefault_disable();
670 unwritten = __copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]));
671 pagefault_enable();
672 if (unlikely(unwritten)) {
673 ret = -EFAULT;
674 goto out;
675 }
676
677 do {
678 u64 offset = r->presumed_offset;
679
680 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r, &cache);
681 if (ret)
682 goto out;
683
684 if (r->presumed_offset != offset) {
685 pagefault_disable();
686 unwritten = __put_user(r->presumed_offset,
687 &user_relocs->presumed_offset);
688 pagefault_enable();
689 if (unlikely(unwritten)) {
690 /* Note that reporting an error now
691 * leaves everything in an inconsistent
692 * state as we have *already* changed
693 * the relocation value inside the
694 * object. As we have not changed the
695 * reloc.presumed_offset or will not
696 * change the execobject.offset, on the
697 * call we may not rewrite the value
698 * inside the object, leaving it
699 * dangling and causing a GPU hang.
700 */
701 ret = -EFAULT;
702 goto out;
703 }
704 }
705
706 user_relocs++;
707 r++;
708 } while (--count);
709 }
710
711 out:
712 reloc_cache_fini(&cache);
713 return ret;
714 #undef N_RELOC
715 }
716
717 static int
718 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
719 struct eb_vmas *eb,
720 struct drm_i915_gem_relocation_entry *relocs)
721 {
722 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
723 struct reloc_cache cache;
724 int i, ret = 0;
725
726 reloc_cache_init(&cache, eb->i915);
727 for (i = 0; i < entry->relocation_count; i++) {
728 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i], &cache);
729 if (ret)
730 break;
731 }
732 reloc_cache_fini(&cache);
733
734 return ret;
735 }
736
737 static int
738 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
739 {
740 struct i915_vma *vma;
741 int ret = 0;
742
743 list_for_each_entry(vma, &eb->vmas, exec_list) {
744 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
745 if (ret)
746 break;
747 }
748
749 return ret;
750 }
751
752 static bool only_mappable_for_reloc(unsigned int flags)
753 {
754 return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
755 __EXEC_OBJECT_NEEDS_MAP;
756 }
757
758 static int
759 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
760 struct intel_engine_cs *engine,
761 bool *need_reloc)
762 {
763 struct drm_i915_gem_object *obj = vma->obj;
764 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
765 uint64_t flags;
766 int ret;
767
768 flags = PIN_USER;
769 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
770 flags |= PIN_GLOBAL;
771
772 if (!drm_mm_node_allocated(&vma->node)) {
773 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
774 * limit address to the first 4GBs for unflagged objects.
775 */
776 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
777 flags |= PIN_ZONE_4G;
778 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
779 flags |= PIN_GLOBAL | PIN_MAPPABLE;
780 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
781 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
782 if (entry->flags & EXEC_OBJECT_PINNED)
783 flags |= entry->offset | PIN_OFFSET_FIXED;
784 if ((flags & PIN_MAPPABLE) == 0)
785 flags |= PIN_HIGH;
786 }
787
788 ret = i915_vma_pin(vma,
789 entry->pad_to_size,
790 entry->alignment,
791 flags);
792 if ((ret == -ENOSPC || ret == -E2BIG) &&
793 only_mappable_for_reloc(entry->flags))
794 ret = i915_vma_pin(vma,
795 entry->pad_to_size,
796 entry->alignment,
797 flags & ~PIN_MAPPABLE);
798 if (ret)
799 return ret;
800
801 entry->flags |= __EXEC_OBJECT_HAS_PIN;
802
803 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
804 ret = i915_vma_get_fence(vma);
805 if (ret)
806 return ret;
807
808 if (i915_vma_pin_fence(vma))
809 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
810 }
811
812 if (entry->offset != vma->node.start) {
813 entry->offset = vma->node.start;
814 *need_reloc = true;
815 }
816
817 if (entry->flags & EXEC_OBJECT_WRITE) {
818 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
819 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
820 }
821
822 return 0;
823 }
824
825 static bool
826 need_reloc_mappable(struct i915_vma *vma)
827 {
828 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
829
830 if (entry->relocation_count == 0)
831 return false;
832
833 if (!i915_vma_is_ggtt(vma))
834 return false;
835
836 /* See also use_cpu_reloc() */
837 if (HAS_LLC(to_i915(vma->obj->base.dev)))
838 return false;
839
840 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
841 return false;
842
843 return true;
844 }
845
846 static bool
847 eb_vma_misplaced(struct i915_vma *vma)
848 {
849 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
850
851 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
852 !i915_vma_is_ggtt(vma));
853
854 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
855 return true;
856
857 if (vma->node.size < entry->pad_to_size)
858 return true;
859
860 if (entry->flags & EXEC_OBJECT_PINNED &&
861 vma->node.start != entry->offset)
862 return true;
863
864 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
865 vma->node.start < BATCH_OFFSET_BIAS)
866 return true;
867
868 /* avoid costly ping-pong once a batch bo ended up non-mappable */
869 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
870 !i915_vma_is_map_and_fenceable(vma))
871 return !only_mappable_for_reloc(entry->flags);
872
873 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
874 (vma->node.start + vma->node.size - 1) >> 32)
875 return true;
876
877 return false;
878 }
879
880 static int
881 i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
882 struct list_head *vmas,
883 struct i915_gem_context *ctx,
884 bool *need_relocs)
885 {
886 struct drm_i915_gem_object *obj;
887 struct i915_vma *vma;
888 struct i915_address_space *vm;
889 struct list_head ordered_vmas;
890 struct list_head pinned_vmas;
891 bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
892 int retry;
893
894 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
895
896 INIT_LIST_HEAD(&ordered_vmas);
897 INIT_LIST_HEAD(&pinned_vmas);
898 while (!list_empty(vmas)) {
899 struct drm_i915_gem_exec_object2 *entry;
900 bool need_fence, need_mappable;
901
902 vma = list_first_entry(vmas, struct i915_vma, exec_list);
903 obj = vma->obj;
904 entry = vma->exec_entry;
905
906 if (ctx->flags & CONTEXT_NO_ZEROMAP)
907 entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
908
909 if (!has_fenced_gpu_access)
910 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
911 need_fence =
912 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
913 i915_gem_object_is_tiled(obj);
914 need_mappable = need_fence || need_reloc_mappable(vma);
915
916 if (entry->flags & EXEC_OBJECT_PINNED)
917 list_move_tail(&vma->exec_list, &pinned_vmas);
918 else if (need_mappable) {
919 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
920 list_move(&vma->exec_list, &ordered_vmas);
921 } else
922 list_move_tail(&vma->exec_list, &ordered_vmas);
923
924 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
925 obj->base.pending_write_domain = 0;
926 }
927 list_splice(&ordered_vmas, vmas);
928 list_splice(&pinned_vmas, vmas);
929
930 /* Attempt to pin all of the buffers into the GTT.
931 * This is done in 3 phases:
932 *
933 * 1a. Unbind all objects that do not match the GTT constraints for
934 * the execbuffer (fenceable, mappable, alignment etc).
935 * 1b. Increment pin count for already bound objects.
936 * 2. Bind new objects.
937 * 3. Decrement pin count.
938 *
939 * This avoid unnecessary unbinding of later objects in order to make
940 * room for the earlier objects *unless* we need to defragment.
941 */
942 retry = 0;
943 do {
944 int ret = 0;
945
946 /* Unbind any ill-fitting objects or pin. */
947 list_for_each_entry(vma, vmas, exec_list) {
948 if (!drm_mm_node_allocated(&vma->node))
949 continue;
950
951 if (eb_vma_misplaced(vma))
952 ret = i915_vma_unbind(vma);
953 else
954 ret = i915_gem_execbuffer_reserve_vma(vma,
955 engine,
956 need_relocs);
957 if (ret)
958 goto err;
959 }
960
961 /* Bind fresh objects */
962 list_for_each_entry(vma, vmas, exec_list) {
963 if (drm_mm_node_allocated(&vma->node))
964 continue;
965
966 ret = i915_gem_execbuffer_reserve_vma(vma, engine,
967 need_relocs);
968 if (ret)
969 goto err;
970 }
971
972 err:
973 if (ret != -ENOSPC || retry++)
974 return ret;
975
976 /* Decrement pin count for bound objects */
977 list_for_each_entry(vma, vmas, exec_list)
978 i915_gem_execbuffer_unreserve_vma(vma);
979
980 ret = i915_gem_evict_vm(vm, true);
981 if (ret)
982 return ret;
983 } while (1);
984 }
985
986 static int
987 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
988 struct drm_i915_gem_execbuffer2 *args,
989 struct drm_file *file,
990 struct intel_engine_cs *engine,
991 struct eb_vmas *eb,
992 struct drm_i915_gem_exec_object2 *exec,
993 struct i915_gem_context *ctx)
994 {
995 struct drm_i915_gem_relocation_entry *reloc;
996 struct i915_address_space *vm;
997 struct i915_vma *vma;
998 bool need_relocs;
999 int *reloc_offset;
1000 int i, total, ret;
1001 unsigned count = args->buffer_count;
1002
1003 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
1004
1005 /* We may process another execbuffer during the unlock... */
1006 while (!list_empty(&eb->vmas)) {
1007 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
1008 list_del_init(&vma->exec_list);
1009 i915_gem_execbuffer_unreserve_vma(vma);
1010 i915_vma_put(vma);
1011 }
1012
1013 mutex_unlock(&dev->struct_mutex);
1014
1015 total = 0;
1016 for (i = 0; i < count; i++)
1017 total += exec[i].relocation_count;
1018
1019 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
1020 reloc = drm_malloc_ab(total, sizeof(*reloc));
1021 if (reloc == NULL || reloc_offset == NULL) {
1022 drm_free_large(reloc);
1023 drm_free_large(reloc_offset);
1024 mutex_lock(&dev->struct_mutex);
1025 return -ENOMEM;
1026 }
1027
1028 total = 0;
1029 for (i = 0; i < count; i++) {
1030 struct drm_i915_gem_relocation_entry __user *user_relocs;
1031 u64 invalid_offset = (u64)-1;
1032 int j;
1033
1034 user_relocs = u64_to_user_ptr(exec[i].relocs_ptr);
1035
1036 if (copy_from_user(reloc+total, user_relocs,
1037 exec[i].relocation_count * sizeof(*reloc))) {
1038 ret = -EFAULT;
1039 mutex_lock(&dev->struct_mutex);
1040 goto err;
1041 }
1042
1043 /* As we do not update the known relocation offsets after
1044 * relocating (due to the complexities in lock handling),
1045 * we need to mark them as invalid now so that we force the
1046 * relocation processing next time. Just in case the target
1047 * object is evicted and then rebound into its old
1048 * presumed_offset before the next execbuffer - if that
1049 * happened we would make the mistake of assuming that the
1050 * relocations were valid.
1051 */
1052 for (j = 0; j < exec[i].relocation_count; j++) {
1053 if (__copy_to_user(&user_relocs[j].presumed_offset,
1054 &invalid_offset,
1055 sizeof(invalid_offset))) {
1056 ret = -EFAULT;
1057 mutex_lock(&dev->struct_mutex);
1058 goto err;
1059 }
1060 }
1061
1062 reloc_offset[i] = total;
1063 total += exec[i].relocation_count;
1064 }
1065
1066 ret = i915_mutex_lock_interruptible(dev);
1067 if (ret) {
1068 mutex_lock(&dev->struct_mutex);
1069 goto err;
1070 }
1071
1072 /* reacquire the objects */
1073 eb_reset(eb);
1074 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1075 if (ret)
1076 goto err;
1077
1078 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1079 ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1080 &need_relocs);
1081 if (ret)
1082 goto err;
1083
1084 list_for_each_entry(vma, &eb->vmas, exec_list) {
1085 int offset = vma->exec_entry - exec;
1086 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
1087 reloc + reloc_offset[offset]);
1088 if (ret)
1089 goto err;
1090 }
1091
1092 /* Leave the user relocations as are, this is the painfully slow path,
1093 * and we want to avoid the complication of dropping the lock whilst
1094 * having buffers reserved in the aperture and so causing spurious
1095 * ENOSPC for random operations.
1096 */
1097
1098 err:
1099 drm_free_large(reloc);
1100 drm_free_large(reloc_offset);
1101 return ret;
1102 }
1103
1104 static int
1105 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
1106 struct list_head *vmas)
1107 {
1108 struct i915_vma *vma;
1109 int ret;
1110
1111 list_for_each_entry(vma, vmas, exec_list) {
1112 struct drm_i915_gem_object *obj = vma->obj;
1113
1114 ret = i915_gem_request_await_object
1115 (req, obj, obj->base.pending_write_domain);
1116 if (ret)
1117 return ret;
1118
1119 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
1120 i915_gem_clflush_object(obj, false);
1121 }
1122
1123 /* Unconditionally flush any chipset caches (for streaming writes). */
1124 i915_gem_chipset_flush(req->engine->i915);
1125
1126 /* Unconditionally invalidate GPU caches and TLBs. */
1127 return req->engine->emit_flush(req, EMIT_INVALIDATE);
1128 }
1129
1130 static bool
1131 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1132 {
1133 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
1134 return false;
1135
1136 /* Kernel clipping was a DRI1 misfeature */
1137 if (exec->num_cliprects || exec->cliprects_ptr)
1138 return false;
1139
1140 if (exec->DR4 == 0xffffffff) {
1141 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1142 exec->DR4 = 0;
1143 }
1144 if (exec->DR1 || exec->DR4)
1145 return false;
1146
1147 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1148 return false;
1149
1150 return true;
1151 }
1152
1153 static int
1154 validate_exec_list(struct drm_device *dev,
1155 struct drm_i915_gem_exec_object2 *exec,
1156 int count)
1157 {
1158 unsigned relocs_total = 0;
1159 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1160 unsigned invalid_flags;
1161 int i;
1162
1163 /* INTERNAL flags must not overlap with external ones */
1164 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS);
1165
1166 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1167 if (USES_FULL_PPGTT(dev))
1168 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1169
1170 for (i = 0; i < count; i++) {
1171 char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr);
1172 int length; /* limited by fault_in_pages_readable() */
1173
1174 if (exec[i].flags & invalid_flags)
1175 return -EINVAL;
1176
1177 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1178 * any non-page-aligned or non-canonical addresses.
1179 */
1180 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1181 if (exec[i].offset !=
1182 gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1183 return -EINVAL;
1184
1185 /* From drm_mm perspective address space is continuous,
1186 * so from this point we're always using non-canonical
1187 * form internally.
1188 */
1189 exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1190 }
1191
1192 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1193 return -EINVAL;
1194
1195 /* pad_to_size was once a reserved field, so sanitize it */
1196 if (exec[i].flags & EXEC_OBJECT_PAD_TO_SIZE) {
1197 if (offset_in_page(exec[i].pad_to_size))
1198 return -EINVAL;
1199 } else {
1200 exec[i].pad_to_size = 0;
1201 }
1202
1203 /* First check for malicious input causing overflow in
1204 * the worst case where we need to allocate the entire
1205 * relocation tree as a single array.
1206 */
1207 if (exec[i].relocation_count > relocs_max - relocs_total)
1208 return -EINVAL;
1209 relocs_total += exec[i].relocation_count;
1210
1211 length = exec[i].relocation_count *
1212 sizeof(struct drm_i915_gem_relocation_entry);
1213 /*
1214 * We must check that the entire relocation array is safe
1215 * to read, but since we may need to update the presumed
1216 * offsets during execution, check for full write access.
1217 */
1218 if (!access_ok(VERIFY_WRITE, ptr, length))
1219 return -EFAULT;
1220
1221 if (likely(!i915.prefault_disable)) {
1222 if (fault_in_pages_readable(ptr, length))
1223 return -EFAULT;
1224 }
1225 }
1226
1227 return 0;
1228 }
1229
1230 static struct i915_gem_context *
1231 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1232 struct intel_engine_cs *engine, const u32 ctx_id)
1233 {
1234 struct i915_gem_context *ctx;
1235
1236 ctx = i915_gem_context_lookup(file->driver_priv, ctx_id);
1237 if (IS_ERR(ctx))
1238 return ctx;
1239
1240 if (i915_gem_context_is_banned(ctx)) {
1241 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1242 return ERR_PTR(-EIO);
1243 }
1244
1245 return ctx;
1246 }
1247
1248 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
1249 {
1250 return !(obj->cache_level == I915_CACHE_NONE ||
1251 obj->cache_level == I915_CACHE_WT);
1252 }
1253
1254 void i915_vma_move_to_active(struct i915_vma *vma,
1255 struct drm_i915_gem_request *req,
1256 unsigned int flags)
1257 {
1258 struct drm_i915_gem_object *obj = vma->obj;
1259 const unsigned int idx = req->engine->id;
1260
1261 lockdep_assert_held(&req->i915->drm.struct_mutex);
1262 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1263
1264 /* Add a reference if we're newly entering the active list.
1265 * The order in which we add operations to the retirement queue is
1266 * vital here: mark_active adds to the start of the callback list,
1267 * such that subsequent callbacks are called first. Therefore we
1268 * add the active reference first and queue for it to be dropped
1269 * *last*.
1270 */
1271 if (!i915_vma_is_active(vma))
1272 obj->active_count++;
1273 i915_vma_set_active(vma, idx);
1274 i915_gem_active_set(&vma->last_read[idx], req);
1275 list_move_tail(&vma->vm_link, &vma->vm->active_list);
1276
1277 if (flags & EXEC_OBJECT_WRITE) {
1278 if (intel_fb_obj_invalidate(obj, ORIGIN_CS))
1279 i915_gem_active_set(&obj->frontbuffer_write, req);
1280
1281 /* update for the implicit flush after a batch */
1282 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1283 if (!obj->cache_dirty && gpu_write_needs_clflush(obj))
1284 obj->cache_dirty = true;
1285 }
1286
1287 if (flags & EXEC_OBJECT_NEEDS_FENCE)
1288 i915_gem_active_set(&vma->last_fence, req);
1289 }
1290
1291 static void eb_export_fence(struct drm_i915_gem_object *obj,
1292 struct drm_i915_gem_request *req,
1293 unsigned int flags)
1294 {
1295 struct reservation_object *resv = obj->resv;
1296
1297 /* Ignore errors from failing to allocate the new fence, we can't
1298 * handle an error right now. Worst case should be missed
1299 * synchronisation leading to rendering corruption.
1300 */
1301 ww_mutex_lock(&resv->lock, NULL);
1302 if (flags & EXEC_OBJECT_WRITE)
1303 reservation_object_add_excl_fence(resv, &req->fence);
1304 else if (reservation_object_reserve_shared(resv) == 0)
1305 reservation_object_add_shared_fence(resv, &req->fence);
1306 ww_mutex_unlock(&resv->lock);
1307 }
1308
1309 static void
1310 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1311 struct drm_i915_gem_request *req)
1312 {
1313 struct i915_vma *vma;
1314
1315 list_for_each_entry(vma, vmas, exec_list) {
1316 struct drm_i915_gem_object *obj = vma->obj;
1317 u32 old_read = obj->base.read_domains;
1318 u32 old_write = obj->base.write_domain;
1319
1320 obj->base.write_domain = obj->base.pending_write_domain;
1321 if (obj->base.write_domain)
1322 vma->exec_entry->flags |= EXEC_OBJECT_WRITE;
1323 else
1324 obj->base.pending_read_domains |= obj->base.read_domains;
1325 obj->base.read_domains = obj->base.pending_read_domains;
1326
1327 i915_vma_move_to_active(vma, req, vma->exec_entry->flags);
1328 eb_export_fence(obj, req, vma->exec_entry->flags);
1329 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1330 }
1331 }
1332
1333 static int
1334 i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1335 {
1336 struct intel_ring *ring = req->ring;
1337 int ret, i;
1338
1339 if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1340 DRM_DEBUG("sol reset is gen7/rcs only\n");
1341 return -EINVAL;
1342 }
1343
1344 ret = intel_ring_begin(req, 4 * 3);
1345 if (ret)
1346 return ret;
1347
1348 for (i = 0; i < 4; i++) {
1349 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1350 intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1351 intel_ring_emit(ring, 0);
1352 }
1353
1354 intel_ring_advance(ring);
1355
1356 return 0;
1357 }
1358
1359 static struct i915_vma *
1360 i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
1361 struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1362 struct drm_i915_gem_object *batch_obj,
1363 struct eb_vmas *eb,
1364 u32 batch_start_offset,
1365 u32 batch_len,
1366 bool is_master)
1367 {
1368 struct drm_i915_gem_object *shadow_batch_obj;
1369 struct i915_vma *vma;
1370 int ret;
1371
1372 shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool,
1373 PAGE_ALIGN(batch_len));
1374 if (IS_ERR(shadow_batch_obj))
1375 return ERR_CAST(shadow_batch_obj);
1376
1377 ret = intel_engine_cmd_parser(engine,
1378 batch_obj,
1379 shadow_batch_obj,
1380 batch_start_offset,
1381 batch_len,
1382 is_master);
1383 if (ret) {
1384 if (ret == -EACCES) /* unhandled chained batch */
1385 vma = NULL;
1386 else
1387 vma = ERR_PTR(ret);
1388 goto out;
1389 }
1390
1391 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1392 if (IS_ERR(vma))
1393 goto out;
1394
1395 memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1396
1397 vma->exec_entry = shadow_exec_entry;
1398 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1399 i915_gem_object_get(shadow_batch_obj);
1400 list_add_tail(&vma->exec_list, &eb->vmas);
1401
1402 out:
1403 i915_gem_object_unpin_pages(shadow_batch_obj);
1404 return vma;
1405 }
1406
1407 static int
1408 execbuf_submit(struct i915_execbuffer_params *params,
1409 struct drm_i915_gem_execbuffer2 *args,
1410 struct list_head *vmas)
1411 {
1412 struct drm_i915_private *dev_priv = params->request->i915;
1413 u64 exec_start, exec_len;
1414 int instp_mode;
1415 u32 instp_mask;
1416 int ret;
1417
1418 ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1419 if (ret)
1420 return ret;
1421
1422 ret = i915_switch_context(params->request);
1423 if (ret)
1424 return ret;
1425
1426 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1427 instp_mask = I915_EXEC_CONSTANTS_MASK;
1428 switch (instp_mode) {
1429 case I915_EXEC_CONSTANTS_REL_GENERAL:
1430 case I915_EXEC_CONSTANTS_ABSOLUTE:
1431 case I915_EXEC_CONSTANTS_REL_SURFACE:
1432 if (instp_mode != 0 && params->engine->id != RCS) {
1433 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1434 return -EINVAL;
1435 }
1436
1437 if (instp_mode != dev_priv->relative_constants_mode) {
1438 if (INTEL_INFO(dev_priv)->gen < 4) {
1439 DRM_DEBUG("no rel constants on pre-gen4\n");
1440 return -EINVAL;
1441 }
1442
1443 if (INTEL_INFO(dev_priv)->gen > 5 &&
1444 instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1445 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1446 return -EINVAL;
1447 }
1448
1449 /* The HW changed the meaning on this bit on gen6 */
1450 if (INTEL_INFO(dev_priv)->gen >= 6)
1451 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1452 }
1453 break;
1454 default:
1455 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1456 return -EINVAL;
1457 }
1458
1459 if (params->engine->id == RCS &&
1460 instp_mode != dev_priv->relative_constants_mode) {
1461 struct intel_ring *ring = params->request->ring;
1462
1463 ret = intel_ring_begin(params->request, 4);
1464 if (ret)
1465 return ret;
1466
1467 intel_ring_emit(ring, MI_NOOP);
1468 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1469 intel_ring_emit_reg(ring, INSTPM);
1470 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1471 intel_ring_advance(ring);
1472
1473 dev_priv->relative_constants_mode = instp_mode;
1474 }
1475
1476 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1477 ret = i915_reset_gen7_sol_offsets(params->request);
1478 if (ret)
1479 return ret;
1480 }
1481
1482 exec_len = args->batch_len;
1483 exec_start = params->batch->node.start +
1484 params->args_batch_start_offset;
1485
1486 if (exec_len == 0)
1487 exec_len = params->batch->size - params->args_batch_start_offset;
1488
1489 ret = params->engine->emit_bb_start(params->request,
1490 exec_start, exec_len,
1491 params->dispatch_flags);
1492 if (ret)
1493 return ret;
1494
1495 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1496
1497 i915_gem_execbuffer_move_to_active(vmas, params->request);
1498
1499 return 0;
1500 }
1501
1502 /**
1503 * Find one BSD ring to dispatch the corresponding BSD command.
1504 * The engine index is returned.
1505 */
1506 static unsigned int
1507 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1508 struct drm_file *file)
1509 {
1510 struct drm_i915_file_private *file_priv = file->driver_priv;
1511
1512 /* Check whether the file_priv has already selected one ring. */
1513 if ((int)file_priv->bsd_engine < 0)
1514 file_priv->bsd_engine = atomic_fetch_xor(1,
1515 &dev_priv->mm.bsd_engine_dispatch_index);
1516
1517 return file_priv->bsd_engine;
1518 }
1519
1520 #define I915_USER_RINGS (4)
1521
1522 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1523 [I915_EXEC_DEFAULT] = RCS,
1524 [I915_EXEC_RENDER] = RCS,
1525 [I915_EXEC_BLT] = BCS,
1526 [I915_EXEC_BSD] = VCS,
1527 [I915_EXEC_VEBOX] = VECS
1528 };
1529
1530 static struct intel_engine_cs *
1531 eb_select_engine(struct drm_i915_private *dev_priv,
1532 struct drm_file *file,
1533 struct drm_i915_gem_execbuffer2 *args)
1534 {
1535 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
1536 struct intel_engine_cs *engine;
1537
1538 if (user_ring_id > I915_USER_RINGS) {
1539 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
1540 return NULL;
1541 }
1542
1543 if ((user_ring_id != I915_EXEC_BSD) &&
1544 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1545 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1546 "bsd dispatch flags: %d\n", (int)(args->flags));
1547 return NULL;
1548 }
1549
1550 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
1551 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
1552
1553 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
1554 bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
1555 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
1556 bsd_idx <= I915_EXEC_BSD_RING2) {
1557 bsd_idx >>= I915_EXEC_BSD_SHIFT;
1558 bsd_idx--;
1559 } else {
1560 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1561 bsd_idx);
1562 return NULL;
1563 }
1564
1565 engine = dev_priv->engine[_VCS(bsd_idx)];
1566 } else {
1567 engine = dev_priv->engine[user_ring_map[user_ring_id]];
1568 }
1569
1570 if (!engine) {
1571 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
1572 return NULL;
1573 }
1574
1575 return engine;
1576 }
1577
1578 static int
1579 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1580 struct drm_file *file,
1581 struct drm_i915_gem_execbuffer2 *args,
1582 struct drm_i915_gem_exec_object2 *exec)
1583 {
1584 struct drm_i915_private *dev_priv = to_i915(dev);
1585 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1586 struct eb_vmas *eb;
1587 struct drm_i915_gem_exec_object2 shadow_exec_entry;
1588 struct intel_engine_cs *engine;
1589 struct i915_gem_context *ctx;
1590 struct i915_address_space *vm;
1591 struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1592 struct i915_execbuffer_params *params = &params_master;
1593 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1594 u32 dispatch_flags;
1595 int ret;
1596 bool need_relocs;
1597
1598 if (!i915_gem_check_execbuffer(args))
1599 return -EINVAL;
1600
1601 ret = validate_exec_list(dev, exec, args->buffer_count);
1602 if (ret)
1603 return ret;
1604
1605 dispatch_flags = 0;
1606 if (args->flags & I915_EXEC_SECURE) {
1607 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
1608 return -EPERM;
1609
1610 dispatch_flags |= I915_DISPATCH_SECURE;
1611 }
1612 if (args->flags & I915_EXEC_IS_PINNED)
1613 dispatch_flags |= I915_DISPATCH_PINNED;
1614
1615 engine = eb_select_engine(dev_priv, file, args);
1616 if (!engine)
1617 return -EINVAL;
1618
1619 if (args->buffer_count < 1) {
1620 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1621 return -EINVAL;
1622 }
1623
1624 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1625 if (!HAS_RESOURCE_STREAMER(dev_priv)) {
1626 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1627 return -EINVAL;
1628 }
1629 if (engine->id != RCS) {
1630 DRM_DEBUG("RS is not available on %s\n",
1631 engine->name);
1632 return -EINVAL;
1633 }
1634
1635 dispatch_flags |= I915_DISPATCH_RS;
1636 }
1637
1638 /* Take a local wakeref for preparing to dispatch the execbuf as
1639 * we expect to access the hardware fairly frequently in the
1640 * process. Upon first dispatch, we acquire another prolonged
1641 * wakeref that we hold until the GPU has been idle for at least
1642 * 100ms.
1643 */
1644 intel_runtime_pm_get(dev_priv);
1645
1646 ret = i915_mutex_lock_interruptible(dev);
1647 if (ret)
1648 goto pre_mutex_err;
1649
1650 ctx = i915_gem_validate_context(dev, file, engine, ctx_id);
1651 if (IS_ERR(ctx)) {
1652 mutex_unlock(&dev->struct_mutex);
1653 ret = PTR_ERR(ctx);
1654 goto pre_mutex_err;
1655 }
1656
1657 i915_gem_context_get(ctx);
1658
1659 if (ctx->ppgtt)
1660 vm = &ctx->ppgtt->base;
1661 else
1662 vm = &ggtt->base;
1663
1664 memset(&params_master, 0x00, sizeof(params_master));
1665
1666 eb = eb_create(dev_priv, args);
1667 if (eb == NULL) {
1668 i915_gem_context_put(ctx);
1669 mutex_unlock(&dev->struct_mutex);
1670 ret = -ENOMEM;
1671 goto pre_mutex_err;
1672 }
1673
1674 /* Look up object handles */
1675 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1676 if (ret)
1677 goto err;
1678
1679 /* take note of the batch buffer before we might reorder the lists */
1680 params->batch = eb_get_batch(eb);
1681
1682 /* Move the objects en-masse into the GTT, evicting if necessary. */
1683 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1684 ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1685 &need_relocs);
1686 if (ret)
1687 goto err;
1688
1689 /* The objects are in their final locations, apply the relocations. */
1690 if (need_relocs)
1691 ret = i915_gem_execbuffer_relocate(eb);
1692 if (ret) {
1693 if (ret == -EFAULT) {
1694 ret = i915_gem_execbuffer_relocate_slow(dev, args, file,
1695 engine,
1696 eb, exec, ctx);
1697 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1698 }
1699 if (ret)
1700 goto err;
1701 }
1702
1703 /* Set the pending read domains for the batch buffer to COMMAND */
1704 if (params->batch->obj->base.pending_write_domain) {
1705 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1706 ret = -EINVAL;
1707 goto err;
1708 }
1709 if (args->batch_start_offset > params->batch->size ||
1710 args->batch_len > params->batch->size - args->batch_start_offset) {
1711 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
1712 ret = -EINVAL;
1713 goto err;
1714 }
1715
1716 params->args_batch_start_offset = args->batch_start_offset;
1717 if (engine->needs_cmd_parser && args->batch_len) {
1718 struct i915_vma *vma;
1719
1720 vma = i915_gem_execbuffer_parse(engine, &shadow_exec_entry,
1721 params->batch->obj,
1722 eb,
1723 args->batch_start_offset,
1724 args->batch_len,
1725 drm_is_current_master(file));
1726 if (IS_ERR(vma)) {
1727 ret = PTR_ERR(vma);
1728 goto err;
1729 }
1730
1731 if (vma) {
1732 /*
1733 * Batch parsed and accepted:
1734 *
1735 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1736 * bit from MI_BATCH_BUFFER_START commands issued in
1737 * the dispatch_execbuffer implementations. We
1738 * specifically don't want that set on batches the
1739 * command parser has accepted.
1740 */
1741 dispatch_flags |= I915_DISPATCH_SECURE;
1742 params->args_batch_start_offset = 0;
1743 params->batch = vma;
1744 }
1745 }
1746
1747 params->batch->obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1748
1749 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1750 * batch" bit. Hence we need to pin secure batches into the global gtt.
1751 * hsw should have this fixed, but bdw mucks it up again. */
1752 if (dispatch_flags & I915_DISPATCH_SECURE) {
1753 struct drm_i915_gem_object *obj = params->batch->obj;
1754 struct i915_vma *vma;
1755
1756 /*
1757 * So on first glance it looks freaky that we pin the batch here
1758 * outside of the reservation loop. But:
1759 * - The batch is already pinned into the relevant ppgtt, so we
1760 * already have the backing storage fully allocated.
1761 * - No other BO uses the global gtt (well contexts, but meh),
1762 * so we don't really have issues with multiple objects not
1763 * fitting due to fragmentation.
1764 * So this is actually safe.
1765 */
1766 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
1767 if (IS_ERR(vma)) {
1768 ret = PTR_ERR(vma);
1769 goto err;
1770 }
1771
1772 params->batch = vma;
1773 }
1774
1775 /* Allocate a request for this batch buffer nice and early. */
1776 params->request = i915_gem_request_alloc(engine, ctx);
1777 if (IS_ERR(params->request)) {
1778 ret = PTR_ERR(params->request);
1779 goto err_batch_unpin;
1780 }
1781
1782 /* Whilst this request exists, batch_obj will be on the
1783 * active_list, and so will hold the active reference. Only when this
1784 * request is retired will the the batch_obj be moved onto the
1785 * inactive_list and lose its active reference. Hence we do not need
1786 * to explicitly hold another reference here.
1787 */
1788 params->request->batch = params->batch;
1789
1790 ret = i915_gem_request_add_to_client(params->request, file);
1791 if (ret)
1792 goto err_request;
1793
1794 /*
1795 * Save assorted stuff away to pass through to *_submission().
1796 * NB: This data should be 'persistent' and not local as it will
1797 * kept around beyond the duration of the IOCTL once the GPU
1798 * scheduler arrives.
1799 */
1800 params->dev = dev;
1801 params->file = file;
1802 params->engine = engine;
1803 params->dispatch_flags = dispatch_flags;
1804 params->ctx = ctx;
1805
1806 ret = execbuf_submit(params, args, &eb->vmas);
1807 err_request:
1808 __i915_add_request(params->request, ret == 0);
1809
1810 err_batch_unpin:
1811 /*
1812 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1813 * batch vma for correctness. For less ugly and less fragility this
1814 * needs to be adjusted to also track the ggtt batch vma properly as
1815 * active.
1816 */
1817 if (dispatch_flags & I915_DISPATCH_SECURE)
1818 i915_vma_unpin(params->batch);
1819 err:
1820 /* the request owns the ref now */
1821 i915_gem_context_put(ctx);
1822 eb_destroy(eb);
1823
1824 mutex_unlock(&dev->struct_mutex);
1825
1826 pre_mutex_err:
1827 /* intel_gpu_busy should also get a ref, so it will free when the device
1828 * is really idle. */
1829 intel_runtime_pm_put(dev_priv);
1830 return ret;
1831 }
1832
1833 /*
1834 * Legacy execbuffer just creates an exec2 list from the original exec object
1835 * list array and passes it to the real function.
1836 */
1837 int
1838 i915_gem_execbuffer(struct drm_device *dev, void *data,
1839 struct drm_file *file)
1840 {
1841 struct drm_i915_gem_execbuffer *args = data;
1842 struct drm_i915_gem_execbuffer2 exec2;
1843 struct drm_i915_gem_exec_object *exec_list = NULL;
1844 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1845 int ret, i;
1846
1847 if (args->buffer_count < 1) {
1848 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1849 return -EINVAL;
1850 }
1851
1852 /* Copy in the exec list from userland */
1853 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1854 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1855 if (exec_list == NULL || exec2_list == NULL) {
1856 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1857 args->buffer_count);
1858 drm_free_large(exec_list);
1859 drm_free_large(exec2_list);
1860 return -ENOMEM;
1861 }
1862 ret = copy_from_user(exec_list,
1863 u64_to_user_ptr(args->buffers_ptr),
1864 sizeof(*exec_list) * args->buffer_count);
1865 if (ret != 0) {
1866 DRM_DEBUG("copy %d exec entries failed %d\n",
1867 args->buffer_count, ret);
1868 drm_free_large(exec_list);
1869 drm_free_large(exec2_list);
1870 return -EFAULT;
1871 }
1872
1873 for (i = 0; i < args->buffer_count; i++) {
1874 exec2_list[i].handle = exec_list[i].handle;
1875 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1876 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1877 exec2_list[i].alignment = exec_list[i].alignment;
1878 exec2_list[i].offset = exec_list[i].offset;
1879 if (INTEL_GEN(to_i915(dev)) < 4)
1880 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1881 else
1882 exec2_list[i].flags = 0;
1883 }
1884
1885 exec2.buffers_ptr = args->buffers_ptr;
1886 exec2.buffer_count = args->buffer_count;
1887 exec2.batch_start_offset = args->batch_start_offset;
1888 exec2.batch_len = args->batch_len;
1889 exec2.DR1 = args->DR1;
1890 exec2.DR4 = args->DR4;
1891 exec2.num_cliprects = args->num_cliprects;
1892 exec2.cliprects_ptr = args->cliprects_ptr;
1893 exec2.flags = I915_EXEC_RENDER;
1894 i915_execbuffer2_set_context_id(exec2, 0);
1895
1896 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1897 if (!ret) {
1898 struct drm_i915_gem_exec_object __user *user_exec_list =
1899 u64_to_user_ptr(args->buffers_ptr);
1900
1901 /* Copy the new buffer offsets back to the user's exec list. */
1902 for (i = 0; i < args->buffer_count; i++) {
1903 exec2_list[i].offset =
1904 gen8_canonical_addr(exec2_list[i].offset);
1905 ret = __copy_to_user(&user_exec_list[i].offset,
1906 &exec2_list[i].offset,
1907 sizeof(user_exec_list[i].offset));
1908 if (ret) {
1909 ret = -EFAULT;
1910 DRM_DEBUG("failed to copy %d exec entries "
1911 "back to user (%d)\n",
1912 args->buffer_count, ret);
1913 break;
1914 }
1915 }
1916 }
1917
1918 drm_free_large(exec_list);
1919 drm_free_large(exec2_list);
1920 return ret;
1921 }
1922
1923 int
1924 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1925 struct drm_file *file)
1926 {
1927 struct drm_i915_gem_execbuffer2 *args = data;
1928 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1929 int ret;
1930
1931 if (args->buffer_count < 1 ||
1932 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1933 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1934 return -EINVAL;
1935 }
1936
1937 if (args->rsvd2 != 0) {
1938 DRM_DEBUG("dirty rvsd2 field\n");
1939 return -EINVAL;
1940 }
1941
1942 exec2_list = drm_malloc_gfp(args->buffer_count,
1943 sizeof(*exec2_list),
1944 GFP_TEMPORARY);
1945 if (exec2_list == NULL) {
1946 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1947 args->buffer_count);
1948 return -ENOMEM;
1949 }
1950 ret = copy_from_user(exec2_list,
1951 u64_to_user_ptr(args->buffers_ptr),
1952 sizeof(*exec2_list) * args->buffer_count);
1953 if (ret != 0) {
1954 DRM_DEBUG("copy %d exec entries failed %d\n",
1955 args->buffer_count, ret);
1956 drm_free_large(exec2_list);
1957 return -EFAULT;
1958 }
1959
1960 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1961 if (!ret) {
1962 /* Copy the new buffer offsets back to the user's exec list. */
1963 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1964 u64_to_user_ptr(args->buffers_ptr);
1965 int i;
1966
1967 for (i = 0; i < args->buffer_count; i++) {
1968 exec2_list[i].offset =
1969 gen8_canonical_addr(exec2_list[i].offset);
1970 ret = __copy_to_user(&user_exec_list[i].offset,
1971 &exec2_list[i].offset,
1972 sizeof(user_exec_list[i].offset));
1973 if (ret) {
1974 ret = -EFAULT;
1975 DRM_DEBUG("failed to copy %d exec entries "
1976 "back to user\n",
1977 args->buffer_count);
1978 break;
1979 }
1980 }
1981 }
1982
1983 drm_free_large(exec2_list);
1984 return ret;
1985 }
Linux with added FPC-III support