drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30
  31 #define GEN_DEFAULT_PIPEOFFSETS \
  32         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  33                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  34         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  35                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  36         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  37
  38 #define GEN_CHV_PIPEOFFSETS \
  39         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  40                           CHV_PIPE_C_OFFSET }, \
  41         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  42                            CHV_TRANSCODER_C_OFFSET, }, \
  43         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  44                              CHV_PALETTE_C_OFFSET }
  45
  46 #define CURSOR_OFFSETS \
  47         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  48
  49 #define IVB_CURSOR_OFFSETS \
  50         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  51
  52 #define BDW_COLORS \
  53         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  54 #define CHV_COLORS \
  55         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  56
  57 /* Keep in gen based order, and chronological order within a gen */
  58 #define GEN2_FEATURES \
  59         .gen = 2, .num_pipes = 1, \
  60         .has_overlay = 1, .overlay_needs_physical = 1, \
  61         .has_gmch_display = 1, \
  62         .hws_needs_physical = 1, \
  63         .ring_mask = RENDER_RING, \
  64         GEN_DEFAULT_PIPEOFFSETS, \
  65         CURSOR_OFFSETS
  66
  67 static const struct intel_device_info intel_i830_info = {
  68         GEN2_FEATURES,
  69         .platform = INTEL_I830,
  70         .is_mobile = 1, .cursor_needs_physical = 1,
  71         .num_pipes = 2, /* legal, last one wins */
  72 };
  73
  74 static const struct intel_device_info intel_i845g_info = {
  75         GEN2_FEATURES,
  76         .platform = INTEL_I845G,
  77 };
  78
  79 static const struct intel_device_info intel_i85x_info = {
  80         GEN2_FEATURES,
  81         .platform = INTEL_I85X, .is_mobile = 1,
  82         .num_pipes = 2, /* legal, last one wins */
  83         .cursor_needs_physical = 1,
  84         .has_fbc = 1,
  85 };
  86
  87 static const struct intel_device_info intel_i865g_info = {
  88         GEN2_FEATURES,
  89         .platform = INTEL_I865G,
  90 };
  91
  92 #define GEN3_FEATURES \
  93         .gen = 3, .num_pipes = 2, \
  94         .has_gmch_display = 1, \
  95         .ring_mask = RENDER_RING, \
  96         GEN_DEFAULT_PIPEOFFSETS, \
  97         CURSOR_OFFSETS
  98
  99 static const struct intel_device_info intel_i915g_info = {
 100         GEN3_FEATURES,
 101         .platform = INTEL_I915G, .cursor_needs_physical = 1,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .hws_needs_physical = 1,
 104 };
 105
 106 static const struct intel_device_info intel_i915gm_info = {
 107         GEN3_FEATURES,
 108         .platform = INTEL_I915GM,
 109         .is_mobile = 1,
 110         .cursor_needs_physical = 1,
 111         .has_overlay = 1, .overlay_needs_physical = 1,
 112         .supports_tv = 1,
 113         .has_fbc = 1,
 114         .hws_needs_physical = 1,
 115 };
 116
 117 static const struct intel_device_info intel_i945g_info = {
 118         GEN3_FEATURES,
 119         .platform = INTEL_I945G,
 120         .has_hotplug = 1, .cursor_needs_physical = 1,
 121         .has_overlay = 1, .overlay_needs_physical = 1,
 122         .hws_needs_physical = 1,
 123 };
 124
 125 static const struct intel_device_info intel_i945gm_info = {
 126         GEN3_FEATURES,
 127         .platform = INTEL_I945GM, .is_mobile = 1,
 128         .has_hotplug = 1, .cursor_needs_physical = 1,
 129         .has_overlay = 1, .overlay_needs_physical = 1,
 130         .supports_tv = 1,
 131         .has_fbc = 1,
 132         .hws_needs_physical = 1,
 133 };
 134
 135 static const struct intel_device_info intel_g33_info = {
 136         GEN3_FEATURES,
 137         .platform = INTEL_G33,
 138         .has_hotplug = 1,
 139         .has_overlay = 1,
 140 };
 141
 142 static const struct intel_device_info intel_pineview_info = {
 143         GEN3_FEATURES,
 144         .platform = INTEL_PINEVIEW, .is_mobile = 1,
 145         .has_hotplug = 1,
 146         .has_overlay = 1,
 147 };
 148
 149 #define GEN4_FEATURES \
 150         .gen = 4, .num_pipes = 2, \
 151         .has_hotplug = 1, \
 152         .has_gmch_display = 1, \
 153         .ring_mask = RENDER_RING, \
 154         GEN_DEFAULT_PIPEOFFSETS, \
 155         CURSOR_OFFSETS
 156
 157 static const struct intel_device_info intel_i965g_info = {
 158         GEN4_FEATURES,
 159         .platform = INTEL_I965G,
 160         .has_overlay = 1,
 161         .hws_needs_physical = 1,
 162 };
 163
 164 static const struct intel_device_info intel_i965gm_info = {
 165         GEN4_FEATURES,
 166         .platform = INTEL_I965GM,
 167         .is_mobile = 1, .has_fbc = 1,
 168         .has_overlay = 1,
 169         .supports_tv = 1,
 170         .hws_needs_physical = 1,
 171 };
 172
 173 static const struct intel_device_info intel_g45_info = {
 174         GEN4_FEATURES,
 175         .platform = INTEL_G45,
 176         .has_pipe_cxsr = 1,
 177         .ring_mask = RENDER_RING | BSD_RING,
 178 };
 179
 180 static const struct intel_device_info intel_gm45_info = {
 181         GEN4_FEATURES,
 182         .platform = INTEL_GM45,
 183         .is_mobile = 1, .has_fbc = 1,
 184         .has_pipe_cxsr = 1,
 185         .supports_tv = 1,
 186         .ring_mask = RENDER_RING | BSD_RING,
 187 };
 188
 189 #define GEN5_FEATURES \
 190         .gen = 5, .num_pipes = 2, \
 191         .has_hotplug = 1, \
 192         .has_gmbus_irq = 1, \
 193         .ring_mask = RENDER_RING | BSD_RING, \
 194         GEN_DEFAULT_PIPEOFFSETS, \
 195         CURSOR_OFFSETS
 196
 197 static const struct intel_device_info intel_ironlake_d_info = {
 198         GEN5_FEATURES,
 199         .platform = INTEL_IRONLAKE,
 200 };
 201
 202 static const struct intel_device_info intel_ironlake_m_info = {
 203         GEN5_FEATURES,
 204         .platform = INTEL_IRONLAKE,
 205         .is_mobile = 1,
 206 };
 207
 208 #define GEN6_FEATURES \
 209         .gen = 6, .num_pipes = 2, \
 210         .has_hotplug = 1, \
 211         .has_fbc = 1, \
 212         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 213         .has_llc = 1, \
 214         .has_rc6 = 1, \
 215         .has_rc6p = 1, \
 216         .has_gmbus_irq = 1, \
 217         .has_hw_contexts = 1, \
 218         .has_aliasing_ppgtt = 1, \
 219         GEN_DEFAULT_PIPEOFFSETS, \
 220         CURSOR_OFFSETS
 221
 222 static const struct intel_device_info intel_sandybridge_d_info = {
 223         GEN6_FEATURES,
 224         .platform = INTEL_SANDYBRIDGE,
 225 };
 226
 227 static const struct intel_device_info intel_sandybridge_m_info = {
 228         GEN6_FEATURES,
 229         .platform = INTEL_SANDYBRIDGE,
 230         .is_mobile = 1,
 231 };
 232
 233 #define GEN7_FEATURES  \
 234         .gen = 7, .num_pipes = 3, \
 235         .has_hotplug = 1, \
 236         .has_fbc = 1, \
 237         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 238         .has_llc = 1, \
 239         .has_rc6 = 1, \
 240         .has_rc6p = 1, \
 241         .has_gmbus_irq = 1, \
 242         .has_hw_contexts = 1, \
 243         .has_aliasing_ppgtt = 1, \
 244         .has_full_ppgtt = 1, \
 245         GEN_DEFAULT_PIPEOFFSETS, \
 246         IVB_CURSOR_OFFSETS
 247
 248 static const struct intel_device_info intel_ivybridge_d_info = {
 249         GEN7_FEATURES,
 250         .platform = INTEL_IVYBRIDGE,
 251         .has_l3_dpf = 1,
 252 };
 253
 254 static const struct intel_device_info intel_ivybridge_m_info = {
 255         GEN7_FEATURES,
 256         .platform = INTEL_IVYBRIDGE,
 257         .is_mobile = 1,
 258         .has_l3_dpf = 1,
 259 };
 260
 261 static const struct intel_device_info intel_ivybridge_q_info = {
 262         GEN7_FEATURES,
 263         .platform = INTEL_IVYBRIDGE,
 264         .num_pipes = 0, /* legal, last one wins */
 265         .has_l3_dpf = 1,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_info = {
 269         .platform = INTEL_VALLEYVIEW,
 270         .gen = 7,
 271         .is_lp = 1,
 272         .num_pipes = 2,
 273         .has_psr = 1,
 274         .has_runtime_pm = 1,
 275         .has_rc6 = 1,
 276         .has_gmbus_irq = 1,
 277         .has_hw_contexts = 1,
 278         .has_gmch_display = 1,
 279         .has_hotplug = 1,
 280         .has_aliasing_ppgtt = 1,
 281         .has_full_ppgtt = 1,
 282         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 283         .display_mmio_offset = VLV_DISPLAY_BASE,
 284         GEN_DEFAULT_PIPEOFFSETS,
 285         CURSOR_OFFSETS
 286 };
 287
 288 #define HSW_FEATURES  \
 289         GEN7_FEATURES, \
 290         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 291         .has_ddi = 1, \
 292         .has_fpga_dbg = 1, \
 293         .has_psr = 1, \
 294         .has_resource_streamer = 1, \
 295         .has_dp_mst = 1, \
 296         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 297         .has_runtime_pm = 1
 298
 299 static const struct intel_device_info intel_haswell_info = {
 300         HSW_FEATURES,
 301         .platform = INTEL_HASWELL,
 302         .has_l3_dpf = 1,
 303 };
 304
 305 #define BDW_FEATURES \
 306         HSW_FEATURES, \
 307         BDW_COLORS, \
 308         .has_logical_ring_contexts = 1, \
 309         .has_full_48bit_ppgtt = 1, \
 310         .has_64bit_reloc = 1
 311
 312 static const struct intel_device_info intel_broadwell_info = {
 313         BDW_FEATURES,
 314         .gen = 8,
 315         .platform = INTEL_BROADWELL,
 316 };
 317
 318 static const struct intel_device_info intel_broadwell_gt3_info = {
 319         BDW_FEATURES,
 320         .gen = 8,
 321         .platform = INTEL_BROADWELL,
 322         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 323 };
 324
 325 static const struct intel_device_info intel_cherryview_info = {
 326         .gen = 8, .num_pipes = 3,
 327         .has_hotplug = 1,
 328         .is_lp = 1,
 329         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 330         .platform = INTEL_CHERRYVIEW,
 331         .has_64bit_reloc = 1,
 332         .has_psr = 1,
 333         .has_runtime_pm = 1,
 334         .has_resource_streamer = 1,
 335         .has_rc6 = 1,
 336         .has_gmbus_irq = 1,
 337         .has_hw_contexts = 1,
 338         .has_logical_ring_contexts = 1,
 339         .has_gmch_display = 1,
 340         .has_aliasing_ppgtt = 1,
 341         .has_full_ppgtt = 1,
 342         .display_mmio_offset = VLV_DISPLAY_BASE,
 343         GEN_CHV_PIPEOFFSETS,
 344         CURSOR_OFFSETS,
 345         CHV_COLORS,
 346 };
 347
 348 static const struct intel_device_info intel_skylake_info = {
 349         BDW_FEATURES,
 350         .platform = INTEL_SKYLAKE,
 351         .gen = 9,
 352         .has_csr = 1,
 353         .has_guc = 1,
 354         .ddb_size = 896,
 355 };
 356
 357 static const struct intel_device_info intel_skylake_gt3_info = {
 358         BDW_FEATURES,
 359         .platform = INTEL_SKYLAKE,
 360         .gen = 9,
 361         .has_csr = 1,
 362         .has_guc = 1,
 363         .ddb_size = 896,
 364         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 365 };
 366
 367 #define GEN9_LP_FEATURES \
 368         .gen = 9, \
 369         .is_lp = 1, \
 370         .has_hotplug = 1, \
 371         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 372         .num_pipes = 3, \
 373         .has_64bit_reloc = 1, \
 374         .has_ddi = 1, \
 375         .has_fpga_dbg = 1, \
 376         .has_fbc = 1, \
 377         .has_runtime_pm = 1, \
 378         .has_pooled_eu = 0, \
 379         .has_csr = 1, \
 380         .has_resource_streamer = 1, \
 381         .has_rc6 = 1, \
 382         .has_dp_mst = 1, \
 383         .has_gmbus_irq = 1, \
 384         .has_hw_contexts = 1, \
 385         .has_logical_ring_contexts = 1, \
 386         .has_guc = 1, \
 387         .has_decoupled_mmio = 1, \
 388         .has_aliasing_ppgtt = 1, \
 389         .has_full_ppgtt = 1, \
 390         .has_full_48bit_ppgtt = 1, \
 391         GEN_DEFAULT_PIPEOFFSETS, \
 392         IVB_CURSOR_OFFSETS, \
 393         BDW_COLORS
 394
 395 static const struct intel_device_info intel_broxton_info = {
 396         GEN9_LP_FEATURES,
 397         .platform = INTEL_BROXTON,
 398         .ddb_size = 512,
 399 };
 400
 401 static const struct intel_device_info intel_geminilake_info = {
 402         GEN9_LP_FEATURES,
 403         .platform = INTEL_GEMINILAKE,
 404         .is_alpha_support = 1,
 405         .ddb_size = 1024,
 406 };
 407
 408 static const struct intel_device_info intel_kabylake_info = {
 409         BDW_FEATURES,
 410         .platform = INTEL_KABYLAKE,
 411         .gen = 9,
 412         .has_csr = 1,
 413         .has_guc = 1,
 414         .ddb_size = 896,
 415 };
 416
 417 static const struct intel_device_info intel_kabylake_gt3_info = {
 418         BDW_FEATURES,
 419         .platform = INTEL_KABYLAKE,
 420         .gen = 9,
 421         .has_csr = 1,
 422         .has_guc = 1,
 423         .ddb_size = 896,
 424         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 425 };
 426
 427 /*
 428  * Make sure any device matches here are from most specific to most
 429  * general.  For example, since the Quanta match is based on the subsystem
 430  * and subvendor IDs, we need it to come before the more general IVB
 431  * PCI ID matches, otherwise we'll use the wrong info struct above.
 432  */
 433 static const struct pci_device_id pciidlist[] = {
 434         INTEL_I830_IDS(&intel_i830_info),
 435         INTEL_I845G_IDS(&intel_i845g_info),
 436         INTEL_I85X_IDS(&intel_i85x_info),
 437         INTEL_I865G_IDS(&intel_i865g_info),
 438         INTEL_I915G_IDS(&intel_i915g_info),
 439         INTEL_I915GM_IDS(&intel_i915gm_info),
 440         INTEL_I945G_IDS(&intel_i945g_info),
 441         INTEL_I945GM_IDS(&intel_i945gm_info),
 442         INTEL_I965G_IDS(&intel_i965g_info),
 443         INTEL_G33_IDS(&intel_g33_info),
 444         INTEL_I965GM_IDS(&intel_i965gm_info),
 445         INTEL_GM45_IDS(&intel_gm45_info),
 446         INTEL_G45_IDS(&intel_g45_info),
 447         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 448         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 449         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 450         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
 451         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
 452         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 453         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 454         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
 455         INTEL_HSW_IDS(&intel_haswell_info),
 456         INTEL_VLV_IDS(&intel_valleyview_info),
 457         INTEL_BDW_GT12_IDS(&intel_broadwell_info),
 458         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 459         INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
 460         INTEL_CHV_IDS(&intel_cherryview_info),
 461         INTEL_SKL_GT1_IDS(&intel_skylake_info),
 462         INTEL_SKL_GT2_IDS(&intel_skylake_info),
 463         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 464         INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
 465         INTEL_BXT_IDS(&intel_broxton_info),
 466         INTEL_GLK_IDS(&intel_geminilake_info),
 467         INTEL_KBL_GT1_IDS(&intel_kabylake_info),
 468         INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 469         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 470         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 471         {0, 0, 0}
 472 };
 473 MODULE_DEVICE_TABLE(pci, pciidlist);
 474
 475 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 476 {
 477         struct intel_device_info *intel_info =
 478                 (struct intel_device_info *) ent->driver_data;
 479
 480         if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
 481                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 482                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 483                          "to enable support in this kernel version, or check for kernel updates.\n");
 484                 return -ENODEV;
 485         }
 486
 487         /* Only bind to function 0 of the device. Early generations
 488          * used function 1 as a placeholder for multi-head. This causes
 489          * us confusion instead, especially on the systems where both
 490          * functions have the same PCI-ID!
 491          */
 492         if (PCI_FUNC(pdev->devfn))
 493                 return -ENODEV;
 494
 495         /*
 496          * apple-gmux is needed on dual GPU MacBook Pro
 497          * to probe the panel if we're the inactive GPU.
 498          */
 499         if (vga_switcheroo_client_probe_defer(pdev))
 500                 return -EPROBE_DEFER;
 501
 502         return i915_driver_load(pdev, ent);
 503 }
 504
 505 static void i915_pci_remove(struct pci_dev *pdev)
 506 {
 507         struct drm_device *dev = pci_get_drvdata(pdev);
 508
 509         i915_driver_unload(dev);
 510         drm_dev_unref(dev);
 511 }
 512
 513 static struct pci_driver i915_pci_driver = {
 514         .name = DRIVER_NAME,
 515         .id_table = pciidlist,
 516         .probe = i915_pci_probe,
 517         .remove = i915_pci_remove,
 518         .driver.pm = &i915_pm_ops,
 519 };
 520
 521 static int __init i915_init(void)
 522 {
 523         bool use_kms = true;
 524
 525         /*
 526          * Enable KMS by default, unless explicitly overriden by
 527          * either the i915.modeset prarameter or by the
 528          * vga_text_mode_force boot option.
 529          */
 530
 531         if (i915.modeset == 0)
 532                 use_kms = false;
 533
 534         if (vgacon_text_force() && i915.modeset == -1)
 535                 use_kms = false;
 536
 537         if (!use_kms) {
 538                 /* Silently fail loading to not upset userspace. */
 539                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 540                 return 0;
 541         }
 542
 543         return pci_register_driver(&i915_pci_driver);
 544 }
 545
 546 static void __exit i915_exit(void)
 547 {
 548         if (!i915_pci_driver.driver.owner)
 549                 return;
 550
 551         pci_unregister_driver(&i915_pci_driver);
 552 }
 553
 554 module_init(i915_init);
 555 module_exit(i915_exit);
 556
 557 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 558 MODULE_AUTHOR("Intel Corporation");
 559
 560 MODULE_DESCRIPTION(DRIVER_DESC);
 561 MODULE_LICENSE("GPL and additional rights");