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drm/exynos: Stop using drm_framebuffer_unregister_private
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_dp.c
blobe80d620846c8310fc88bbb0ac07a66e5a820ff87
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include "i915_drv.h"
41
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
50 struct dp_link_dpll {
51 int clock;
52 struct dpll dpll;
53 };
54
55 static const struct dp_link_dpll gen4_dpll[] = {
56 { 162000,
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
58 { 270000,
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60 };
61
62 static const struct dp_link_dpll pch_dpll[] = {
63 { 162000,
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
65 { 270000,
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67 };
68
69 static const struct dp_link_dpll vlv_dpll[] = {
70 { 162000,
71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
72 { 270000,
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74 };
75
76 /*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80 static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92 };
93
94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates[] = { 162000, 270000, 540000 };
99
100 /**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107 static bool is_edp(struct intel_dp *intel_dp)
108 {
109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
112 }
113
114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
115 {
116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
119 }
120
121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122 {
123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
124 }
125
126 static void intel_dp_link_down(struct intel_dp *intel_dp);
127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
130 static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
133
134 static int
135 intel_dp_max_link_bw(struct intel_dp *intel_dp)
136 {
137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
142 case DP_LINK_BW_5_4:
143 break;
144 default:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151 }
152
153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154 {
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
156 u8 source_max, sink_max;
157
158 source_max = intel_dig_port->max_lanes;
159 sink_max = intel_dp->max_sink_lane_count;
160
161 return min(source_max, sink_max);
162 }
163
164 int
165 intel_dp_link_required(int pixel_clock, int bpp)
166 {
167 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
168 return DIV_ROUND_UP(pixel_clock * bpp, 8);
169 }
170
171 int
172 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
173 {
174 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
175 * link rate that is generally expressed in Gbps. Since, 8 bits of data
176 * is transmitted every LS_Clk per lane, there is no need to account for
177 * the channel encoding that is done in the PHY layer here.
178 */
179
180 return max_link_clock * max_lanes;
181 }
182
183 static int
184 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
185 {
186 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
187 struct intel_encoder *encoder = &intel_dig_port->base;
188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
189 int max_dotclk = dev_priv->max_dotclk_freq;
190 int ds_max_dotclk;
191
192 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
193
194 if (type != DP_DS_PORT_TYPE_VGA)
195 return max_dotclk;
196
197 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
198 intel_dp->downstream_ports);
199
200 if (ds_max_dotclk != 0)
201 max_dotclk = min(max_dotclk, ds_max_dotclk);
202
203 return max_dotclk;
204 }
205
206 static int
207 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
208 {
209 if (intel_dp->num_sink_rates) {
210 *sink_rates = intel_dp->sink_rates;
211 return intel_dp->num_sink_rates;
212 }
213
214 *sink_rates = default_rates;
215
216 return (intel_dp->max_sink_link_bw >> 3) + 1;
217 }
218
219 static int
220 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
221 {
222 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
223 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
224 int size;
225
226 if (IS_GEN9_LP(dev_priv)) {
227 *source_rates = bxt_rates;
228 size = ARRAY_SIZE(bxt_rates);
229 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
230 *source_rates = skl_rates;
231 size = ARRAY_SIZE(skl_rates);
232 } else {
233 *source_rates = default_rates;
234 size = ARRAY_SIZE(default_rates);
235 }
236
237 /* This depends on the fact that 5.4 is last value in the array */
238 if (!intel_dp_source_supports_hbr2(intel_dp))
239 size--;
240
241 return size;
242 }
243
244 static int intersect_rates(const int *source_rates, int source_len,
245 const int *sink_rates, int sink_len,
246 int *common_rates)
247 {
248 int i = 0, j = 0, k = 0;
249
250 while (i < source_len && j < sink_len) {
251 if (source_rates[i] == sink_rates[j]) {
252 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
253 return k;
254 common_rates[k] = source_rates[i];
255 ++k;
256 ++i;
257 ++j;
258 } else if (source_rates[i] < sink_rates[j]) {
259 ++i;
260 } else {
261 ++j;
262 }
263 }
264 return k;
265 }
266
267 static int intel_dp_common_rates(struct intel_dp *intel_dp,
268 int *common_rates)
269 {
270 const int *source_rates, *sink_rates;
271 int source_len, sink_len;
272
273 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
274 source_len = intel_dp_source_rates(intel_dp, &source_rates);
275
276 return intersect_rates(source_rates, source_len,
277 sink_rates, sink_len,
278 common_rates);
279 }
280
281 static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
282 int *common_rates, int link_rate)
283 {
284 int common_len;
285 int index;
286
287 common_len = intel_dp_common_rates(intel_dp, common_rates);
288 for (index = 0; index < common_len; index++) {
289 if (link_rate == common_rates[common_len - index - 1])
290 return common_len - index - 1;
291 }
292
293 return -1;
294 }
295
296 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
297 int link_rate, uint8_t lane_count)
298 {
299 int common_rates[DP_MAX_SUPPORTED_RATES];
300 int link_rate_index;
301
302 link_rate_index = intel_dp_link_rate_index(intel_dp,
303 common_rates,
304 link_rate);
305 if (link_rate_index > 0) {
306 intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]);
307 intel_dp->max_sink_lane_count = lane_count;
308 } else if (lane_count > 1) {
309 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
310 intel_dp->max_sink_lane_count = lane_count >> 1;
311 } else {
312 DRM_ERROR("Link Training Unsuccessful\n");
313 return -1;
314 }
315
316 return 0;
317 }
318
319 static enum drm_mode_status
320 intel_dp_mode_valid(struct drm_connector *connector,
321 struct drm_display_mode *mode)
322 {
323 struct intel_dp *intel_dp = intel_attached_dp(connector);
324 struct intel_connector *intel_connector = to_intel_connector(connector);
325 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
326 int target_clock = mode->clock;
327 int max_rate, mode_rate, max_lanes, max_link_clock;
328 int max_dotclk;
329
330 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
331
332 if (is_edp(intel_dp) && fixed_mode) {
333 if (mode->hdisplay > fixed_mode->hdisplay)
334 return MODE_PANEL;
335
336 if (mode->vdisplay > fixed_mode->vdisplay)
337 return MODE_PANEL;
338
339 target_clock = fixed_mode->clock;
340 }
341
342 max_link_clock = intel_dp_max_link_rate(intel_dp);
343 max_lanes = intel_dp_max_lane_count(intel_dp);
344
345 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
346 mode_rate = intel_dp_link_required(target_clock, 18);
347
348 if (mode_rate > max_rate || target_clock > max_dotclk)
349 return MODE_CLOCK_HIGH;
350
351 if (mode->clock < 10000)
352 return MODE_CLOCK_LOW;
353
354 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
355 return MODE_H_ILLEGAL;
356
357 return MODE_OK;
358 }
359
360 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
361 {
362 int i;
363 uint32_t v = 0;
364
365 if (src_bytes > 4)
366 src_bytes = 4;
367 for (i = 0; i < src_bytes; i++)
368 v |= ((uint32_t) src[i]) << ((3-i) * 8);
369 return v;
370 }
371
372 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
373 {
374 int i;
375 if (dst_bytes > 4)
376 dst_bytes = 4;
377 for (i = 0; i < dst_bytes; i++)
378 dst[i] = src >> ((3-i) * 8);
379 }
380
381 static void
382 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
383 struct intel_dp *intel_dp);
384 static void
385 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
386 struct intel_dp *intel_dp,
387 bool force_disable_vdd);
388 static void
389 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
390
391 static void pps_lock(struct intel_dp *intel_dp)
392 {
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
394 struct intel_encoder *encoder = &intel_dig_port->base;
395 struct drm_device *dev = encoder->base.dev;
396 struct drm_i915_private *dev_priv = to_i915(dev);
397 enum intel_display_power_domain power_domain;
398
399 /*
400 * See vlv_power_sequencer_reset() why we need
401 * a power domain reference here.
402 */
403 power_domain = intel_display_port_aux_power_domain(encoder);
404 intel_display_power_get(dev_priv, power_domain);
405
406 mutex_lock(&dev_priv->pps_mutex);
407 }
408
409 static void pps_unlock(struct intel_dp *intel_dp)
410 {
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct intel_encoder *encoder = &intel_dig_port->base;
413 struct drm_device *dev = encoder->base.dev;
414 struct drm_i915_private *dev_priv = to_i915(dev);
415 enum intel_display_power_domain power_domain;
416
417 mutex_unlock(&dev_priv->pps_mutex);
418
419 power_domain = intel_display_port_aux_power_domain(encoder);
420 intel_display_power_put(dev_priv, power_domain);
421 }
422
423 static void
424 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
425 {
426 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
427 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
428 enum pipe pipe = intel_dp->pps_pipe;
429 bool pll_enabled, release_cl_override = false;
430 enum dpio_phy phy = DPIO_PHY(pipe);
431 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
432 uint32_t DP;
433
434 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
435 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
436 pipe_name(pipe), port_name(intel_dig_port->port)))
437 return;
438
439 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
440 pipe_name(pipe), port_name(intel_dig_port->port));
441
442 /* Preserve the BIOS-computed detected bit. This is
443 * supposed to be read-only.
444 */
445 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
446 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
447 DP |= DP_PORT_WIDTH(1);
448 DP |= DP_LINK_TRAIN_PAT_1;
449
450 if (IS_CHERRYVIEW(dev_priv))
451 DP |= DP_PIPE_SELECT_CHV(pipe);
452 else if (pipe == PIPE_B)
453 DP |= DP_PIPEB_SELECT;
454
455 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
456
457 /*
458 * The DPLL for the pipe must be enabled for this to work.
459 * So enable temporarily it if it's not already enabled.
460 */
461 if (!pll_enabled) {
462 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
463 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
464
465 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
466 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
467 DRM_ERROR("Failed to force on pll for pipe %c!\n",
468 pipe_name(pipe));
469 return;
470 }
471 }
472
473 /*
474 * Similar magic as in intel_dp_enable_port().
475 * We _must_ do this port enable + disable trick
476 * to make this power seqeuencer lock onto the port.
477 * Otherwise even VDD force bit won't work.
478 */
479 I915_WRITE(intel_dp->output_reg, DP);
480 POSTING_READ(intel_dp->output_reg);
481
482 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
483 POSTING_READ(intel_dp->output_reg);
484
485 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
486 POSTING_READ(intel_dp->output_reg);
487
488 if (!pll_enabled) {
489 vlv_force_pll_off(dev_priv, pipe);
490
491 if (release_cl_override)
492 chv_phy_powergate_ch(dev_priv, phy, ch, false);
493 }
494 }
495
496 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
497 {
498 struct intel_encoder *encoder;
499 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
500
501 /*
502 * We don't have power sequencer currently.
503 * Pick one that's not used by other ports.
504 */
505 for_each_intel_encoder(&dev_priv->drm, encoder) {
506 struct intel_dp *intel_dp;
507
508 if (encoder->type != INTEL_OUTPUT_DP &&
509 encoder->type != INTEL_OUTPUT_EDP)
510 continue;
511
512 intel_dp = enc_to_intel_dp(&encoder->base);
513
514 if (encoder->type == INTEL_OUTPUT_EDP) {
515 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
516 intel_dp->active_pipe != intel_dp->pps_pipe);
517
518 if (intel_dp->pps_pipe != INVALID_PIPE)
519 pipes &= ~(1 << intel_dp->pps_pipe);
520 } else {
521 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
522
523 if (intel_dp->active_pipe != INVALID_PIPE)
524 pipes &= ~(1 << intel_dp->active_pipe);
525 }
526 }
527
528 if (pipes == 0)
529 return INVALID_PIPE;
530
531 return ffs(pipes) - 1;
532 }
533
534 static enum pipe
535 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
536 {
537 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
538 struct drm_device *dev = intel_dig_port->base.base.dev;
539 struct drm_i915_private *dev_priv = to_i915(dev);
540 enum pipe pipe;
541
542 lockdep_assert_held(&dev_priv->pps_mutex);
543
544 /* We should never land here with regular DP ports */
545 WARN_ON(!is_edp(intel_dp));
546
547 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
548 intel_dp->active_pipe != intel_dp->pps_pipe);
549
550 if (intel_dp->pps_pipe != INVALID_PIPE)
551 return intel_dp->pps_pipe;
552
553 pipe = vlv_find_free_pps(dev_priv);
554
555 /*
556 * Didn't find one. This should not happen since there
557 * are two power sequencers and up to two eDP ports.
558 */
559 if (WARN_ON(pipe == INVALID_PIPE))
560 pipe = PIPE_A;
561
562 vlv_steal_power_sequencer(dev, pipe);
563 intel_dp->pps_pipe = pipe;
564
565 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
566 pipe_name(intel_dp->pps_pipe),
567 port_name(intel_dig_port->port));
568
569 /* init power sequencer on this pipe and port */
570 intel_dp_init_panel_power_sequencer(dev, intel_dp);
571 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
572
573 /*
574 * Even vdd force doesn't work until we've made
575 * the power sequencer lock in on the port.
576 */
577 vlv_power_sequencer_kick(intel_dp);
578
579 return intel_dp->pps_pipe;
580 }
581
582 static int
583 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
584 {
585 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
586 struct drm_device *dev = intel_dig_port->base.base.dev;
587 struct drm_i915_private *dev_priv = to_i915(dev);
588
589 lockdep_assert_held(&dev_priv->pps_mutex);
590
591 /* We should never land here with regular DP ports */
592 WARN_ON(!is_edp(intel_dp));
593
594 /*
595 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
596 * mapping needs to be retrieved from VBT, for now just hard-code to
597 * use instance #0 always.
598 */
599 if (!intel_dp->pps_reset)
600 return 0;
601
602 intel_dp->pps_reset = false;
603
604 /*
605 * Only the HW needs to be reprogrammed, the SW state is fixed and
606 * has been setup during connector init.
607 */
608 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
609
610 return 0;
611 }
612
613 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
614 enum pipe pipe);
615
616 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
617 enum pipe pipe)
618 {
619 return I915_READ(PP_STATUS(pipe)) & PP_ON;
620 }
621
622 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
623 enum pipe pipe)
624 {
625 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
626 }
627
628 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
629 enum pipe pipe)
630 {
631 return true;
632 }
633
634 static enum pipe
635 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
636 enum port port,
637 vlv_pipe_check pipe_check)
638 {
639 enum pipe pipe;
640
641 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
642 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
643 PANEL_PORT_SELECT_MASK;
644
645 if (port_sel != PANEL_PORT_SELECT_VLV(port))
646 continue;
647
648 if (!pipe_check(dev_priv, pipe))
649 continue;
650
651 return pipe;
652 }
653
654 return INVALID_PIPE;
655 }
656
657 static void
658 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
659 {
660 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
661 struct drm_device *dev = intel_dig_port->base.base.dev;
662 struct drm_i915_private *dev_priv = to_i915(dev);
663 enum port port = intel_dig_port->port;
664
665 lockdep_assert_held(&dev_priv->pps_mutex);
666
667 /* try to find a pipe with this port selected */
668 /* first pick one where the panel is on */
669 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
670 vlv_pipe_has_pp_on);
671 /* didn't find one? pick one where vdd is on */
672 if (intel_dp->pps_pipe == INVALID_PIPE)
673 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
674 vlv_pipe_has_vdd_on);
675 /* didn't find one? pick one with just the correct port */
676 if (intel_dp->pps_pipe == INVALID_PIPE)
677 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
678 vlv_pipe_any);
679
680 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
681 if (intel_dp->pps_pipe == INVALID_PIPE) {
682 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
683 port_name(port));
684 return;
685 }
686
687 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
688 port_name(port), pipe_name(intel_dp->pps_pipe));
689
690 intel_dp_init_panel_power_sequencer(dev, intel_dp);
691 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
692 }
693
694 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
695 {
696 struct drm_device *dev = &dev_priv->drm;
697 struct intel_encoder *encoder;
698
699 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
700 !IS_GEN9_LP(dev_priv)))
701 return;
702
703 /*
704 * We can't grab pps_mutex here due to deadlock with power_domain
705 * mutex when power_domain functions are called while holding pps_mutex.
706 * That also means that in order to use pps_pipe the code needs to
707 * hold both a power domain reference and pps_mutex, and the power domain
708 * reference get/put must be done while _not_ holding pps_mutex.
709 * pps_{lock,unlock}() do these steps in the correct order, so one
710 * should use them always.
711 */
712
713 for_each_intel_encoder(dev, encoder) {
714 struct intel_dp *intel_dp;
715
716 if (encoder->type != INTEL_OUTPUT_DP &&
717 encoder->type != INTEL_OUTPUT_EDP)
718 continue;
719
720 intel_dp = enc_to_intel_dp(&encoder->base);
721
722 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
723
724 if (encoder->type != INTEL_OUTPUT_EDP)
725 continue;
726
727 if (IS_GEN9_LP(dev_priv))
728 intel_dp->pps_reset = true;
729 else
730 intel_dp->pps_pipe = INVALID_PIPE;
731 }
732 }
733
734 struct pps_registers {
735 i915_reg_t pp_ctrl;
736 i915_reg_t pp_stat;
737 i915_reg_t pp_on;
738 i915_reg_t pp_off;
739 i915_reg_t pp_div;
740 };
741
742 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
743 struct intel_dp *intel_dp,
744 struct pps_registers *regs)
745 {
746 int pps_idx = 0;
747
748 memset(regs, 0, sizeof(*regs));
749
750 if (IS_GEN9_LP(dev_priv))
751 pps_idx = bxt_power_sequencer_idx(intel_dp);
752 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
753 pps_idx = vlv_power_sequencer_pipe(intel_dp);
754
755 regs->pp_ctrl = PP_CONTROL(pps_idx);
756 regs->pp_stat = PP_STATUS(pps_idx);
757 regs->pp_on = PP_ON_DELAYS(pps_idx);
758 regs->pp_off = PP_OFF_DELAYS(pps_idx);
759 if (!IS_GEN9_LP(dev_priv))
760 regs->pp_div = PP_DIVISOR(pps_idx);
761 }
762
763 static i915_reg_t
764 _pp_ctrl_reg(struct intel_dp *intel_dp)
765 {
766 struct pps_registers regs;
767
768 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
769 &regs);
770
771 return regs.pp_ctrl;
772 }
773
774 static i915_reg_t
775 _pp_stat_reg(struct intel_dp *intel_dp)
776 {
777 struct pps_registers regs;
778
779 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
780 &regs);
781
782 return regs.pp_stat;
783 }
784
785 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
786 This function only applicable when panel PM state is not to be tracked */
787 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
788 void *unused)
789 {
790 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
791 edp_notifier);
792 struct drm_device *dev = intel_dp_to_dev(intel_dp);
793 struct drm_i915_private *dev_priv = to_i915(dev);
794
795 if (!is_edp(intel_dp) || code != SYS_RESTART)
796 return 0;
797
798 pps_lock(intel_dp);
799
800 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
801 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
802 i915_reg_t pp_ctrl_reg, pp_div_reg;
803 u32 pp_div;
804
805 pp_ctrl_reg = PP_CONTROL(pipe);
806 pp_div_reg = PP_DIVISOR(pipe);
807 pp_div = I915_READ(pp_div_reg);
808 pp_div &= PP_REFERENCE_DIVIDER_MASK;
809
810 /* 0x1F write to PP_DIV_REG sets max cycle delay */
811 I915_WRITE(pp_div_reg, pp_div | 0x1F);
812 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
813 msleep(intel_dp->panel_power_cycle_delay);
814 }
815
816 pps_unlock(intel_dp);
817
818 return 0;
819 }
820
821 static bool edp_have_panel_power(struct intel_dp *intel_dp)
822 {
823 struct drm_device *dev = intel_dp_to_dev(intel_dp);
824 struct drm_i915_private *dev_priv = to_i915(dev);
825
826 lockdep_assert_held(&dev_priv->pps_mutex);
827
828 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
829 intel_dp->pps_pipe == INVALID_PIPE)
830 return false;
831
832 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
833 }
834
835 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
836 {
837 struct drm_device *dev = intel_dp_to_dev(intel_dp);
838 struct drm_i915_private *dev_priv = to_i915(dev);
839
840 lockdep_assert_held(&dev_priv->pps_mutex);
841
842 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
843 intel_dp->pps_pipe == INVALID_PIPE)
844 return false;
845
846 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
847 }
848
849 static void
850 intel_dp_check_edp(struct intel_dp *intel_dp)
851 {
852 struct drm_device *dev = intel_dp_to_dev(intel_dp);
853 struct drm_i915_private *dev_priv = to_i915(dev);
854
855 if (!is_edp(intel_dp))
856 return;
857
858 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
859 WARN(1, "eDP powered off while attempting aux channel communication.\n");
860 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
861 I915_READ(_pp_stat_reg(intel_dp)),
862 I915_READ(_pp_ctrl_reg(intel_dp)));
863 }
864 }
865
866 static uint32_t
867 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
868 {
869 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
870 struct drm_device *dev = intel_dig_port->base.base.dev;
871 struct drm_i915_private *dev_priv = to_i915(dev);
872 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
873 uint32_t status;
874 bool done;
875
876 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
877 if (has_aux_irq)
878 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
879 msecs_to_jiffies_timeout(10));
880 else
881 done = wait_for(C, 10) == 0;
882 if (!done)
883 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
884 has_aux_irq);
885 #undef C
886
887 return status;
888 }
889
890 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
891 {
892 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
893 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
894
895 if (index)
896 return 0;
897
898 /*
899 * The clock divider is based off the hrawclk, and would like to run at
900 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
901 */
902 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
903 }
904
905 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
906 {
907 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
908 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
909
910 if (index)
911 return 0;
912
913 /*
914 * The clock divider is based off the cdclk or PCH rawclk, and would
915 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
916 * divide by 2000 and use that
917 */
918 if (intel_dig_port->port == PORT_A)
919 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
920 else
921 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
922 }
923
924 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
925 {
926 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
927 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
928
929 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
930 /* Workaround for non-ULT HSW */
931 switch (index) {
932 case 0: return 63;
933 case 1: return 72;
934 default: return 0;
935 }
936 }
937
938 return ilk_get_aux_clock_divider(intel_dp, index);
939 }
940
941 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
942 {
943 /*
944 * SKL doesn't need us to program the AUX clock divider (Hardware will
945 * derive the clock from CDCLK automatically). We still implement the
946 * get_aux_clock_divider vfunc to plug-in into the existing code.
947 */
948 return index ? 0 : 1;
949 }
950
951 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
952 bool has_aux_irq,
953 int send_bytes,
954 uint32_t aux_clock_divider)
955 {
956 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
957 struct drm_i915_private *dev_priv =
958 to_i915(intel_dig_port->base.base.dev);
959 uint32_t precharge, timeout;
960
961 if (IS_GEN6(dev_priv))
962 precharge = 3;
963 else
964 precharge = 5;
965
966 if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
967 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
968 else
969 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
970
971 return DP_AUX_CH_CTL_SEND_BUSY |
972 DP_AUX_CH_CTL_DONE |
973 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
974 DP_AUX_CH_CTL_TIME_OUT_ERROR |
975 timeout |
976 DP_AUX_CH_CTL_RECEIVE_ERROR |
977 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
978 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
979 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
980 }
981
982 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
983 bool has_aux_irq,
984 int send_bytes,
985 uint32_t unused)
986 {
987 return DP_AUX_CH_CTL_SEND_BUSY |
988 DP_AUX_CH_CTL_DONE |
989 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
990 DP_AUX_CH_CTL_TIME_OUT_ERROR |
991 DP_AUX_CH_CTL_TIME_OUT_1600us |
992 DP_AUX_CH_CTL_RECEIVE_ERROR |
993 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
994 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
995 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
996 }
997
998 static int
999 intel_dp_aux_ch(struct intel_dp *intel_dp,
1000 const uint8_t *send, int send_bytes,
1001 uint8_t *recv, int recv_size)
1002 {
1003 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1004 struct drm_i915_private *dev_priv =
1005 to_i915(intel_dig_port->base.base.dev);
1006 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1007 uint32_t aux_clock_divider;
1008 int i, ret, recv_bytes;
1009 uint32_t status;
1010 int try, clock = 0;
1011 bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1012 bool vdd;
1013
1014 pps_lock(intel_dp);
1015
1016 /*
1017 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1018 * In such cases we want to leave VDD enabled and it's up to upper layers
1019 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1020 * ourselves.
1021 */
1022 vdd = edp_panel_vdd_on(intel_dp);
1023
1024 /* dp aux is extremely sensitive to irq latency, hence request the
1025 * lowest possible wakeup latency and so prevent the cpu from going into
1026 * deep sleep states.
1027 */
1028 pm_qos_update_request(&dev_priv->pm_qos, 0);
1029
1030 intel_dp_check_edp(intel_dp);
1031
1032 /* Try to wait for any previous AUX channel activity */
1033 for (try = 0; try < 3; try++) {
1034 status = I915_READ_NOTRACE(ch_ctl);
1035 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1036 break;
1037 msleep(1);
1038 }
1039
1040 if (try == 3) {
1041 static u32 last_status = -1;
1042 const u32 status = I915_READ(ch_ctl);
1043
1044 if (status != last_status) {
1045 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1046 status);
1047 last_status = status;
1048 }
1049
1050 ret = -EBUSY;
1051 goto out;
1052 }
1053
1054 /* Only 5 data registers! */
1055 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1056 ret = -E2BIG;
1057 goto out;
1058 }
1059
1060 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1061 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1062 has_aux_irq,
1063 send_bytes,
1064 aux_clock_divider);
1065
1066 /* Must try at least 3 times according to DP spec */
1067 for (try = 0; try < 5; try++) {
1068 /* Load the send data into the aux channel data registers */
1069 for (i = 0; i < send_bytes; i += 4)
1070 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1071 intel_dp_pack_aux(send + i,
1072 send_bytes - i));
1073
1074 /* Send the command and wait for it to complete */
1075 I915_WRITE(ch_ctl, send_ctl);
1076
1077 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1078
1079 /* Clear done status and any errors */
1080 I915_WRITE(ch_ctl,
1081 status |
1082 DP_AUX_CH_CTL_DONE |
1083 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1084 DP_AUX_CH_CTL_RECEIVE_ERROR);
1085
1086 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1087 continue;
1088
1089 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1090 * 400us delay required for errors and timeouts
1091 * Timeout errors from the HW already meet this
1092 * requirement so skip to next iteration
1093 */
1094 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1095 usleep_range(400, 500);
1096 continue;
1097 }
1098 if (status & DP_AUX_CH_CTL_DONE)
1099 goto done;
1100 }
1101 }
1102
1103 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1104 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1105 ret = -EBUSY;
1106 goto out;
1107 }
1108
1109 done:
1110 /* Check for timeout or receive error.
1111 * Timeouts occur when the sink is not connected
1112 */
1113 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1114 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1115 ret = -EIO;
1116 goto out;
1117 }
1118
1119 /* Timeouts occur when the device isn't connected, so they're
1120 * "normal" -- don't fill the kernel log with these */
1121 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1122 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1123 ret = -ETIMEDOUT;
1124 goto out;
1125 }
1126
1127 /* Unload any bytes sent back from the other side */
1128 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1129 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1130
1131 /*
1132 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1133 * We have no idea of what happened so we return -EBUSY so
1134 * drm layer takes care for the necessary retries.
1135 */
1136 if (recv_bytes == 0 || recv_bytes > 20) {
1137 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1138 recv_bytes);
1139 /*
1140 * FIXME: This patch was created on top of a series that
1141 * organize the retries at drm level. There EBUSY should
1142 * also take care for 1ms wait before retrying.
1143 * That aux retries re-org is still needed and after that is
1144 * merged we remove this sleep from here.
1145 */
1146 usleep_range(1000, 1500);
1147 ret = -EBUSY;
1148 goto out;
1149 }
1150
1151 if (recv_bytes > recv_size)
1152 recv_bytes = recv_size;
1153
1154 for (i = 0; i < recv_bytes; i += 4)
1155 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1156 recv + i, recv_bytes - i);
1157
1158 ret = recv_bytes;
1159 out:
1160 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1161
1162 if (vdd)
1163 edp_panel_vdd_off(intel_dp, false);
1164
1165 pps_unlock(intel_dp);
1166
1167 return ret;
1168 }
1169
1170 #define BARE_ADDRESS_SIZE 3
1171 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1172 static ssize_t
1173 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1174 {
1175 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1176 uint8_t txbuf[20], rxbuf[20];
1177 size_t txsize, rxsize;
1178 int ret;
1179
1180 txbuf[0] = (msg->request << 4) |
1181 ((msg->address >> 16) & 0xf);
1182 txbuf[1] = (msg->address >> 8) & 0xff;
1183 txbuf[2] = msg->address & 0xff;
1184 txbuf[3] = msg->size - 1;
1185
1186 switch (msg->request & ~DP_AUX_I2C_MOT) {
1187 case DP_AUX_NATIVE_WRITE:
1188 case DP_AUX_I2C_WRITE:
1189 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1190 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1191 rxsize = 2; /* 0 or 1 data bytes */
1192
1193 if (WARN_ON(txsize > 20))
1194 return -E2BIG;
1195
1196 WARN_ON(!msg->buffer != !msg->size);
1197
1198 if (msg->buffer)
1199 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1200
1201 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1202 if (ret > 0) {
1203 msg->reply = rxbuf[0] >> 4;
1204
1205 if (ret > 1) {
1206 /* Number of bytes written in a short write. */
1207 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1208 } else {
1209 /* Return payload size. */
1210 ret = msg->size;
1211 }
1212 }
1213 break;
1214
1215 case DP_AUX_NATIVE_READ:
1216 case DP_AUX_I2C_READ:
1217 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1218 rxsize = msg->size + 1;
1219
1220 if (WARN_ON(rxsize > 20))
1221 return -E2BIG;
1222
1223 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1224 if (ret > 0) {
1225 msg->reply = rxbuf[0] >> 4;
1226 /*
1227 * Assume happy day, and copy the data. The caller is
1228 * expected to check msg->reply before touching it.
1229 *
1230 * Return payload size.
1231 */
1232 ret--;
1233 memcpy(msg->buffer, rxbuf + 1, ret);
1234 }
1235 break;
1236
1237 default:
1238 ret = -EINVAL;
1239 break;
1240 }
1241
1242 return ret;
1243 }
1244
1245 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1246 enum port port)
1247 {
1248 const struct ddi_vbt_port_info *info =
1249 &dev_priv->vbt.ddi_port_info[port];
1250 enum port aux_port;
1251
1252 if (!info->alternate_aux_channel) {
1253 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1254 port_name(port), port_name(port));
1255 return port;
1256 }
1257
1258 switch (info->alternate_aux_channel) {
1259 case DP_AUX_A:
1260 aux_port = PORT_A;
1261 break;
1262 case DP_AUX_B:
1263 aux_port = PORT_B;
1264 break;
1265 case DP_AUX_C:
1266 aux_port = PORT_C;
1267 break;
1268 case DP_AUX_D:
1269 aux_port = PORT_D;
1270 break;
1271 default:
1272 MISSING_CASE(info->alternate_aux_channel);
1273 aux_port = PORT_A;
1274 break;
1275 }
1276
1277 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1278 port_name(aux_port), port_name(port));
1279
1280 return aux_port;
1281 }
1282
1283 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1284 enum port port)
1285 {
1286 switch (port) {
1287 case PORT_B:
1288 case PORT_C:
1289 case PORT_D:
1290 return DP_AUX_CH_CTL(port);
1291 default:
1292 MISSING_CASE(port);
1293 return DP_AUX_CH_CTL(PORT_B);
1294 }
1295 }
1296
1297 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1298 enum port port, int index)
1299 {
1300 switch (port) {
1301 case PORT_B:
1302 case PORT_C:
1303 case PORT_D:
1304 return DP_AUX_CH_DATA(port, index);
1305 default:
1306 MISSING_CASE(port);
1307 return DP_AUX_CH_DATA(PORT_B, index);
1308 }
1309 }
1310
1311 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1312 enum port port)
1313 {
1314 switch (port) {
1315 case PORT_A:
1316 return DP_AUX_CH_CTL(port);
1317 case PORT_B:
1318 case PORT_C:
1319 case PORT_D:
1320 return PCH_DP_AUX_CH_CTL(port);
1321 default:
1322 MISSING_CASE(port);
1323 return DP_AUX_CH_CTL(PORT_A);
1324 }
1325 }
1326
1327 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1328 enum port port, int index)
1329 {
1330 switch (port) {
1331 case PORT_A:
1332 return DP_AUX_CH_DATA(port, index);
1333 case PORT_B:
1334 case PORT_C:
1335 case PORT_D:
1336 return PCH_DP_AUX_CH_DATA(port, index);
1337 default:
1338 MISSING_CASE(port);
1339 return DP_AUX_CH_DATA(PORT_A, index);
1340 }
1341 }
1342
1343 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1344 enum port port)
1345 {
1346 switch (port) {
1347 case PORT_A:
1348 case PORT_B:
1349 case PORT_C:
1350 case PORT_D:
1351 return DP_AUX_CH_CTL(port);
1352 default:
1353 MISSING_CASE(port);
1354 return DP_AUX_CH_CTL(PORT_A);
1355 }
1356 }
1357
1358 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1359 enum port port, int index)
1360 {
1361 switch (port) {
1362 case PORT_A:
1363 case PORT_B:
1364 case PORT_C:
1365 case PORT_D:
1366 return DP_AUX_CH_DATA(port, index);
1367 default:
1368 MISSING_CASE(port);
1369 return DP_AUX_CH_DATA(PORT_A, index);
1370 }
1371 }
1372
1373 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1374 enum port port)
1375 {
1376 if (INTEL_INFO(dev_priv)->gen >= 9)
1377 return skl_aux_ctl_reg(dev_priv, port);
1378 else if (HAS_PCH_SPLIT(dev_priv))
1379 return ilk_aux_ctl_reg(dev_priv, port);
1380 else
1381 return g4x_aux_ctl_reg(dev_priv, port);
1382 }
1383
1384 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1385 enum port port, int index)
1386 {
1387 if (INTEL_INFO(dev_priv)->gen >= 9)
1388 return skl_aux_data_reg(dev_priv, port, index);
1389 else if (HAS_PCH_SPLIT(dev_priv))
1390 return ilk_aux_data_reg(dev_priv, port, index);
1391 else
1392 return g4x_aux_data_reg(dev_priv, port, index);
1393 }
1394
1395 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1396 {
1397 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1398 enum port port = intel_aux_port(dev_priv,
1399 dp_to_dig_port(intel_dp)->port);
1400 int i;
1401
1402 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1403 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1404 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1405 }
1406
1407 static void
1408 intel_dp_aux_fini(struct intel_dp *intel_dp)
1409 {
1410 kfree(intel_dp->aux.name);
1411 }
1412
1413 static void
1414 intel_dp_aux_init(struct intel_dp *intel_dp)
1415 {
1416 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1417 enum port port = intel_dig_port->port;
1418
1419 intel_aux_reg_init(intel_dp);
1420 drm_dp_aux_init(&intel_dp->aux);
1421
1422 /* Failure to allocate our preferred name is not critical */
1423 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1424 intel_dp->aux.transfer = intel_dp_aux_transfer;
1425 }
1426
1427 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1428 {
1429 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1430 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1431
1432 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1433 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1434 return true;
1435 else
1436 return false;
1437 }
1438
1439 static void
1440 intel_dp_set_clock(struct intel_encoder *encoder,
1441 struct intel_crtc_state *pipe_config)
1442 {
1443 struct drm_device *dev = encoder->base.dev;
1444 struct drm_i915_private *dev_priv = to_i915(dev);
1445 const struct dp_link_dpll *divisor = NULL;
1446 int i, count = 0;
1447
1448 if (IS_G4X(dev_priv)) {
1449 divisor = gen4_dpll;
1450 count = ARRAY_SIZE(gen4_dpll);
1451 } else if (HAS_PCH_SPLIT(dev_priv)) {
1452 divisor = pch_dpll;
1453 count = ARRAY_SIZE(pch_dpll);
1454 } else if (IS_CHERRYVIEW(dev_priv)) {
1455 divisor = chv_dpll;
1456 count = ARRAY_SIZE(chv_dpll);
1457 } else if (IS_VALLEYVIEW(dev_priv)) {
1458 divisor = vlv_dpll;
1459 count = ARRAY_SIZE(vlv_dpll);
1460 }
1461
1462 if (divisor && count) {
1463 for (i = 0; i < count; i++) {
1464 if (pipe_config->port_clock == divisor[i].clock) {
1465 pipe_config->dpll = divisor[i].dpll;
1466 pipe_config->clock_set = true;
1467 break;
1468 }
1469 }
1470 }
1471 }
1472
1473 static void snprintf_int_array(char *str, size_t len,
1474 const int *array, int nelem)
1475 {
1476 int i;
1477
1478 str[0] = '\0';
1479
1480 for (i = 0; i < nelem; i++) {
1481 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1482 if (r >= len)
1483 return;
1484 str += r;
1485 len -= r;
1486 }
1487 }
1488
1489 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1490 {
1491 const int *source_rates, *sink_rates;
1492 int source_len, sink_len, common_len;
1493 int common_rates[DP_MAX_SUPPORTED_RATES];
1494 char str[128]; /* FIXME: too big for stack? */
1495
1496 if ((drm_debug & DRM_UT_KMS) == 0)
1497 return;
1498
1499 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1500 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1501 DRM_DEBUG_KMS("source rates: %s\n", str);
1502
1503 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1504 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1505 DRM_DEBUG_KMS("sink rates: %s\n", str);
1506
1507 common_len = intel_dp_common_rates(intel_dp, common_rates);
1508 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1509 DRM_DEBUG_KMS("common rates: %s\n", str);
1510 }
1511
1512 bool
1513 __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
1514 {
1515 u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1516 DP_SINK_OUI;
1517
1518 return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1519 sizeof(*desc);
1520 }
1521
1522 bool intel_dp_read_desc(struct intel_dp *intel_dp)
1523 {
1524 struct intel_dp_desc *desc = &intel_dp->desc;
1525 bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1526 DP_OUI_SUPPORT;
1527 int dev_id_len;
1528
1529 if (!__intel_dp_read_desc(intel_dp, desc))
1530 return false;
1531
1532 dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1533 DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1534 drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1535 (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1536 dev_id_len, desc->device_id,
1537 desc->hw_rev >> 4, desc->hw_rev & 0xf,
1538 desc->sw_major_rev, desc->sw_minor_rev);
1539
1540 return true;
1541 }
1542
1543 static int rate_to_index(int find, const int *rates)
1544 {
1545 int i = 0;
1546
1547 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1548 if (find == rates[i])
1549 break;
1550
1551 return i;
1552 }
1553
1554 int
1555 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1556 {
1557 int rates[DP_MAX_SUPPORTED_RATES] = {};
1558 int len;
1559
1560 len = intel_dp_common_rates(intel_dp, rates);
1561 if (WARN_ON(len <= 0))
1562 return 162000;
1563
1564 return rates[len - 1];
1565 }
1566
1567 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1568 {
1569 return rate_to_index(rate, intel_dp->sink_rates);
1570 }
1571
1572 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1573 uint8_t *link_bw, uint8_t *rate_select)
1574 {
1575 if (intel_dp->num_sink_rates) {
1576 *link_bw = 0;
1577 *rate_select =
1578 intel_dp_rate_select(intel_dp, port_clock);
1579 } else {
1580 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1581 *rate_select = 0;
1582 }
1583 }
1584
1585 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1586 struct intel_crtc_state *pipe_config)
1587 {
1588 int bpp, bpc;
1589
1590 bpp = pipe_config->pipe_bpp;
1591 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1592
1593 if (bpc > 0)
1594 bpp = min(bpp, 3*bpc);
1595
1596 return bpp;
1597 }
1598
1599 bool
1600 intel_dp_compute_config(struct intel_encoder *encoder,
1601 struct intel_crtc_state *pipe_config,
1602 struct drm_connector_state *conn_state)
1603 {
1604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1605 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1606 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1607 enum port port = dp_to_dig_port(intel_dp)->port;
1608 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1609 struct intel_connector *intel_connector = intel_dp->attached_connector;
1610 int lane_count, clock;
1611 int min_lane_count = 1;
1612 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1613 /* Conveniently, the link BW constants become indices with a shift...*/
1614 int min_clock = 0;
1615 int max_clock;
1616 int bpp, mode_rate;
1617 int link_avail, link_clock;
1618 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1619 int common_len;
1620 uint8_t link_bw, rate_select;
1621
1622 common_len = intel_dp_common_rates(intel_dp, common_rates);
1623
1624 /* No common link rates between source and sink */
1625 WARN_ON(common_len <= 0);
1626
1627 max_clock = common_len - 1;
1628
1629 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1630 pipe_config->has_pch_encoder = true;
1631
1632 pipe_config->has_drrs = false;
1633 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1634
1635 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1636 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1637 adjusted_mode);
1638
1639 if (INTEL_GEN(dev_priv) >= 9) {
1640 int ret;
1641 ret = skl_update_scaler_crtc(pipe_config);
1642 if (ret)
1643 return ret;
1644 }
1645
1646 if (HAS_GMCH_DISPLAY(dev_priv))
1647 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1648 intel_connector->panel.fitting_mode);
1649 else
1650 intel_pch_panel_fitting(intel_crtc, pipe_config,
1651 intel_connector->panel.fitting_mode);
1652 }
1653
1654 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1655 return false;
1656
1657 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1658 "max bw %d pixel clock %iKHz\n",
1659 max_lane_count, common_rates[max_clock],
1660 adjusted_mode->crtc_clock);
1661
1662 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1663 * bpc in between. */
1664 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1665 if (is_edp(intel_dp)) {
1666
1667 /* Get bpp from vbt only for panels that dont have bpp in edid */
1668 if (intel_connector->base.display_info.bpc == 0 &&
1669 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1670 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1671 dev_priv->vbt.edp.bpp);
1672 bpp = dev_priv->vbt.edp.bpp;
1673 }
1674
1675 /*
1676 * Use the maximum clock and number of lanes the eDP panel
1677 * advertizes being capable of. The panels are generally
1678 * designed to support only a single clock and lane
1679 * configuration, and typically these values correspond to the
1680 * native resolution of the panel.
1681 */
1682 min_lane_count = max_lane_count;
1683 min_clock = max_clock;
1684 }
1685
1686 for (; bpp >= 6*3; bpp -= 2*3) {
1687 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1688 bpp);
1689
1690 for (clock = min_clock; clock <= max_clock; clock++) {
1691 for (lane_count = min_lane_count;
1692 lane_count <= max_lane_count;
1693 lane_count <<= 1) {
1694
1695 link_clock = common_rates[clock];
1696 link_avail = intel_dp_max_data_rate(link_clock,
1697 lane_count);
1698
1699 if (mode_rate <= link_avail) {
1700 goto found;
1701 }
1702 }
1703 }
1704 }
1705
1706 return false;
1707
1708 found:
1709 if (intel_dp->color_range_auto) {
1710 /*
1711 * See:
1712 * CEA-861-E - 5.1 Default Encoding Parameters
1713 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1714 */
1715 pipe_config->limited_color_range =
1716 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1717 } else {
1718 pipe_config->limited_color_range =
1719 intel_dp->limited_color_range;
1720 }
1721
1722 pipe_config->lane_count = lane_count;
1723
1724 pipe_config->pipe_bpp = bpp;
1725 pipe_config->port_clock = common_rates[clock];
1726
1727 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1728 &link_bw, &rate_select);
1729
1730 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1731 link_bw, rate_select, pipe_config->lane_count,
1732 pipe_config->port_clock, bpp);
1733 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1734 mode_rate, link_avail);
1735
1736 intel_link_compute_m_n(bpp, lane_count,
1737 adjusted_mode->crtc_clock,
1738 pipe_config->port_clock,
1739 &pipe_config->dp_m_n);
1740
1741 if (intel_connector->panel.downclock_mode != NULL &&
1742 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1743 pipe_config->has_drrs = true;
1744 intel_link_compute_m_n(bpp, lane_count,
1745 intel_connector->panel.downclock_mode->clock,
1746 pipe_config->port_clock,
1747 &pipe_config->dp_m2_n2);
1748 }
1749
1750 /*
1751 * DPLL0 VCO may need to be adjusted to get the correct
1752 * clock for eDP. This will affect cdclk as well.
1753 */
1754 if (is_edp(intel_dp) &&
1755 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1756 int vco;
1757
1758 switch (pipe_config->port_clock / 2) {
1759 case 108000:
1760 case 216000:
1761 vco = 8640000;
1762 break;
1763 default:
1764 vco = 8100000;
1765 break;
1766 }
1767
1768 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1769 }
1770
1771 if (!HAS_DDI(dev_priv))
1772 intel_dp_set_clock(encoder, pipe_config);
1773
1774 return true;
1775 }
1776
1777 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1778 int link_rate, uint8_t lane_count,
1779 bool link_mst)
1780 {
1781 intel_dp->link_rate = link_rate;
1782 intel_dp->lane_count = lane_count;
1783 intel_dp->link_mst = link_mst;
1784 }
1785
1786 static void intel_dp_prepare(struct intel_encoder *encoder,
1787 struct intel_crtc_state *pipe_config)
1788 {
1789 struct drm_device *dev = encoder->base.dev;
1790 struct drm_i915_private *dev_priv = to_i915(dev);
1791 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1792 enum port port = dp_to_dig_port(intel_dp)->port;
1793 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1794 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1795
1796 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1797 pipe_config->lane_count,
1798 intel_crtc_has_type(pipe_config,
1799 INTEL_OUTPUT_DP_MST));
1800
1801 /*
1802 * There are four kinds of DP registers:
1803 *
1804 * IBX PCH
1805 * SNB CPU
1806 * IVB CPU
1807 * CPT PCH
1808 *
1809 * IBX PCH and CPU are the same for almost everything,
1810 * except that the CPU DP PLL is configured in this
1811 * register
1812 *
1813 * CPT PCH is quite different, having many bits moved
1814 * to the TRANS_DP_CTL register instead. That
1815 * configuration happens (oddly) in ironlake_pch_enable
1816 */
1817
1818 /* Preserve the BIOS-computed detected bit. This is
1819 * supposed to be read-only.
1820 */
1821 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1822
1823 /* Handle DP bits in common between all three register formats */
1824 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1825 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1826
1827 /* Split out the IBX/CPU vs CPT settings */
1828
1829 if (IS_GEN7(dev_priv) && port == PORT_A) {
1830 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1831 intel_dp->DP |= DP_SYNC_HS_HIGH;
1832 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1833 intel_dp->DP |= DP_SYNC_VS_HIGH;
1834 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1835
1836 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1837 intel_dp->DP |= DP_ENHANCED_FRAMING;
1838
1839 intel_dp->DP |= crtc->pipe << 29;
1840 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1841 u32 trans_dp;
1842
1843 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1844
1845 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1846 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1847 trans_dp |= TRANS_DP_ENH_FRAMING;
1848 else
1849 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1850 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1851 } else {
1852 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1853 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1854
1855 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1856 intel_dp->DP |= DP_SYNC_HS_HIGH;
1857 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1858 intel_dp->DP |= DP_SYNC_VS_HIGH;
1859 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1860
1861 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1862 intel_dp->DP |= DP_ENHANCED_FRAMING;
1863
1864 if (IS_CHERRYVIEW(dev_priv))
1865 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1866 else if (crtc->pipe == PIPE_B)
1867 intel_dp->DP |= DP_PIPEB_SELECT;
1868 }
1869 }
1870
1871 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1872 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1873
1874 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1875 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1876
1877 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1878 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1879
1880 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1881 struct intel_dp *intel_dp);
1882
1883 static void wait_panel_status(struct intel_dp *intel_dp,
1884 u32 mask,
1885 u32 value)
1886 {
1887 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1888 struct drm_i915_private *dev_priv = to_i915(dev);
1889 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1890
1891 lockdep_assert_held(&dev_priv->pps_mutex);
1892
1893 intel_pps_verify_state(dev_priv, intel_dp);
1894
1895 pp_stat_reg = _pp_stat_reg(intel_dp);
1896 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1897
1898 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1899 mask, value,
1900 I915_READ(pp_stat_reg),
1901 I915_READ(pp_ctrl_reg));
1902
1903 if (intel_wait_for_register(dev_priv,
1904 pp_stat_reg, mask, value,
1905 5000))
1906 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1907 I915_READ(pp_stat_reg),
1908 I915_READ(pp_ctrl_reg));
1909
1910 DRM_DEBUG_KMS("Wait complete\n");
1911 }
1912
1913 static void wait_panel_on(struct intel_dp *intel_dp)
1914 {
1915 DRM_DEBUG_KMS("Wait for panel power on\n");
1916 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1917 }
1918
1919 static void wait_panel_off(struct intel_dp *intel_dp)
1920 {
1921 DRM_DEBUG_KMS("Wait for panel power off time\n");
1922 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1923 }
1924
1925 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1926 {
1927 ktime_t panel_power_on_time;
1928 s64 panel_power_off_duration;
1929
1930 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1931
1932 /* take the difference of currrent time and panel power off time
1933 * and then make panel wait for t11_t12 if needed. */
1934 panel_power_on_time = ktime_get_boottime();
1935 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1936
1937 /* When we disable the VDD override bit last we have to do the manual
1938 * wait. */
1939 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1940 wait_remaining_ms_from_jiffies(jiffies,
1941 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1942
1943 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1944 }
1945
1946 static void wait_backlight_on(struct intel_dp *intel_dp)
1947 {
1948 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1949 intel_dp->backlight_on_delay);
1950 }
1951
1952 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1953 {
1954 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1955 intel_dp->backlight_off_delay);
1956 }
1957
1958 /* Read the current pp_control value, unlocking the register if it
1959 * is locked
1960 */
1961
1962 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1963 {
1964 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1965 struct drm_i915_private *dev_priv = to_i915(dev);
1966 u32 control;
1967
1968 lockdep_assert_held(&dev_priv->pps_mutex);
1969
1970 control = I915_READ(_pp_ctrl_reg(intel_dp));
1971 if (WARN_ON(!HAS_DDI(dev_priv) &&
1972 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1973 control &= ~PANEL_UNLOCK_MASK;
1974 control |= PANEL_UNLOCK_REGS;
1975 }
1976 return control;
1977 }
1978
1979 /*
1980 * Must be paired with edp_panel_vdd_off().
1981 * Must hold pps_mutex around the whole on/off sequence.
1982 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1983 */
1984 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1985 {
1986 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1987 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1988 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1989 struct drm_i915_private *dev_priv = to_i915(dev);
1990 enum intel_display_power_domain power_domain;
1991 u32 pp;
1992 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1993 bool need_to_disable = !intel_dp->want_panel_vdd;
1994
1995 lockdep_assert_held(&dev_priv->pps_mutex);
1996
1997 if (!is_edp(intel_dp))
1998 return false;
1999
2000 cancel_delayed_work(&intel_dp->panel_vdd_work);
2001 intel_dp->want_panel_vdd = true;
2002
2003 if (edp_have_panel_vdd(intel_dp))
2004 return need_to_disable;
2005
2006 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2007 intel_display_power_get(dev_priv, power_domain);
2008
2009 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2010 port_name(intel_dig_port->port));
2011
2012 if (!edp_have_panel_power(intel_dp))
2013 wait_panel_power_cycle(intel_dp);
2014
2015 pp = ironlake_get_pp_control(intel_dp);
2016 pp |= EDP_FORCE_VDD;
2017
2018 pp_stat_reg = _pp_stat_reg(intel_dp);
2019 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2020
2021 I915_WRITE(pp_ctrl_reg, pp);
2022 POSTING_READ(pp_ctrl_reg);
2023 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2024 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2025 /*
2026 * If the panel wasn't on, delay before accessing aux channel
2027 */
2028 if (!edp_have_panel_power(intel_dp)) {
2029 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2030 port_name(intel_dig_port->port));
2031 msleep(intel_dp->panel_power_up_delay);
2032 }
2033
2034 return need_to_disable;
2035 }
2036
2037 /*
2038 * Must be paired with intel_edp_panel_vdd_off() or
2039 * intel_edp_panel_off().
2040 * Nested calls to these functions are not allowed since
2041 * we drop the lock. Caller must use some higher level
2042 * locking to prevent nested calls from other threads.
2043 */
2044 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2045 {
2046 bool vdd;
2047
2048 if (!is_edp(intel_dp))
2049 return;
2050
2051 pps_lock(intel_dp);
2052 vdd = edp_panel_vdd_on(intel_dp);
2053 pps_unlock(intel_dp);
2054
2055 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2056 port_name(dp_to_dig_port(intel_dp)->port));
2057 }
2058
2059 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2060 {
2061 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2062 struct drm_i915_private *dev_priv = to_i915(dev);
2063 struct intel_digital_port *intel_dig_port =
2064 dp_to_dig_port(intel_dp);
2065 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2066 enum intel_display_power_domain power_domain;
2067 u32 pp;
2068 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2069
2070 lockdep_assert_held(&dev_priv->pps_mutex);
2071
2072 WARN_ON(intel_dp->want_panel_vdd);
2073
2074 if (!edp_have_panel_vdd(intel_dp))
2075 return;
2076
2077 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2078 port_name(intel_dig_port->port));
2079
2080 pp = ironlake_get_pp_control(intel_dp);
2081 pp &= ~EDP_FORCE_VDD;
2082
2083 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2084 pp_stat_reg = _pp_stat_reg(intel_dp);
2085
2086 I915_WRITE(pp_ctrl_reg, pp);
2087 POSTING_READ(pp_ctrl_reg);
2088
2089 /* Make sure sequencer is idle before allowing subsequent activity */
2090 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2091 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2092
2093 if ((pp & PANEL_POWER_ON) == 0)
2094 intel_dp->panel_power_off_time = ktime_get_boottime();
2095
2096 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2097 intel_display_power_put(dev_priv, power_domain);
2098 }
2099
2100 static void edp_panel_vdd_work(struct work_struct *__work)
2101 {
2102 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2103 struct intel_dp, panel_vdd_work);
2104
2105 pps_lock(intel_dp);
2106 if (!intel_dp->want_panel_vdd)
2107 edp_panel_vdd_off_sync(intel_dp);
2108 pps_unlock(intel_dp);
2109 }
2110
2111 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2112 {
2113 unsigned long delay;
2114
2115 /*
2116 * Queue the timer to fire a long time from now (relative to the power
2117 * down delay) to keep the panel power up across a sequence of
2118 * operations.
2119 */
2120 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2121 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2122 }
2123
2124 /*
2125 * Must be paired with edp_panel_vdd_on().
2126 * Must hold pps_mutex around the whole on/off sequence.
2127 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2128 */
2129 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2130 {
2131 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2132
2133 lockdep_assert_held(&dev_priv->pps_mutex);
2134
2135 if (!is_edp(intel_dp))
2136 return;
2137
2138 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2139 port_name(dp_to_dig_port(intel_dp)->port));
2140
2141 intel_dp->want_panel_vdd = false;
2142
2143 if (sync)
2144 edp_panel_vdd_off_sync(intel_dp);
2145 else
2146 edp_panel_vdd_schedule_off(intel_dp);
2147 }
2148
2149 static void edp_panel_on(struct intel_dp *intel_dp)
2150 {
2151 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2152 struct drm_i915_private *dev_priv = to_i915(dev);
2153 u32 pp;
2154 i915_reg_t pp_ctrl_reg;
2155
2156 lockdep_assert_held(&dev_priv->pps_mutex);
2157
2158 if (!is_edp(intel_dp))
2159 return;
2160
2161 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2162 port_name(dp_to_dig_port(intel_dp)->port));
2163
2164 if (WARN(edp_have_panel_power(intel_dp),
2165 "eDP port %c panel power already on\n",
2166 port_name(dp_to_dig_port(intel_dp)->port)))
2167 return;
2168
2169 wait_panel_power_cycle(intel_dp);
2170
2171 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2172 pp = ironlake_get_pp_control(intel_dp);
2173 if (IS_GEN5(dev_priv)) {
2174 /* ILK workaround: disable reset around power sequence */
2175 pp &= ~PANEL_POWER_RESET;
2176 I915_WRITE(pp_ctrl_reg, pp);
2177 POSTING_READ(pp_ctrl_reg);
2178 }
2179
2180 pp |= PANEL_POWER_ON;
2181 if (!IS_GEN5(dev_priv))
2182 pp |= PANEL_POWER_RESET;
2183
2184 I915_WRITE(pp_ctrl_reg, pp);
2185 POSTING_READ(pp_ctrl_reg);
2186
2187 wait_panel_on(intel_dp);
2188 intel_dp->last_power_on = jiffies;
2189
2190 if (IS_GEN5(dev_priv)) {
2191 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2192 I915_WRITE(pp_ctrl_reg, pp);
2193 POSTING_READ(pp_ctrl_reg);
2194 }
2195 }
2196
2197 void intel_edp_panel_on(struct intel_dp *intel_dp)
2198 {
2199 if (!is_edp(intel_dp))
2200 return;
2201
2202 pps_lock(intel_dp);
2203 edp_panel_on(intel_dp);
2204 pps_unlock(intel_dp);
2205 }
2206
2207
2208 static void edp_panel_off(struct intel_dp *intel_dp)
2209 {
2210 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2211 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2212 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2213 struct drm_i915_private *dev_priv = to_i915(dev);
2214 enum intel_display_power_domain power_domain;
2215 u32 pp;
2216 i915_reg_t pp_ctrl_reg;
2217
2218 lockdep_assert_held(&dev_priv->pps_mutex);
2219
2220 if (!is_edp(intel_dp))
2221 return;
2222
2223 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2224 port_name(dp_to_dig_port(intel_dp)->port));
2225
2226 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2227 port_name(dp_to_dig_port(intel_dp)->port));
2228
2229 pp = ironlake_get_pp_control(intel_dp);
2230 /* We need to switch off panel power _and_ force vdd, for otherwise some
2231 * panels get very unhappy and cease to work. */
2232 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2233 EDP_BLC_ENABLE);
2234
2235 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2236
2237 intel_dp->want_panel_vdd = false;
2238
2239 I915_WRITE(pp_ctrl_reg, pp);
2240 POSTING_READ(pp_ctrl_reg);
2241
2242 intel_dp->panel_power_off_time = ktime_get_boottime();
2243 wait_panel_off(intel_dp);
2244
2245 /* We got a reference when we enabled the VDD. */
2246 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2247 intel_display_power_put(dev_priv, power_domain);
2248 }
2249
2250 void intel_edp_panel_off(struct intel_dp *intel_dp)
2251 {
2252 if (!is_edp(intel_dp))
2253 return;
2254
2255 pps_lock(intel_dp);
2256 edp_panel_off(intel_dp);
2257 pps_unlock(intel_dp);
2258 }
2259
2260 /* Enable backlight in the panel power control. */
2261 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2262 {
2263 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2264 struct drm_device *dev = intel_dig_port->base.base.dev;
2265 struct drm_i915_private *dev_priv = to_i915(dev);
2266 u32 pp;
2267 i915_reg_t pp_ctrl_reg;
2268
2269 /*
2270 * If we enable the backlight right away following a panel power
2271 * on, we may see slight flicker as the panel syncs with the eDP
2272 * link. So delay a bit to make sure the image is solid before
2273 * allowing it to appear.
2274 */
2275 wait_backlight_on(intel_dp);
2276
2277 pps_lock(intel_dp);
2278
2279 pp = ironlake_get_pp_control(intel_dp);
2280 pp |= EDP_BLC_ENABLE;
2281
2282 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2283
2284 I915_WRITE(pp_ctrl_reg, pp);
2285 POSTING_READ(pp_ctrl_reg);
2286
2287 pps_unlock(intel_dp);
2288 }
2289
2290 /* Enable backlight PWM and backlight PP control. */
2291 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2292 {
2293 if (!is_edp(intel_dp))
2294 return;
2295
2296 DRM_DEBUG_KMS("\n");
2297
2298 intel_panel_enable_backlight(intel_dp->attached_connector);
2299 _intel_edp_backlight_on(intel_dp);
2300 }
2301
2302 /* Disable backlight in the panel power control. */
2303 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2304 {
2305 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2306 struct drm_i915_private *dev_priv = to_i915(dev);
2307 u32 pp;
2308 i915_reg_t pp_ctrl_reg;
2309
2310 if (!is_edp(intel_dp))
2311 return;
2312
2313 pps_lock(intel_dp);
2314
2315 pp = ironlake_get_pp_control(intel_dp);
2316 pp &= ~EDP_BLC_ENABLE;
2317
2318 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2319
2320 I915_WRITE(pp_ctrl_reg, pp);
2321 POSTING_READ(pp_ctrl_reg);
2322
2323 pps_unlock(intel_dp);
2324
2325 intel_dp->last_backlight_off = jiffies;
2326 edp_wait_backlight_off(intel_dp);
2327 }
2328
2329 /* Disable backlight PP control and backlight PWM. */
2330 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2331 {
2332 if (!is_edp(intel_dp))
2333 return;
2334
2335 DRM_DEBUG_KMS("\n");
2336
2337 _intel_edp_backlight_off(intel_dp);
2338 intel_panel_disable_backlight(intel_dp->attached_connector);
2339 }
2340
2341 /*
2342 * Hook for controlling the panel power control backlight through the bl_power
2343 * sysfs attribute. Take care to handle multiple calls.
2344 */
2345 static void intel_edp_backlight_power(struct intel_connector *connector,
2346 bool enable)
2347 {
2348 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2349 bool is_enabled;
2350
2351 pps_lock(intel_dp);
2352 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2353 pps_unlock(intel_dp);
2354
2355 if (is_enabled == enable)
2356 return;
2357
2358 DRM_DEBUG_KMS("panel power control backlight %s\n",
2359 enable ? "enable" : "disable");
2360
2361 if (enable)
2362 _intel_edp_backlight_on(intel_dp);
2363 else
2364 _intel_edp_backlight_off(intel_dp);
2365 }
2366
2367 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2368 {
2369 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2370 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2371 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2372
2373 I915_STATE_WARN(cur_state != state,
2374 "DP port %c state assertion failure (expected %s, current %s)\n",
2375 port_name(dig_port->port),
2376 onoff(state), onoff(cur_state));
2377 }
2378 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2379
2380 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2381 {
2382 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2383
2384 I915_STATE_WARN(cur_state != state,
2385 "eDP PLL state assertion failure (expected %s, current %s)\n",
2386 onoff(state), onoff(cur_state));
2387 }
2388 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2389 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2390
2391 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2392 struct intel_crtc_state *pipe_config)
2393 {
2394 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2396
2397 assert_pipe_disabled(dev_priv, crtc->pipe);
2398 assert_dp_port_disabled(intel_dp);
2399 assert_edp_pll_disabled(dev_priv);
2400
2401 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2402 pipe_config->port_clock);
2403
2404 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2405
2406 if (pipe_config->port_clock == 162000)
2407 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2408 else
2409 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2410
2411 I915_WRITE(DP_A, intel_dp->DP);
2412 POSTING_READ(DP_A);
2413 udelay(500);
2414
2415 /*
2416 * [DevILK] Work around required when enabling DP PLL
2417 * while a pipe is enabled going to FDI:
2418 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2419 * 2. Program DP PLL enable
2420 */
2421 if (IS_GEN5(dev_priv))
2422 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2423
2424 intel_dp->DP |= DP_PLL_ENABLE;
2425
2426 I915_WRITE(DP_A, intel_dp->DP);
2427 POSTING_READ(DP_A);
2428 udelay(200);
2429 }
2430
2431 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2432 {
2433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2434 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2436
2437 assert_pipe_disabled(dev_priv, crtc->pipe);
2438 assert_dp_port_disabled(intel_dp);
2439 assert_edp_pll_enabled(dev_priv);
2440
2441 DRM_DEBUG_KMS("disabling eDP PLL\n");
2442
2443 intel_dp->DP &= ~DP_PLL_ENABLE;
2444
2445 I915_WRITE(DP_A, intel_dp->DP);
2446 POSTING_READ(DP_A);
2447 udelay(200);
2448 }
2449
2450 /* If the sink supports it, try to set the power state appropriately */
2451 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2452 {
2453 int ret, i;
2454
2455 /* Should have a valid DPCD by this point */
2456 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2457 return;
2458
2459 if (mode != DRM_MODE_DPMS_ON) {
2460 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2461 DP_SET_POWER_D3);
2462 } else {
2463 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2464
2465 /*
2466 * When turning on, we need to retry for 1ms to give the sink
2467 * time to wake up.
2468 */
2469 for (i = 0; i < 3; i++) {
2470 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2471 DP_SET_POWER_D0);
2472 if (ret == 1)
2473 break;
2474 msleep(1);
2475 }
2476
2477 if (ret == 1 && lspcon->active)
2478 lspcon_wait_pcon_mode(lspcon);
2479 }
2480
2481 if (ret != 1)
2482 DRM_DEBUG_KMS("failed to %s sink power state\n",
2483 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2484 }
2485
2486 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2487 enum pipe *pipe)
2488 {
2489 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2490 enum port port = dp_to_dig_port(intel_dp)->port;
2491 struct drm_device *dev = encoder->base.dev;
2492 struct drm_i915_private *dev_priv = to_i915(dev);
2493 enum intel_display_power_domain power_domain;
2494 u32 tmp;
2495 bool ret;
2496
2497 power_domain = intel_display_port_power_domain(encoder);
2498 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2499 return false;
2500
2501 ret = false;
2502
2503 tmp = I915_READ(intel_dp->output_reg);
2504
2505 if (!(tmp & DP_PORT_EN))
2506 goto out;
2507
2508 if (IS_GEN7(dev_priv) && port == PORT_A) {
2509 *pipe = PORT_TO_PIPE_CPT(tmp);
2510 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2511 enum pipe p;
2512
2513 for_each_pipe(dev_priv, p) {
2514 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2515 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2516 *pipe = p;
2517 ret = true;
2518
2519 goto out;
2520 }
2521 }
2522
2523 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2524 i915_mmio_reg_offset(intel_dp->output_reg));
2525 } else if (IS_CHERRYVIEW(dev_priv)) {
2526 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2527 } else {
2528 *pipe = PORT_TO_PIPE(tmp);
2529 }
2530
2531 ret = true;
2532
2533 out:
2534 intel_display_power_put(dev_priv, power_domain);
2535
2536 return ret;
2537 }
2538
2539 static void intel_dp_get_config(struct intel_encoder *encoder,
2540 struct intel_crtc_state *pipe_config)
2541 {
2542 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2543 u32 tmp, flags = 0;
2544 struct drm_device *dev = encoder->base.dev;
2545 struct drm_i915_private *dev_priv = to_i915(dev);
2546 enum port port = dp_to_dig_port(intel_dp)->port;
2547 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2548
2549 tmp = I915_READ(intel_dp->output_reg);
2550
2551 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2552
2553 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2554 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2555
2556 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2557 flags |= DRM_MODE_FLAG_PHSYNC;
2558 else
2559 flags |= DRM_MODE_FLAG_NHSYNC;
2560
2561 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2562 flags |= DRM_MODE_FLAG_PVSYNC;
2563 else
2564 flags |= DRM_MODE_FLAG_NVSYNC;
2565 } else {
2566 if (tmp & DP_SYNC_HS_HIGH)
2567 flags |= DRM_MODE_FLAG_PHSYNC;
2568 else
2569 flags |= DRM_MODE_FLAG_NHSYNC;
2570
2571 if (tmp & DP_SYNC_VS_HIGH)
2572 flags |= DRM_MODE_FLAG_PVSYNC;
2573 else
2574 flags |= DRM_MODE_FLAG_NVSYNC;
2575 }
2576
2577 pipe_config->base.adjusted_mode.flags |= flags;
2578
2579 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2580 pipe_config->limited_color_range = true;
2581
2582 pipe_config->lane_count =
2583 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2584
2585 intel_dp_get_m_n(crtc, pipe_config);
2586
2587 if (port == PORT_A) {
2588 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2589 pipe_config->port_clock = 162000;
2590 else
2591 pipe_config->port_clock = 270000;
2592 }
2593
2594 pipe_config->base.adjusted_mode.crtc_clock =
2595 intel_dotclock_calculate(pipe_config->port_clock,
2596 &pipe_config->dp_m_n);
2597
2598 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2599 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2600 /*
2601 * This is a big fat ugly hack.
2602 *
2603 * Some machines in UEFI boot mode provide us a VBT that has 18
2604 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2605 * unknown we fail to light up. Yet the same BIOS boots up with
2606 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2607 * max, not what it tells us to use.
2608 *
2609 * Note: This will still be broken if the eDP panel is not lit
2610 * up by the BIOS, and thus we can't get the mode at module
2611 * load.
2612 */
2613 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2614 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2615 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2616 }
2617 }
2618
2619 static void intel_disable_dp(struct intel_encoder *encoder,
2620 struct intel_crtc_state *old_crtc_state,
2621 struct drm_connector_state *old_conn_state)
2622 {
2623 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2624 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2625
2626 if (old_crtc_state->has_audio)
2627 intel_audio_codec_disable(encoder);
2628
2629 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2630 intel_psr_disable(intel_dp);
2631
2632 /* Make sure the panel is off before trying to change the mode. But also
2633 * ensure that we have vdd while we switch off the panel. */
2634 intel_edp_panel_vdd_on(intel_dp);
2635 intel_edp_backlight_off(intel_dp);
2636 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2637 intel_edp_panel_off(intel_dp);
2638
2639 /* disable the port before the pipe on g4x */
2640 if (INTEL_GEN(dev_priv) < 5)
2641 intel_dp_link_down(intel_dp);
2642 }
2643
2644 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2645 struct intel_crtc_state *old_crtc_state,
2646 struct drm_connector_state *old_conn_state)
2647 {
2648 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2649 enum port port = dp_to_dig_port(intel_dp)->port;
2650
2651 intel_dp_link_down(intel_dp);
2652
2653 /* Only ilk+ has port A */
2654 if (port == PORT_A)
2655 ironlake_edp_pll_off(intel_dp);
2656 }
2657
2658 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2659 struct intel_crtc_state *old_crtc_state,
2660 struct drm_connector_state *old_conn_state)
2661 {
2662 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2663
2664 intel_dp_link_down(intel_dp);
2665 }
2666
2667 static void chv_post_disable_dp(struct intel_encoder *encoder,
2668 struct intel_crtc_state *old_crtc_state,
2669 struct drm_connector_state *old_conn_state)
2670 {
2671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2672 struct drm_device *dev = encoder->base.dev;
2673 struct drm_i915_private *dev_priv = to_i915(dev);
2674
2675 intel_dp_link_down(intel_dp);
2676
2677 mutex_lock(&dev_priv->sb_lock);
2678
2679 /* Assert data lane reset */
2680 chv_data_lane_soft_reset(encoder, true);
2681
2682 mutex_unlock(&dev_priv->sb_lock);
2683 }
2684
2685 static void
2686 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2687 uint32_t *DP,
2688 uint8_t dp_train_pat)
2689 {
2690 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2691 struct drm_device *dev = intel_dig_port->base.base.dev;
2692 struct drm_i915_private *dev_priv = to_i915(dev);
2693 enum port port = intel_dig_port->port;
2694
2695 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2696 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2697 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2698
2699 if (HAS_DDI(dev_priv)) {
2700 uint32_t temp = I915_READ(DP_TP_CTL(port));
2701
2702 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2703 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2704 else
2705 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2706
2707 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2708 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2709 case DP_TRAINING_PATTERN_DISABLE:
2710 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2711
2712 break;
2713 case DP_TRAINING_PATTERN_1:
2714 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2715 break;
2716 case DP_TRAINING_PATTERN_2:
2717 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2718 break;
2719 case DP_TRAINING_PATTERN_3:
2720 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2721 break;
2722 }
2723 I915_WRITE(DP_TP_CTL(port), temp);
2724
2725 } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2726 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2727 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2728
2729 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2730 case DP_TRAINING_PATTERN_DISABLE:
2731 *DP |= DP_LINK_TRAIN_OFF_CPT;
2732 break;
2733 case DP_TRAINING_PATTERN_1:
2734 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2735 break;
2736 case DP_TRAINING_PATTERN_2:
2737 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2738 break;
2739 case DP_TRAINING_PATTERN_3:
2740 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2741 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2742 break;
2743 }
2744
2745 } else {
2746 if (IS_CHERRYVIEW(dev_priv))
2747 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2748 else
2749 *DP &= ~DP_LINK_TRAIN_MASK;
2750
2751 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2752 case DP_TRAINING_PATTERN_DISABLE:
2753 *DP |= DP_LINK_TRAIN_OFF;
2754 break;
2755 case DP_TRAINING_PATTERN_1:
2756 *DP |= DP_LINK_TRAIN_PAT_1;
2757 break;
2758 case DP_TRAINING_PATTERN_2:
2759 *DP |= DP_LINK_TRAIN_PAT_2;
2760 break;
2761 case DP_TRAINING_PATTERN_3:
2762 if (IS_CHERRYVIEW(dev_priv)) {
2763 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2764 } else {
2765 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2766 *DP |= DP_LINK_TRAIN_PAT_2;
2767 }
2768 break;
2769 }
2770 }
2771 }
2772
2773 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2774 struct intel_crtc_state *old_crtc_state)
2775 {
2776 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2777 struct drm_i915_private *dev_priv = to_i915(dev);
2778
2779 /* enable with pattern 1 (as per spec) */
2780
2781 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2782
2783 /*
2784 * Magic for VLV/CHV. We _must_ first set up the register
2785 * without actually enabling the port, and then do another
2786 * write to enable the port. Otherwise link training will
2787 * fail when the power sequencer is freshly used for this port.
2788 */
2789 intel_dp->DP |= DP_PORT_EN;
2790 if (old_crtc_state->has_audio)
2791 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2792
2793 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2794 POSTING_READ(intel_dp->output_reg);
2795 }
2796
2797 static void intel_enable_dp(struct intel_encoder *encoder,
2798 struct intel_crtc_state *pipe_config,
2799 struct drm_connector_state *conn_state)
2800 {
2801 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2802 struct drm_device *dev = encoder->base.dev;
2803 struct drm_i915_private *dev_priv = to_i915(dev);
2804 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2805 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2806 enum pipe pipe = crtc->pipe;
2807
2808 if (WARN_ON(dp_reg & DP_PORT_EN))
2809 return;
2810
2811 pps_lock(intel_dp);
2812
2813 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2814 vlv_init_panel_power_sequencer(intel_dp);
2815
2816 intel_dp_enable_port(intel_dp, pipe_config);
2817
2818 edp_panel_vdd_on(intel_dp);
2819 edp_panel_on(intel_dp);
2820 edp_panel_vdd_off(intel_dp, true);
2821
2822 pps_unlock(intel_dp);
2823
2824 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2825 unsigned int lane_mask = 0x0;
2826
2827 if (IS_CHERRYVIEW(dev_priv))
2828 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2829
2830 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2831 lane_mask);
2832 }
2833
2834 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2835 intel_dp_start_link_train(intel_dp);
2836 intel_dp_stop_link_train(intel_dp);
2837
2838 if (pipe_config->has_audio) {
2839 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2840 pipe_name(pipe));
2841 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2842 }
2843 }
2844
2845 static void g4x_enable_dp(struct intel_encoder *encoder,
2846 struct intel_crtc_state *pipe_config,
2847 struct drm_connector_state *conn_state)
2848 {
2849 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2850
2851 intel_enable_dp(encoder, pipe_config, conn_state);
2852 intel_edp_backlight_on(intel_dp);
2853 }
2854
2855 static void vlv_enable_dp(struct intel_encoder *encoder,
2856 struct intel_crtc_state *pipe_config,
2857 struct drm_connector_state *conn_state)
2858 {
2859 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2860
2861 intel_edp_backlight_on(intel_dp);
2862 intel_psr_enable(intel_dp);
2863 }
2864
2865 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2866 struct intel_crtc_state *pipe_config,
2867 struct drm_connector_state *conn_state)
2868 {
2869 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2870 enum port port = dp_to_dig_port(intel_dp)->port;
2871
2872 intel_dp_prepare(encoder, pipe_config);
2873
2874 /* Only ilk+ has port A */
2875 if (port == PORT_A)
2876 ironlake_edp_pll_on(intel_dp, pipe_config);
2877 }
2878
2879 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2880 {
2881 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2882 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2883 enum pipe pipe = intel_dp->pps_pipe;
2884 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2885
2886 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2887
2888 edp_panel_vdd_off_sync(intel_dp);
2889
2890 /*
2891 * VLV seems to get confused when multiple power seqeuencers
2892 * have the same port selected (even if only one has power/vdd
2893 * enabled). The failure manifests as vlv_wait_port_ready() failing
2894 * CHV on the other hand doesn't seem to mind having the same port
2895 * selected in multiple power seqeuencers, but let's clear the
2896 * port select always when logically disconnecting a power sequencer
2897 * from a port.
2898 */
2899 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2900 pipe_name(pipe), port_name(intel_dig_port->port));
2901 I915_WRITE(pp_on_reg, 0);
2902 POSTING_READ(pp_on_reg);
2903
2904 intel_dp->pps_pipe = INVALID_PIPE;
2905 }
2906
2907 static void vlv_steal_power_sequencer(struct drm_device *dev,
2908 enum pipe pipe)
2909 {
2910 struct drm_i915_private *dev_priv = to_i915(dev);
2911 struct intel_encoder *encoder;
2912
2913 lockdep_assert_held(&dev_priv->pps_mutex);
2914
2915 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2916 return;
2917
2918 for_each_intel_encoder(dev, encoder) {
2919 struct intel_dp *intel_dp;
2920 enum port port;
2921
2922 if (encoder->type != INTEL_OUTPUT_DP &&
2923 encoder->type != INTEL_OUTPUT_EDP)
2924 continue;
2925
2926 intel_dp = enc_to_intel_dp(&encoder->base);
2927 port = dp_to_dig_port(intel_dp)->port;
2928
2929 WARN(intel_dp->active_pipe == pipe,
2930 "stealing pipe %c power sequencer from active (e)DP port %c\n",
2931 pipe_name(pipe), port_name(port));
2932
2933 if (intel_dp->pps_pipe != pipe)
2934 continue;
2935
2936 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2937 pipe_name(pipe), port_name(port));
2938
2939 /* make sure vdd is off before we steal it */
2940 vlv_detach_power_sequencer(intel_dp);
2941 }
2942 }
2943
2944 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2945 {
2946 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2947 struct intel_encoder *encoder = &intel_dig_port->base;
2948 struct drm_device *dev = encoder->base.dev;
2949 struct drm_i915_private *dev_priv = to_i915(dev);
2950 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2951
2952 lockdep_assert_held(&dev_priv->pps_mutex);
2953
2954 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2955
2956 if (intel_dp->pps_pipe != INVALID_PIPE &&
2957 intel_dp->pps_pipe != crtc->pipe) {
2958 /*
2959 * If another power sequencer was being used on this
2960 * port previously make sure to turn off vdd there while
2961 * we still have control of it.
2962 */
2963 vlv_detach_power_sequencer(intel_dp);
2964 }
2965
2966 /*
2967 * We may be stealing the power
2968 * sequencer from another port.
2969 */
2970 vlv_steal_power_sequencer(dev, crtc->pipe);
2971
2972 intel_dp->active_pipe = crtc->pipe;
2973
2974 if (!is_edp(intel_dp))
2975 return;
2976
2977 /* now it's all ours */
2978 intel_dp->pps_pipe = crtc->pipe;
2979
2980 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2981 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2982
2983 /* init power sequencer on this pipe and port */
2984 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2985 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
2986 }
2987
2988 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2989 struct intel_crtc_state *pipe_config,
2990 struct drm_connector_state *conn_state)
2991 {
2992 vlv_phy_pre_encoder_enable(encoder);
2993
2994 intel_enable_dp(encoder, pipe_config, conn_state);
2995 }
2996
2997 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2998 struct intel_crtc_state *pipe_config,
2999 struct drm_connector_state *conn_state)
3000 {
3001 intel_dp_prepare(encoder, pipe_config);
3002
3003 vlv_phy_pre_pll_enable(encoder);
3004 }
3005
3006 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3007 struct intel_crtc_state *pipe_config,
3008 struct drm_connector_state *conn_state)
3009 {
3010 chv_phy_pre_encoder_enable(encoder);
3011
3012 intel_enable_dp(encoder, pipe_config, conn_state);
3013
3014 /* Second common lane will stay alive on its own now */
3015 chv_phy_release_cl2_override(encoder);
3016 }
3017
3018 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3019 struct intel_crtc_state *pipe_config,
3020 struct drm_connector_state *conn_state)
3021 {
3022 intel_dp_prepare(encoder, pipe_config);
3023
3024 chv_phy_pre_pll_enable(encoder);
3025 }
3026
3027 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3028 struct intel_crtc_state *pipe_config,
3029 struct drm_connector_state *conn_state)
3030 {
3031 chv_phy_post_pll_disable(encoder);
3032 }
3033
3034 /*
3035 * Fetch AUX CH registers 0x202 - 0x207 which contain
3036 * link status information
3037 */
3038 bool
3039 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3040 {
3041 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3042 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3043 }
3044
3045 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3046 {
3047 uint8_t psr_caps = 0;
3048
3049 drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
3050 return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3051 }
3052
3053 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3054 {
3055 uint8_t dprx = 0;
3056
3057 drm_dp_dpcd_readb(&intel_dp->aux,
3058 DP_DPRX_FEATURE_ENUMERATION_LIST,
3059 &dprx);
3060 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3061 }
3062
3063 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3064 {
3065 uint8_t alpm_caps = 0;
3066
3067 drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
3068 return alpm_caps & DP_ALPM_CAP;
3069 }
3070
3071 /* These are source-specific values. */
3072 uint8_t
3073 intel_dp_voltage_max(struct intel_dp *intel_dp)
3074 {
3075 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3076 enum port port = dp_to_dig_port(intel_dp)->port;
3077
3078 if (IS_GEN9_LP(dev_priv))
3079 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3080 else if (INTEL_GEN(dev_priv) >= 9) {
3081 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
3082 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3083 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3084 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3085 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3086 else if (IS_GEN7(dev_priv) && port == PORT_A)
3087 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3088 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3089 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3090 else
3091 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3092 }
3093
3094 uint8_t
3095 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3096 {
3097 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3098 enum port port = dp_to_dig_port(intel_dp)->port;
3099
3100 if (INTEL_GEN(dev_priv) >= 9) {
3101 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3102 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3103 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3105 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3107 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3109 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3110 default:
3111 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3112 }
3113 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3114 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3116 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3118 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3120 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3122 default:
3123 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3124 }
3125 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3126 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3128 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3130 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3132 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3134 default:
3135 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3136 }
3137 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3138 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3140 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3142 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3143 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3144 default:
3145 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3146 }
3147 } else {
3148 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3149 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3150 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3151 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3152 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3154 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3156 default:
3157 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3158 }
3159 }
3160 }
3161
3162 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3163 {
3164 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3165 unsigned long demph_reg_value, preemph_reg_value,
3166 uniqtranscale_reg_value;
3167 uint8_t train_set = intel_dp->train_set[0];
3168
3169 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3170 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3171 preemph_reg_value = 0x0004000;
3172 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3174 demph_reg_value = 0x2B405555;
3175 uniqtranscale_reg_value = 0x552AB83A;
3176 break;
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3178 demph_reg_value = 0x2B404040;
3179 uniqtranscale_reg_value = 0x5548B83A;
3180 break;
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3182 demph_reg_value = 0x2B245555;
3183 uniqtranscale_reg_value = 0x5560B83A;
3184 break;
3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3186 demph_reg_value = 0x2B405555;
3187 uniqtranscale_reg_value = 0x5598DA3A;
3188 break;
3189 default:
3190 return 0;
3191 }
3192 break;
3193 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3194 preemph_reg_value = 0x0002000;
3195 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3197 demph_reg_value = 0x2B404040;
3198 uniqtranscale_reg_value = 0x5552B83A;
3199 break;
3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3201 demph_reg_value = 0x2B404848;
3202 uniqtranscale_reg_value = 0x5580B83A;
3203 break;
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3205 demph_reg_value = 0x2B404040;
3206 uniqtranscale_reg_value = 0x55ADDA3A;
3207 break;
3208 default:
3209 return 0;
3210 }
3211 break;
3212 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3213 preemph_reg_value = 0x0000000;
3214 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3216 demph_reg_value = 0x2B305555;
3217 uniqtranscale_reg_value = 0x5570B83A;
3218 break;
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3220 demph_reg_value = 0x2B2B4040;
3221 uniqtranscale_reg_value = 0x55ADDA3A;
3222 break;
3223 default:
3224 return 0;
3225 }
3226 break;
3227 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3228 preemph_reg_value = 0x0006000;
3229 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3230 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3231 demph_reg_value = 0x1B405555;
3232 uniqtranscale_reg_value = 0x55ADDA3A;
3233 break;
3234 default:
3235 return 0;
3236 }
3237 break;
3238 default:
3239 return 0;
3240 }
3241
3242 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3243 uniqtranscale_reg_value, 0);
3244
3245 return 0;
3246 }
3247
3248 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3249 {
3250 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3251 u32 deemph_reg_value, margin_reg_value;
3252 bool uniq_trans_scale = false;
3253 uint8_t train_set = intel_dp->train_set[0];
3254
3255 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3256 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3257 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3259 deemph_reg_value = 128;
3260 margin_reg_value = 52;
3261 break;
3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3263 deemph_reg_value = 128;
3264 margin_reg_value = 77;
3265 break;
3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3267 deemph_reg_value = 128;
3268 margin_reg_value = 102;
3269 break;
3270 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3271 deemph_reg_value = 128;
3272 margin_reg_value = 154;
3273 uniq_trans_scale = true;
3274 break;
3275 default:
3276 return 0;
3277 }
3278 break;
3279 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3280 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3282 deemph_reg_value = 85;
3283 margin_reg_value = 78;
3284 break;
3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3286 deemph_reg_value = 85;
3287 margin_reg_value = 116;
3288 break;
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3290 deemph_reg_value = 85;
3291 margin_reg_value = 154;
3292 break;
3293 default:
3294 return 0;
3295 }
3296 break;
3297 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3298 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3300 deemph_reg_value = 64;
3301 margin_reg_value = 104;
3302 break;
3303 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3304 deemph_reg_value = 64;
3305 margin_reg_value = 154;
3306 break;
3307 default:
3308 return 0;
3309 }
3310 break;
3311 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3312 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3314 deemph_reg_value = 43;
3315 margin_reg_value = 154;
3316 break;
3317 default:
3318 return 0;
3319 }
3320 break;
3321 default:
3322 return 0;
3323 }
3324
3325 chv_set_phy_signal_level(encoder, deemph_reg_value,
3326 margin_reg_value, uniq_trans_scale);
3327
3328 return 0;
3329 }
3330
3331 static uint32_t
3332 gen4_signal_levels(uint8_t train_set)
3333 {
3334 uint32_t signal_levels = 0;
3335
3336 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3338 default:
3339 signal_levels |= DP_VOLTAGE_0_4;
3340 break;
3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3342 signal_levels |= DP_VOLTAGE_0_6;
3343 break;
3344 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3345 signal_levels |= DP_VOLTAGE_0_8;
3346 break;
3347 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3348 signal_levels |= DP_VOLTAGE_1_2;
3349 break;
3350 }
3351 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3352 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3353 default:
3354 signal_levels |= DP_PRE_EMPHASIS_0;
3355 break;
3356 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3357 signal_levels |= DP_PRE_EMPHASIS_3_5;
3358 break;
3359 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3360 signal_levels |= DP_PRE_EMPHASIS_6;
3361 break;
3362 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3363 signal_levels |= DP_PRE_EMPHASIS_9_5;
3364 break;
3365 }
3366 return signal_levels;
3367 }
3368
3369 /* Gen6's DP voltage swing and pre-emphasis control */
3370 static uint32_t
3371 gen6_edp_signal_levels(uint8_t train_set)
3372 {
3373 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3374 DP_TRAIN_PRE_EMPHASIS_MASK);
3375 switch (signal_levels) {
3376 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3377 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3378 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3379 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3380 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3381 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3383 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3384 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3386 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3387 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3389 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3390 default:
3391 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3392 "0x%x\n", signal_levels);
3393 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3394 }
3395 }
3396
3397 /* Gen7's DP voltage swing and pre-emphasis control */
3398 static uint32_t
3399 gen7_edp_signal_levels(uint8_t train_set)
3400 {
3401 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3402 DP_TRAIN_PRE_EMPHASIS_MASK);
3403 switch (signal_levels) {
3404 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3405 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3406 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3407 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3409 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3410
3411 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3412 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3413 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3414 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3415
3416 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3417 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3419 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3420
3421 default:
3422 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3423 "0x%x\n", signal_levels);
3424 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3425 }
3426 }
3427
3428 void
3429 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3430 {
3431 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3432 enum port port = intel_dig_port->port;
3433 struct drm_device *dev = intel_dig_port->base.base.dev;
3434 struct drm_i915_private *dev_priv = to_i915(dev);
3435 uint32_t signal_levels, mask = 0;
3436 uint8_t train_set = intel_dp->train_set[0];
3437
3438 if (HAS_DDI(dev_priv)) {
3439 signal_levels = ddi_signal_levels(intel_dp);
3440
3441 if (IS_GEN9_LP(dev_priv))
3442 signal_levels = 0;
3443 else
3444 mask = DDI_BUF_EMP_MASK;
3445 } else if (IS_CHERRYVIEW(dev_priv)) {
3446 signal_levels = chv_signal_levels(intel_dp);
3447 } else if (IS_VALLEYVIEW(dev_priv)) {
3448 signal_levels = vlv_signal_levels(intel_dp);
3449 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3450 signal_levels = gen7_edp_signal_levels(train_set);
3451 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3452 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3453 signal_levels = gen6_edp_signal_levels(train_set);
3454 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3455 } else {
3456 signal_levels = gen4_signal_levels(train_set);
3457 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3458 }
3459
3460 if (mask)
3461 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3462
3463 DRM_DEBUG_KMS("Using vswing level %d\n",
3464 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3465 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3466 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3467 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3468
3469 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3470
3471 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3472 POSTING_READ(intel_dp->output_reg);
3473 }
3474
3475 void
3476 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3477 uint8_t dp_train_pat)
3478 {
3479 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3480 struct drm_i915_private *dev_priv =
3481 to_i915(intel_dig_port->base.base.dev);
3482
3483 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3484
3485 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3486 POSTING_READ(intel_dp->output_reg);
3487 }
3488
3489 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3490 {
3491 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3492 struct drm_device *dev = intel_dig_port->base.base.dev;
3493 struct drm_i915_private *dev_priv = to_i915(dev);
3494 enum port port = intel_dig_port->port;
3495 uint32_t val;
3496
3497 if (!HAS_DDI(dev_priv))
3498 return;
3499
3500 val = I915_READ(DP_TP_CTL(port));
3501 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3502 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3503 I915_WRITE(DP_TP_CTL(port), val);
3504
3505 /*
3506 * On PORT_A we can have only eDP in SST mode. There the only reason
3507 * we need to set idle transmission mode is to work around a HW issue
3508 * where we enable the pipe while not in idle link-training mode.
3509 * In this case there is requirement to wait for a minimum number of
3510 * idle patterns to be sent.
3511 */
3512 if (port == PORT_A)
3513 return;
3514
3515 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3516 DP_TP_STATUS_IDLE_DONE,
3517 DP_TP_STATUS_IDLE_DONE,
3518 1))
3519 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3520 }
3521
3522 static void
3523 intel_dp_link_down(struct intel_dp *intel_dp)
3524 {
3525 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3526 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3527 enum port port = intel_dig_port->port;
3528 struct drm_device *dev = intel_dig_port->base.base.dev;
3529 struct drm_i915_private *dev_priv = to_i915(dev);
3530 uint32_t DP = intel_dp->DP;
3531
3532 if (WARN_ON(HAS_DDI(dev_priv)))
3533 return;
3534
3535 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3536 return;
3537
3538 DRM_DEBUG_KMS("\n");
3539
3540 if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3541 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3542 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3543 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3544 } else {
3545 if (IS_CHERRYVIEW(dev_priv))
3546 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3547 else
3548 DP &= ~DP_LINK_TRAIN_MASK;
3549 DP |= DP_LINK_TRAIN_PAT_IDLE;
3550 }
3551 I915_WRITE(intel_dp->output_reg, DP);
3552 POSTING_READ(intel_dp->output_reg);
3553
3554 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3555 I915_WRITE(intel_dp->output_reg, DP);
3556 POSTING_READ(intel_dp->output_reg);
3557
3558 /*
3559 * HW workaround for IBX, we need to move the port
3560 * to transcoder A after disabling it to allow the
3561 * matching HDMI port to be enabled on transcoder A.
3562 */
3563 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3564 /*
3565 * We get CPU/PCH FIFO underruns on the other pipe when
3566 * doing the workaround. Sweep them under the rug.
3567 */
3568 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3569 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3570
3571 /* always enable with pattern 1 (as per spec) */
3572 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3573 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3574 I915_WRITE(intel_dp->output_reg, DP);
3575 POSTING_READ(intel_dp->output_reg);
3576
3577 DP &= ~DP_PORT_EN;
3578 I915_WRITE(intel_dp->output_reg, DP);
3579 POSTING_READ(intel_dp->output_reg);
3580
3581 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3582 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3583 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3584 }
3585
3586 msleep(intel_dp->panel_power_down_delay);
3587
3588 intel_dp->DP = DP;
3589
3590 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3591 pps_lock(intel_dp);
3592 intel_dp->active_pipe = INVALID_PIPE;
3593 pps_unlock(intel_dp);
3594 }
3595 }
3596
3597 bool
3598 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3599 {
3600 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3601 sizeof(intel_dp->dpcd)) < 0)
3602 return false; /* aux transfer failed */
3603
3604 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3605
3606 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3607 }
3608
3609 static bool
3610 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3611 {
3612 struct drm_i915_private *dev_priv =
3613 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3614
3615 /* this function is meant to be called only once */
3616 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3617
3618 if (!intel_dp_read_dpcd(intel_dp))
3619 return false;
3620
3621 intel_dp_read_desc(intel_dp);
3622
3623 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3624 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3625 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3626
3627 /* Check if the panel supports PSR */
3628 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3629 intel_dp->psr_dpcd,
3630 sizeof(intel_dp->psr_dpcd));
3631 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3632 dev_priv->psr.sink_support = true;
3633 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3634 }
3635
3636 if (INTEL_GEN(dev_priv) >= 9 &&
3637 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3638 uint8_t frame_sync_cap;
3639
3640 dev_priv->psr.sink_support = true;
3641 drm_dp_dpcd_read(&intel_dp->aux,
3642 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3643 &frame_sync_cap, 1);
3644 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3645 /* PSR2 needs frame sync as well */
3646 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3647 DRM_DEBUG_KMS("PSR2 %s on sink",
3648 dev_priv->psr.psr2_support ? "supported" : "not supported");
3649
3650 if (dev_priv->psr.psr2_support) {
3651 dev_priv->psr.y_cord_support =
3652 intel_dp_get_y_cord_status(intel_dp);
3653 dev_priv->psr.colorimetry_support =
3654 intel_dp_get_colorimetry_status(intel_dp);
3655 dev_priv->psr.alpm =
3656 intel_dp_get_alpm_status(intel_dp);
3657 }
3658
3659 }
3660
3661 /* Read the eDP Display control capabilities registers */
3662 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3663 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3664 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3665 sizeof(intel_dp->edp_dpcd))
3666 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3667 intel_dp->edp_dpcd);
3668
3669 /* Intermediate frequency support */
3670 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3671 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3672 int i;
3673
3674 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3675 sink_rates, sizeof(sink_rates));
3676
3677 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3678 int val = le16_to_cpu(sink_rates[i]);
3679
3680 if (val == 0)
3681 break;
3682
3683 /* Value read multiplied by 200kHz gives the per-lane
3684 * link rate in kHz. The source rates are, however,
3685 * stored in terms of LS_Clk kHz. The full conversion
3686 * back to symbols is
3687 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3688 */
3689 intel_dp->sink_rates[i] = (val * 200) / 10;
3690 }
3691 intel_dp->num_sink_rates = i;
3692 }
3693
3694 return true;
3695 }
3696
3697
3698 static bool
3699 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3700 {
3701 if (!intel_dp_read_dpcd(intel_dp))
3702 return false;
3703
3704 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3705 &intel_dp->sink_count, 1) < 0)
3706 return false;
3707
3708 /*
3709 * Sink count can change between short pulse hpd hence
3710 * a member variable in intel_dp will track any changes
3711 * between short pulse interrupts.
3712 */
3713 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3714
3715 /*
3716 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3717 * a dongle is present but no display. Unless we require to know
3718 * if a dongle is present or not, we don't need to update
3719 * downstream port information. So, an early return here saves
3720 * time from performing other operations which are not required.
3721 */
3722 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3723 return false;
3724
3725 if (!drm_dp_is_branch(intel_dp->dpcd))
3726 return true; /* native DP sink */
3727
3728 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3729 return true; /* no per-port downstream info */
3730
3731 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3732 intel_dp->downstream_ports,
3733 DP_MAX_DOWNSTREAM_PORTS) < 0)
3734 return false; /* downstream port status fetch failed */
3735
3736 return true;
3737 }
3738
3739 static bool
3740 intel_dp_can_mst(struct intel_dp *intel_dp)
3741 {
3742 u8 buf[1];
3743
3744 if (!i915.enable_dp_mst)
3745 return false;
3746
3747 if (!intel_dp->can_mst)
3748 return false;
3749
3750 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3751 return false;
3752
3753 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3754 return false;
3755
3756 return buf[0] & DP_MST_CAP;
3757 }
3758
3759 static void
3760 intel_dp_configure_mst(struct intel_dp *intel_dp)
3761 {
3762 if (!i915.enable_dp_mst)
3763 return;
3764
3765 if (!intel_dp->can_mst)
3766 return;
3767
3768 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3769
3770 if (intel_dp->is_mst)
3771 DRM_DEBUG_KMS("Sink is MST capable\n");
3772 else
3773 DRM_DEBUG_KMS("Sink is not MST capable\n");
3774
3775 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3776 intel_dp->is_mst);
3777 }
3778
3779 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3780 {
3781 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3782 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3783 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3784 u8 buf;
3785 int ret = 0;
3786 int count = 0;
3787 int attempts = 10;
3788
3789 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3790 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3791 ret = -EIO;
3792 goto out;
3793 }
3794
3795 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3796 buf & ~DP_TEST_SINK_START) < 0) {
3797 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3798 ret = -EIO;
3799 goto out;
3800 }
3801
3802 do {
3803 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3804
3805 if (drm_dp_dpcd_readb(&intel_dp->aux,
3806 DP_TEST_SINK_MISC, &buf) < 0) {
3807 ret = -EIO;
3808 goto out;
3809 }
3810 count = buf & DP_TEST_COUNT_MASK;
3811 } while (--attempts && count);
3812
3813 if (attempts == 0) {
3814 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3815 ret = -ETIMEDOUT;
3816 }
3817
3818 out:
3819 hsw_enable_ips(intel_crtc);
3820 return ret;
3821 }
3822
3823 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3824 {
3825 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3826 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3827 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3828 u8 buf;
3829 int ret;
3830
3831 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3832 return -EIO;
3833
3834 if (!(buf & DP_TEST_CRC_SUPPORTED))
3835 return -ENOTTY;
3836
3837 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3838 return -EIO;
3839
3840 if (buf & DP_TEST_SINK_START) {
3841 ret = intel_dp_sink_crc_stop(intel_dp);
3842 if (ret)
3843 return ret;
3844 }
3845
3846 hsw_disable_ips(intel_crtc);
3847
3848 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3849 buf | DP_TEST_SINK_START) < 0) {
3850 hsw_enable_ips(intel_crtc);
3851 return -EIO;
3852 }
3853
3854 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3855 return 0;
3856 }
3857
3858 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3859 {
3860 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3861 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3862 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3863 u8 buf;
3864 int count, ret;
3865 int attempts = 6;
3866
3867 ret = intel_dp_sink_crc_start(intel_dp);
3868 if (ret)
3869 return ret;
3870
3871 do {
3872 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3873
3874 if (drm_dp_dpcd_readb(&intel_dp->aux,
3875 DP_TEST_SINK_MISC, &buf) < 0) {
3876 ret = -EIO;
3877 goto stop;
3878 }
3879 count = buf & DP_TEST_COUNT_MASK;
3880
3881 } while (--attempts && count == 0);
3882
3883 if (attempts == 0) {
3884 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3885 ret = -ETIMEDOUT;
3886 goto stop;
3887 }
3888
3889 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3890 ret = -EIO;
3891 goto stop;
3892 }
3893
3894 stop:
3895 intel_dp_sink_crc_stop(intel_dp);
3896 return ret;
3897 }
3898
3899 static bool
3900 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3901 {
3902 return drm_dp_dpcd_read(&intel_dp->aux,
3903 DP_DEVICE_SERVICE_IRQ_VECTOR,
3904 sink_irq_vector, 1) == 1;
3905 }
3906
3907 static bool
3908 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3909 {
3910 int ret;
3911
3912 ret = drm_dp_dpcd_read(&intel_dp->aux,
3913 DP_SINK_COUNT_ESI,
3914 sink_irq_vector, 14);
3915 if (ret != 14)
3916 return false;
3917
3918 return true;
3919 }
3920
3921 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3922 {
3923 uint8_t test_result = DP_TEST_ACK;
3924 return test_result;
3925 }
3926
3927 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3928 {
3929 uint8_t test_result = DP_TEST_NAK;
3930 return test_result;
3931 }
3932
3933 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3934 {
3935 uint8_t test_result = DP_TEST_NAK;
3936 struct intel_connector *intel_connector = intel_dp->attached_connector;
3937 struct drm_connector *connector = &intel_connector->base;
3938
3939 if (intel_connector->detect_edid == NULL ||
3940 connector->edid_corrupt ||
3941 intel_dp->aux.i2c_defer_count > 6) {
3942 /* Check EDID read for NACKs, DEFERs and corruption
3943 * (DP CTS 1.2 Core r1.1)
3944 * 4.2.2.4 : Failed EDID read, I2C_NAK
3945 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3946 * 4.2.2.6 : EDID corruption detected
3947 * Use failsafe mode for all cases
3948 */
3949 if (intel_dp->aux.i2c_nack_count > 0 ||
3950 intel_dp->aux.i2c_defer_count > 0)
3951 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3952 intel_dp->aux.i2c_nack_count,
3953 intel_dp->aux.i2c_defer_count);
3954 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3955 } else {
3956 struct edid *block = intel_connector->detect_edid;
3957
3958 /* We have to write the checksum
3959 * of the last block read
3960 */
3961 block += intel_connector->detect_edid->extensions;
3962
3963 if (!drm_dp_dpcd_write(&intel_dp->aux,
3964 DP_TEST_EDID_CHECKSUM,
3965 &block->checksum,
3966 1))
3967 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3968
3969 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3970 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_STANDARD;
3971 }
3972
3973 /* Set test active flag here so userspace doesn't interrupt things */
3974 intel_dp->compliance.test_active = 1;
3975
3976 return test_result;
3977 }
3978
3979 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3980 {
3981 uint8_t test_result = DP_TEST_NAK;
3982 return test_result;
3983 }
3984
3985 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3986 {
3987 uint8_t response = DP_TEST_NAK;
3988 uint8_t rxdata = 0;
3989 int status = 0;
3990
3991 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3992 if (status <= 0) {
3993 DRM_DEBUG_KMS("Could not read test request from sink\n");
3994 goto update_status;
3995 }
3996
3997 switch (rxdata) {
3998 case DP_TEST_LINK_TRAINING:
3999 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4000 intel_dp->compliance.test_type = DP_TEST_LINK_TRAINING;
4001 response = intel_dp_autotest_link_training(intel_dp);
4002 break;
4003 case DP_TEST_LINK_VIDEO_PATTERN:
4004 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4005 intel_dp->compliance.test_type = DP_TEST_LINK_VIDEO_PATTERN;
4006 response = intel_dp_autotest_video_pattern(intel_dp);
4007 break;
4008 case DP_TEST_LINK_EDID_READ:
4009 DRM_DEBUG_KMS("EDID test requested\n");
4010 intel_dp->compliance.test_type = DP_TEST_LINK_EDID_READ;
4011 response = intel_dp_autotest_edid(intel_dp);
4012 break;
4013 case DP_TEST_LINK_PHY_TEST_PATTERN:
4014 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4015 intel_dp->compliance.test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4016 response = intel_dp_autotest_phy_pattern(intel_dp);
4017 break;
4018 default:
4019 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4020 break;
4021 }
4022
4023 update_status:
4024 status = drm_dp_dpcd_write(&intel_dp->aux,
4025 DP_TEST_RESPONSE,
4026 &response, 1);
4027 if (status <= 0)
4028 DRM_DEBUG_KMS("Could not write test response to sink\n");
4029 }
4030
4031 static int
4032 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4033 {
4034 bool bret;
4035
4036 if (intel_dp->is_mst) {
4037 u8 esi[16] = { 0 };
4038 int ret = 0;
4039 int retry;
4040 bool handled;
4041 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4042 go_again:
4043 if (bret == true) {
4044
4045 /* check link status - esi[10] = 0x200c */
4046 if (intel_dp->active_mst_links &&
4047 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4048 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4049 intel_dp_start_link_train(intel_dp);
4050 intel_dp_stop_link_train(intel_dp);
4051 }
4052
4053 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4054 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4055
4056 if (handled) {
4057 for (retry = 0; retry < 3; retry++) {
4058 int wret;
4059 wret = drm_dp_dpcd_write(&intel_dp->aux,
4060 DP_SINK_COUNT_ESI+1,
4061 &esi[1], 3);
4062 if (wret == 3) {
4063 break;
4064 }
4065 }
4066
4067 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4068 if (bret == true) {
4069 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4070 goto go_again;
4071 }
4072 } else
4073 ret = 0;
4074
4075 return ret;
4076 } else {
4077 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4078 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4079 intel_dp->is_mst = false;
4080 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4081 /* send a hotplug event */
4082 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4083 }
4084 }
4085 return -EINVAL;
4086 }
4087
4088 static void
4089 intel_dp_retrain_link(struct intel_dp *intel_dp)
4090 {
4091 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4093 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4094
4095 /* Suppress underruns caused by re-training */
4096 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4097 if (crtc->config->has_pch_encoder)
4098 intel_set_pch_fifo_underrun_reporting(dev_priv,
4099 intel_crtc_pch_transcoder(crtc), false);
4100
4101 intel_dp_start_link_train(intel_dp);
4102 intel_dp_stop_link_train(intel_dp);
4103
4104 /* Keep underrun reporting disabled until things are stable */
4105 intel_wait_for_vblank(dev_priv, crtc->pipe);
4106
4107 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4108 if (crtc->config->has_pch_encoder)
4109 intel_set_pch_fifo_underrun_reporting(dev_priv,
4110 intel_crtc_pch_transcoder(crtc), true);
4111 }
4112
4113 static void
4114 intel_dp_check_link_status(struct intel_dp *intel_dp)
4115 {
4116 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4117 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4118 u8 link_status[DP_LINK_STATUS_SIZE];
4119
4120 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4121
4122 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4123 DRM_ERROR("Failed to get link status\n");
4124 return;
4125 }
4126
4127 if (!intel_encoder->base.crtc)
4128 return;
4129
4130 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4131 return;
4132
4133 /* FIXME: we need to synchronize this sort of stuff with hardware
4134 * readout. Currently fast link training doesn't work on boot-up. */
4135 if (!intel_dp->lane_count)
4136 return;
4137
4138 /* if link training is requested we should perform it always */
4139 if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) ||
4140 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4141 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4142 intel_encoder->base.name);
4143
4144 intel_dp_retrain_link(intel_dp);
4145 }
4146 }
4147
4148 /*
4149 * According to DP spec
4150 * 5.1.2:
4151 * 1. Read DPCD
4152 * 2. Configure link according to Receiver Capabilities
4153 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4154 * 4. Check link status on receipt of hot-plug interrupt
4155 *
4156 * intel_dp_short_pulse - handles short pulse interrupts
4157 * when full detection is not required.
4158 * Returns %true if short pulse is handled and full detection
4159 * is NOT required and %false otherwise.
4160 */
4161 static bool
4162 intel_dp_short_pulse(struct intel_dp *intel_dp)
4163 {
4164 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4165 u8 sink_irq_vector = 0;
4166 u8 old_sink_count = intel_dp->sink_count;
4167 bool ret;
4168
4169 /*
4170 * Clearing compliance test variables to allow capturing
4171 * of values for next automated test request.
4172 */
4173 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4174
4175 /*
4176 * Now read the DPCD to see if it's actually running
4177 * If the current value of sink count doesn't match with
4178 * the value that was stored earlier or dpcd read failed
4179 * we need to do full detection
4180 */
4181 ret = intel_dp_get_dpcd(intel_dp);
4182
4183 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4184 /* No need to proceed if we are going to do full detect */
4185 return false;
4186 }
4187
4188 /* Try to read the source of the interrupt */
4189 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4190 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4191 sink_irq_vector != 0) {
4192 /* Clear interrupt source */
4193 drm_dp_dpcd_writeb(&intel_dp->aux,
4194 DP_DEVICE_SERVICE_IRQ_VECTOR,
4195 sink_irq_vector);
4196
4197 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4198 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4199 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4200 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4201 }
4202
4203 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4204 intel_dp_check_link_status(intel_dp);
4205 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4206
4207 return true;
4208 }
4209
4210 /* XXX this is probably wrong for multiple downstream ports */
4211 static enum drm_connector_status
4212 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4213 {
4214 uint8_t *dpcd = intel_dp->dpcd;
4215 uint8_t type;
4216
4217 if (!intel_dp_get_dpcd(intel_dp))
4218 return connector_status_disconnected;
4219
4220 if (is_edp(intel_dp))
4221 return connector_status_connected;
4222
4223 /* if there's no downstream port, we're done */
4224 if (!drm_dp_is_branch(dpcd))
4225 return connector_status_connected;
4226
4227 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4228 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4229 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4230
4231 return intel_dp->sink_count ?
4232 connector_status_connected : connector_status_disconnected;
4233 }
4234
4235 if (intel_dp_can_mst(intel_dp))
4236 return connector_status_connected;
4237
4238 /* If no HPD, poke DDC gently */
4239 if (drm_probe_ddc(&intel_dp->aux.ddc))
4240 return connector_status_connected;
4241
4242 /* Well we tried, say unknown for unreliable port types */
4243 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4244 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4245 if (type == DP_DS_PORT_TYPE_VGA ||
4246 type == DP_DS_PORT_TYPE_NON_EDID)
4247 return connector_status_unknown;
4248 } else {
4249 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4250 DP_DWN_STRM_PORT_TYPE_MASK;
4251 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4252 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4253 return connector_status_unknown;
4254 }
4255
4256 /* Anything else is out of spec, warn and ignore */
4257 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4258 return connector_status_disconnected;
4259 }
4260
4261 static enum drm_connector_status
4262 edp_detect(struct intel_dp *intel_dp)
4263 {
4264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4265 struct drm_i915_private *dev_priv = to_i915(dev);
4266 enum drm_connector_status status;
4267
4268 status = intel_panel_detect(dev_priv);
4269 if (status == connector_status_unknown)
4270 status = connector_status_connected;
4271
4272 return status;
4273 }
4274
4275 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4276 struct intel_digital_port *port)
4277 {
4278 u32 bit;
4279
4280 switch (port->port) {
4281 case PORT_A:
4282 return true;
4283 case PORT_B:
4284 bit = SDE_PORTB_HOTPLUG;
4285 break;
4286 case PORT_C:
4287 bit = SDE_PORTC_HOTPLUG;
4288 break;
4289 case PORT_D:
4290 bit = SDE_PORTD_HOTPLUG;
4291 break;
4292 default:
4293 MISSING_CASE(port->port);
4294 return false;
4295 }
4296
4297 return I915_READ(SDEISR) & bit;
4298 }
4299
4300 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4301 struct intel_digital_port *port)
4302 {
4303 u32 bit;
4304
4305 switch (port->port) {
4306 case PORT_A:
4307 return true;
4308 case PORT_B:
4309 bit = SDE_PORTB_HOTPLUG_CPT;
4310 break;
4311 case PORT_C:
4312 bit = SDE_PORTC_HOTPLUG_CPT;
4313 break;
4314 case PORT_D:
4315 bit = SDE_PORTD_HOTPLUG_CPT;
4316 break;
4317 case PORT_E:
4318 bit = SDE_PORTE_HOTPLUG_SPT;
4319 break;
4320 default:
4321 MISSING_CASE(port->port);
4322 return false;
4323 }
4324
4325 return I915_READ(SDEISR) & bit;
4326 }
4327
4328 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4329 struct intel_digital_port *port)
4330 {
4331 u32 bit;
4332
4333 switch (port->port) {
4334 case PORT_B:
4335 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4336 break;
4337 case PORT_C:
4338 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4339 break;
4340 case PORT_D:
4341 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4342 break;
4343 default:
4344 MISSING_CASE(port->port);
4345 return false;
4346 }
4347
4348 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4349 }
4350
4351 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4352 struct intel_digital_port *port)
4353 {
4354 u32 bit;
4355
4356 switch (port->port) {
4357 case PORT_B:
4358 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4359 break;
4360 case PORT_C:
4361 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4362 break;
4363 case PORT_D:
4364 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4365 break;
4366 default:
4367 MISSING_CASE(port->port);
4368 return false;
4369 }
4370
4371 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4372 }
4373
4374 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4375 struct intel_digital_port *intel_dig_port)
4376 {
4377 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4378 enum port port;
4379 u32 bit;
4380
4381 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4382 switch (port) {
4383 case PORT_A:
4384 bit = BXT_DE_PORT_HP_DDIA;
4385 break;
4386 case PORT_B:
4387 bit = BXT_DE_PORT_HP_DDIB;
4388 break;
4389 case PORT_C:
4390 bit = BXT_DE_PORT_HP_DDIC;
4391 break;
4392 default:
4393 MISSING_CASE(port);
4394 return false;
4395 }
4396
4397 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4398 }
4399
4400 /*
4401 * intel_digital_port_connected - is the specified port connected?
4402 * @dev_priv: i915 private structure
4403 * @port: the port to test
4404 *
4405 * Return %true if @port is connected, %false otherwise.
4406 */
4407 static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4408 struct intel_digital_port *port)
4409 {
4410 if (HAS_PCH_IBX(dev_priv))
4411 return ibx_digital_port_connected(dev_priv, port);
4412 else if (HAS_PCH_SPLIT(dev_priv))
4413 return cpt_digital_port_connected(dev_priv, port);
4414 else if (IS_GEN9_LP(dev_priv))
4415 return bxt_digital_port_connected(dev_priv, port);
4416 else if (IS_GM45(dev_priv))
4417 return gm45_digital_port_connected(dev_priv, port);
4418 else
4419 return g4x_digital_port_connected(dev_priv, port);
4420 }
4421
4422 static struct edid *
4423 intel_dp_get_edid(struct intel_dp *intel_dp)
4424 {
4425 struct intel_connector *intel_connector = intel_dp->attached_connector;
4426
4427 /* use cached edid if we have one */
4428 if (intel_connector->edid) {
4429 /* invalid edid */
4430 if (IS_ERR(intel_connector->edid))
4431 return NULL;
4432
4433 return drm_edid_duplicate(intel_connector->edid);
4434 } else
4435 return drm_get_edid(&intel_connector->base,
4436 &intel_dp->aux.ddc);
4437 }
4438
4439 static void
4440 intel_dp_set_edid(struct intel_dp *intel_dp)
4441 {
4442 struct intel_connector *intel_connector = intel_dp->attached_connector;
4443 struct edid *edid;
4444
4445 intel_dp_unset_edid(intel_dp);
4446 edid = intel_dp_get_edid(intel_dp);
4447 intel_connector->detect_edid = edid;
4448
4449 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4450 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4451 else
4452 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4453 }
4454
4455 static void
4456 intel_dp_unset_edid(struct intel_dp *intel_dp)
4457 {
4458 struct intel_connector *intel_connector = intel_dp->attached_connector;
4459
4460 kfree(intel_connector->detect_edid);
4461 intel_connector->detect_edid = NULL;
4462
4463 intel_dp->has_audio = false;
4464 }
4465
4466 static enum drm_connector_status
4467 intel_dp_long_pulse(struct intel_connector *intel_connector)
4468 {
4469 struct drm_connector *connector = &intel_connector->base;
4470 struct intel_dp *intel_dp = intel_attached_dp(connector);
4471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4472 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4473 struct drm_device *dev = connector->dev;
4474 enum drm_connector_status status;
4475 enum intel_display_power_domain power_domain;
4476 u8 sink_irq_vector = 0;
4477
4478 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4479 intel_display_power_get(to_i915(dev), power_domain);
4480
4481 /* Can't disconnect eDP, but you can close the lid... */
4482 if (is_edp(intel_dp))
4483 status = edp_detect(intel_dp);
4484 else if (intel_digital_port_connected(to_i915(dev),
4485 dp_to_dig_port(intel_dp)))
4486 status = intel_dp_detect_dpcd(intel_dp);
4487 else
4488 status = connector_status_disconnected;
4489
4490 if (status == connector_status_disconnected) {
4491 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4492
4493 if (intel_dp->is_mst) {
4494 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4495 intel_dp->is_mst,
4496 intel_dp->mst_mgr.mst_state);
4497 intel_dp->is_mst = false;
4498 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4499 intel_dp->is_mst);
4500 }
4501
4502 goto out;
4503 }
4504
4505 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4506 intel_encoder->type = INTEL_OUTPUT_DP;
4507
4508 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4509 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4510 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4511
4512 /* Set the max lane count for sink */
4513 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
4514
4515 /* Set the max link BW for sink */
4516 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
4517
4518 intel_dp_print_rates(intel_dp);
4519
4520 intel_dp_read_desc(intel_dp);
4521
4522 intel_dp_configure_mst(intel_dp);
4523
4524 if (intel_dp->is_mst) {
4525 /*
4526 * If we are in MST mode then this connector
4527 * won't appear connected or have anything
4528 * with EDID on it
4529 */
4530 status = connector_status_disconnected;
4531 goto out;
4532 } else if (connector->status == connector_status_connected) {
4533 /*
4534 * If display was connected already and is still connected
4535 * check links status, there has been known issues of
4536 * link loss triggerring long pulse!!!!
4537 */
4538 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4539 intel_dp_check_link_status(intel_dp);
4540 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4541 goto out;
4542 }
4543
4544 /*
4545 * Clearing NACK and defer counts to get their exact values
4546 * while reading EDID which are required by Compliance tests
4547 * 4.2.2.4 and 4.2.2.5
4548 */
4549 intel_dp->aux.i2c_nack_count = 0;
4550 intel_dp->aux.i2c_defer_count = 0;
4551
4552 intel_dp_set_edid(intel_dp);
4553 if (is_edp(intel_dp) || intel_connector->detect_edid)
4554 status = connector_status_connected;
4555 intel_dp->detect_done = true;
4556
4557 /* Try to read the source of the interrupt */
4558 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4559 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4560 sink_irq_vector != 0) {
4561 /* Clear interrupt source */
4562 drm_dp_dpcd_writeb(&intel_dp->aux,
4563 DP_DEVICE_SERVICE_IRQ_VECTOR,
4564 sink_irq_vector);
4565
4566 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4567 intel_dp_handle_test_request(intel_dp);
4568 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4569 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4570 }
4571
4572 out:
4573 if (status != connector_status_connected && !intel_dp->is_mst)
4574 intel_dp_unset_edid(intel_dp);
4575
4576 intel_display_power_put(to_i915(dev), power_domain);
4577 return status;
4578 }
4579
4580 static enum drm_connector_status
4581 intel_dp_detect(struct drm_connector *connector, bool force)
4582 {
4583 struct intel_dp *intel_dp = intel_attached_dp(connector);
4584 enum drm_connector_status status = connector->status;
4585
4586 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4587 connector->base.id, connector->name);
4588
4589 /* If full detect is not performed yet, do a full detect */
4590 if (!intel_dp->detect_done)
4591 status = intel_dp_long_pulse(intel_dp->attached_connector);
4592
4593 intel_dp->detect_done = false;
4594
4595 return status;
4596 }
4597
4598 static void
4599 intel_dp_force(struct drm_connector *connector)
4600 {
4601 struct intel_dp *intel_dp = intel_attached_dp(connector);
4602 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4603 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4604 enum intel_display_power_domain power_domain;
4605
4606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4607 connector->base.id, connector->name);
4608 intel_dp_unset_edid(intel_dp);
4609
4610 if (connector->status != connector_status_connected)
4611 return;
4612
4613 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4614 intel_display_power_get(dev_priv, power_domain);
4615
4616 intel_dp_set_edid(intel_dp);
4617
4618 intel_display_power_put(dev_priv, power_domain);
4619
4620 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4621 intel_encoder->type = INTEL_OUTPUT_DP;
4622 }
4623
4624 static int intel_dp_get_modes(struct drm_connector *connector)
4625 {
4626 struct intel_connector *intel_connector = to_intel_connector(connector);
4627 struct edid *edid;
4628
4629 edid = intel_connector->detect_edid;
4630 if (edid) {
4631 int ret = intel_connector_update_modes(connector, edid);
4632 if (ret)
4633 return ret;
4634 }
4635
4636 /* if eDP has no EDID, fall back to fixed mode */
4637 if (is_edp(intel_attached_dp(connector)) &&
4638 intel_connector->panel.fixed_mode) {
4639 struct drm_display_mode *mode;
4640
4641 mode = drm_mode_duplicate(connector->dev,
4642 intel_connector->panel.fixed_mode);
4643 if (mode) {
4644 drm_mode_probed_add(connector, mode);
4645 return 1;
4646 }
4647 }
4648
4649 return 0;
4650 }
4651
4652 static bool
4653 intel_dp_detect_audio(struct drm_connector *connector)
4654 {
4655 bool has_audio = false;
4656 struct edid *edid;
4657
4658 edid = to_intel_connector(connector)->detect_edid;
4659 if (edid)
4660 has_audio = drm_detect_monitor_audio(edid);
4661
4662 return has_audio;
4663 }
4664
4665 static int
4666 intel_dp_set_property(struct drm_connector *connector,
4667 struct drm_property *property,
4668 uint64_t val)
4669 {
4670 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4671 struct intel_connector *intel_connector = to_intel_connector(connector);
4672 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4673 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4674 int ret;
4675
4676 ret = drm_object_property_set_value(&connector->base, property, val);
4677 if (ret)
4678 return ret;
4679
4680 if (property == dev_priv->force_audio_property) {
4681 int i = val;
4682 bool has_audio;
4683
4684 if (i == intel_dp->force_audio)
4685 return 0;
4686
4687 intel_dp->force_audio = i;
4688
4689 if (i == HDMI_AUDIO_AUTO)
4690 has_audio = intel_dp_detect_audio(connector);
4691 else
4692 has_audio = (i == HDMI_AUDIO_ON);
4693
4694 if (has_audio == intel_dp->has_audio)
4695 return 0;
4696
4697 intel_dp->has_audio = has_audio;
4698 goto done;
4699 }
4700
4701 if (property == dev_priv->broadcast_rgb_property) {
4702 bool old_auto = intel_dp->color_range_auto;
4703 bool old_range = intel_dp->limited_color_range;
4704
4705 switch (val) {
4706 case INTEL_BROADCAST_RGB_AUTO:
4707 intel_dp->color_range_auto = true;
4708 break;
4709 case INTEL_BROADCAST_RGB_FULL:
4710 intel_dp->color_range_auto = false;
4711 intel_dp->limited_color_range = false;
4712 break;
4713 case INTEL_BROADCAST_RGB_LIMITED:
4714 intel_dp->color_range_auto = false;
4715 intel_dp->limited_color_range = true;
4716 break;
4717 default:
4718 return -EINVAL;
4719 }
4720
4721 if (old_auto == intel_dp->color_range_auto &&
4722 old_range == intel_dp->limited_color_range)
4723 return 0;
4724
4725 goto done;
4726 }
4727
4728 if (is_edp(intel_dp) &&
4729 property == connector->dev->mode_config.scaling_mode_property) {
4730 if (val == DRM_MODE_SCALE_NONE) {
4731 DRM_DEBUG_KMS("no scaling not supported\n");
4732 return -EINVAL;
4733 }
4734 if (HAS_GMCH_DISPLAY(dev_priv) &&
4735 val == DRM_MODE_SCALE_CENTER) {
4736 DRM_DEBUG_KMS("centering not supported\n");
4737 return -EINVAL;
4738 }
4739
4740 if (intel_connector->panel.fitting_mode == val) {
4741 /* the eDP scaling property is not changed */
4742 return 0;
4743 }
4744 intel_connector->panel.fitting_mode = val;
4745
4746 goto done;
4747 }
4748
4749 return -EINVAL;
4750
4751 done:
4752 if (intel_encoder->base.crtc)
4753 intel_crtc_restore_mode(intel_encoder->base.crtc);
4754
4755 return 0;
4756 }
4757
4758 static int
4759 intel_dp_connector_register(struct drm_connector *connector)
4760 {
4761 struct intel_dp *intel_dp = intel_attached_dp(connector);
4762 int ret;
4763
4764 ret = intel_connector_register(connector);
4765 if (ret)
4766 return ret;
4767
4768 i915_debugfs_connector_add(connector);
4769
4770 DRM_DEBUG_KMS("registering %s bus for %s\n",
4771 intel_dp->aux.name, connector->kdev->kobj.name);
4772
4773 intel_dp->aux.dev = connector->kdev;
4774 return drm_dp_aux_register(&intel_dp->aux);
4775 }
4776
4777 static void
4778 intel_dp_connector_unregister(struct drm_connector *connector)
4779 {
4780 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4781 intel_connector_unregister(connector);
4782 }
4783
4784 static void
4785 intel_dp_connector_destroy(struct drm_connector *connector)
4786 {
4787 struct intel_connector *intel_connector = to_intel_connector(connector);
4788
4789 kfree(intel_connector->detect_edid);
4790
4791 if (!IS_ERR_OR_NULL(intel_connector->edid))
4792 kfree(intel_connector->edid);
4793
4794 /* Can't call is_edp() since the encoder may have been destroyed
4795 * already. */
4796 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4797 intel_panel_fini(&intel_connector->panel);
4798
4799 drm_connector_cleanup(connector);
4800 kfree(connector);
4801 }
4802
4803 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4804 {
4805 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4806 struct intel_dp *intel_dp = &intel_dig_port->dp;
4807
4808 intel_dp_mst_encoder_cleanup(intel_dig_port);
4809 if (is_edp(intel_dp)) {
4810 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4811 /*
4812 * vdd might still be enabled do to the delayed vdd off.
4813 * Make sure vdd is actually turned off here.
4814 */
4815 pps_lock(intel_dp);
4816 edp_panel_vdd_off_sync(intel_dp);
4817 pps_unlock(intel_dp);
4818
4819 if (intel_dp->edp_notifier.notifier_call) {
4820 unregister_reboot_notifier(&intel_dp->edp_notifier);
4821 intel_dp->edp_notifier.notifier_call = NULL;
4822 }
4823 }
4824
4825 intel_dp_aux_fini(intel_dp);
4826
4827 drm_encoder_cleanup(encoder);
4828 kfree(intel_dig_port);
4829 }
4830
4831 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4832 {
4833 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4834
4835 if (!is_edp(intel_dp))
4836 return;
4837
4838 /*
4839 * vdd might still be enabled do to the delayed vdd off.
4840 * Make sure vdd is actually turned off here.
4841 */
4842 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4843 pps_lock(intel_dp);
4844 edp_panel_vdd_off_sync(intel_dp);
4845 pps_unlock(intel_dp);
4846 }
4847
4848 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4849 {
4850 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4851 struct drm_device *dev = intel_dig_port->base.base.dev;
4852 struct drm_i915_private *dev_priv = to_i915(dev);
4853 enum intel_display_power_domain power_domain;
4854
4855 lockdep_assert_held(&dev_priv->pps_mutex);
4856
4857 if (!edp_have_panel_vdd(intel_dp))
4858 return;
4859
4860 /*
4861 * The VDD bit needs a power domain reference, so if the bit is
4862 * already enabled when we boot or resume, grab this reference and
4863 * schedule a vdd off, so we don't hold on to the reference
4864 * indefinitely.
4865 */
4866 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4867 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4868 intel_display_power_get(dev_priv, power_domain);
4869
4870 edp_panel_vdd_schedule_off(intel_dp);
4871 }
4872
4873 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
4874 {
4875 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4876
4877 if ((intel_dp->DP & DP_PORT_EN) == 0)
4878 return INVALID_PIPE;
4879
4880 if (IS_CHERRYVIEW(dev_priv))
4881 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4882 else
4883 return PORT_TO_PIPE(intel_dp->DP);
4884 }
4885
4886 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4887 {
4888 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4889 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4890 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4891
4892 if (!HAS_DDI(dev_priv))
4893 intel_dp->DP = I915_READ(intel_dp->output_reg);
4894
4895 if (lspcon->active)
4896 lspcon_resume(lspcon);
4897
4898 pps_lock(intel_dp);
4899
4900 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4901 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
4902
4903 if (is_edp(intel_dp)) {
4904 /* Reinit the power sequencer, in case BIOS did something with it. */
4905 intel_dp_pps_init(encoder->dev, intel_dp);
4906 intel_edp_panel_vdd_sanitize(intel_dp);
4907 }
4908
4909 pps_unlock(intel_dp);
4910 }
4911
4912 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4913 .dpms = drm_atomic_helper_connector_dpms,
4914 .detect = intel_dp_detect,
4915 .force = intel_dp_force,
4916 .fill_modes = drm_helper_probe_single_connector_modes,
4917 .set_property = intel_dp_set_property,
4918 .atomic_get_property = intel_connector_atomic_get_property,
4919 .late_register = intel_dp_connector_register,
4920 .early_unregister = intel_dp_connector_unregister,
4921 .destroy = intel_dp_connector_destroy,
4922 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4923 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4924 };
4925
4926 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4927 .get_modes = intel_dp_get_modes,
4928 .mode_valid = intel_dp_mode_valid,
4929 };
4930
4931 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4932 .reset = intel_dp_encoder_reset,
4933 .destroy = intel_dp_encoder_destroy,
4934 };
4935
4936 enum irqreturn
4937 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4938 {
4939 struct intel_dp *intel_dp = &intel_dig_port->dp;
4940 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4941 struct drm_device *dev = intel_dig_port->base.base.dev;
4942 struct drm_i915_private *dev_priv = to_i915(dev);
4943 enum intel_display_power_domain power_domain;
4944 enum irqreturn ret = IRQ_NONE;
4945
4946 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4947 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4948 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4949
4950 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4951 /*
4952 * vdd off can generate a long pulse on eDP which
4953 * would require vdd on to handle it, and thus we
4954 * would end up in an endless cycle of
4955 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4956 */
4957 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4958 port_name(intel_dig_port->port));
4959 return IRQ_HANDLED;
4960 }
4961
4962 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4963 port_name(intel_dig_port->port),
4964 long_hpd ? "long" : "short");
4965
4966 if (long_hpd) {
4967 intel_dp->detect_done = false;
4968 return IRQ_NONE;
4969 }
4970
4971 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4972 intel_display_power_get(dev_priv, power_domain);
4973
4974 if (intel_dp->is_mst) {
4975 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4976 /*
4977 * If we were in MST mode, and device is not
4978 * there, get out of MST mode
4979 */
4980 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4981 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4982 intel_dp->is_mst = false;
4983 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4984 intel_dp->is_mst);
4985 intel_dp->detect_done = false;
4986 goto put_power;
4987 }
4988 }
4989
4990 if (!intel_dp->is_mst) {
4991 if (!intel_dp_short_pulse(intel_dp)) {
4992 intel_dp->detect_done = false;
4993 goto put_power;
4994 }
4995 }
4996
4997 ret = IRQ_HANDLED;
4998
4999 put_power:
5000 intel_display_power_put(dev_priv, power_domain);
5001
5002 return ret;
5003 }
5004
5005 /* check the VBT to see whether the eDP is on another port */
5006 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5007 {
5008 /*
5009 * eDP not supported on g4x. so bail out early just
5010 * for a bit extra safety in case the VBT is bonkers.
5011 */
5012 if (INTEL_GEN(dev_priv) < 5)
5013 return false;
5014
5015 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5016 return true;
5017
5018 return intel_bios_is_port_edp(dev_priv, port);
5019 }
5020
5021 void
5022 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5023 {
5024 struct intel_connector *intel_connector = to_intel_connector(connector);
5025
5026 intel_attach_force_audio_property(connector);
5027 intel_attach_broadcast_rgb_property(connector);
5028 intel_dp->color_range_auto = true;
5029
5030 if (is_edp(intel_dp)) {
5031 drm_mode_create_scaling_mode_property(connector->dev);
5032 drm_object_attach_property(
5033 &connector->base,
5034 connector->dev->mode_config.scaling_mode_property,
5035 DRM_MODE_SCALE_ASPECT);
5036 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5037 }
5038 }
5039
5040 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5041 {
5042 intel_dp->panel_power_off_time = ktime_get_boottime();
5043 intel_dp->last_power_on = jiffies;
5044 intel_dp->last_backlight_off = jiffies;
5045 }
5046
5047 static void
5048 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5049 struct intel_dp *intel_dp, struct edp_power_seq *seq)
5050 {
5051 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5052 struct pps_registers regs;
5053
5054 intel_pps_get_registers(dev_priv, intel_dp, &regs);
5055
5056 /* Workaround: Need to write PP_CONTROL with the unlock key as
5057 * the very first thing. */
5058 pp_ctl = ironlake_get_pp_control(intel_dp);
5059
5060 pp_on = I915_READ(regs.pp_on);
5061 pp_off = I915_READ(regs.pp_off);
5062 if (!IS_GEN9_LP(dev_priv)) {
5063 I915_WRITE(regs.pp_ctrl, pp_ctl);
5064 pp_div = I915_READ(regs.pp_div);
5065 }
5066
5067 /* Pull timing values out of registers */
5068 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5069 PANEL_POWER_UP_DELAY_SHIFT;
5070
5071 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5072 PANEL_LIGHT_ON_DELAY_SHIFT;
5073
5074 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5075 PANEL_LIGHT_OFF_DELAY_SHIFT;
5076
5077 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5078 PANEL_POWER_DOWN_DELAY_SHIFT;
5079
5080 if (IS_GEN9_LP(dev_priv)) {
5081 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5082 BXT_POWER_CYCLE_DELAY_SHIFT;
5083 if (tmp > 0)
5084 seq->t11_t12 = (tmp - 1) * 1000;
5085 else
5086 seq->t11_t12 = 0;
5087 } else {
5088 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5089 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5090 }
5091 }
5092
5093 static void
5094 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5095 {
5096 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5097 state_name,
5098 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5099 }
5100
5101 static void
5102 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5103 struct intel_dp *intel_dp)
5104 {
5105 struct edp_power_seq hw;
5106 struct edp_power_seq *sw = &intel_dp->pps_delays;
5107
5108 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5109
5110 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5111 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5112 DRM_ERROR("PPS state mismatch\n");
5113 intel_pps_dump_state("sw", sw);
5114 intel_pps_dump_state("hw", &hw);
5115 }
5116 }
5117
5118 static void
5119 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5120 struct intel_dp *intel_dp)
5121 {
5122 struct drm_i915_private *dev_priv = to_i915(dev);
5123 struct edp_power_seq cur, vbt, spec,
5124 *final = &intel_dp->pps_delays;
5125
5126 lockdep_assert_held(&dev_priv->pps_mutex);
5127
5128 /* already initialized? */
5129 if (final->t11_t12 != 0)
5130 return;
5131
5132 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5133
5134 intel_pps_dump_state("cur", &cur);
5135
5136 vbt = dev_priv->vbt.edp.pps;
5137
5138 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5139 * our hw here, which are all in 100usec. */
5140 spec.t1_t3 = 210 * 10;
5141 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5142 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5143 spec.t10 = 500 * 10;
5144 /* This one is special and actually in units of 100ms, but zero
5145 * based in the hw (so we need to add 100 ms). But the sw vbt
5146 * table multiplies it with 1000 to make it in units of 100usec,
5147 * too. */
5148 spec.t11_t12 = (510 + 100) * 10;
5149
5150 intel_pps_dump_state("vbt", &vbt);
5151
5152 /* Use the max of the register settings and vbt. If both are
5153 * unset, fall back to the spec limits. */
5154 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5155 spec.field : \
5156 max(cur.field, vbt.field))
5157 assign_final(t1_t3);
5158 assign_final(t8);
5159 assign_final(t9);
5160 assign_final(t10);
5161 assign_final(t11_t12);
5162 #undef assign_final
5163
5164 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5165 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5166 intel_dp->backlight_on_delay = get_delay(t8);
5167 intel_dp->backlight_off_delay = get_delay(t9);
5168 intel_dp->panel_power_down_delay = get_delay(t10);
5169 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5170 #undef get_delay
5171
5172 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5173 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5174 intel_dp->panel_power_cycle_delay);
5175
5176 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5177 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5178
5179 /*
5180 * We override the HW backlight delays to 1 because we do manual waits
5181 * on them. For T8, even BSpec recommends doing it. For T9, if we
5182 * don't do this, we'll end up waiting for the backlight off delay
5183 * twice: once when we do the manual sleep, and once when we disable
5184 * the panel and wait for the PP_STATUS bit to become zero.
5185 */
5186 final->t8 = 1;
5187 final->t9 = 1;
5188 }
5189
5190 static void
5191 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5192 struct intel_dp *intel_dp,
5193 bool force_disable_vdd)
5194 {
5195 struct drm_i915_private *dev_priv = to_i915(dev);
5196 u32 pp_on, pp_off, pp_div, port_sel = 0;
5197 int div = dev_priv->rawclk_freq / 1000;
5198 struct pps_registers regs;
5199 enum port port = dp_to_dig_port(intel_dp)->port;
5200 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5201
5202 lockdep_assert_held(&dev_priv->pps_mutex);
5203
5204 intel_pps_get_registers(dev_priv, intel_dp, &regs);
5205
5206 /*
5207 * On some VLV machines the BIOS can leave the VDD
5208 * enabled even on power seqeuencers which aren't
5209 * hooked up to any port. This would mess up the
5210 * power domain tracking the first time we pick
5211 * one of these power sequencers for use since
5212 * edp_panel_vdd_on() would notice that the VDD was
5213 * already on and therefore wouldn't grab the power
5214 * domain reference. Disable VDD first to avoid this.
5215 * This also avoids spuriously turning the VDD on as
5216 * soon as the new power seqeuencer gets initialized.
5217 */
5218 if (force_disable_vdd) {
5219 u32 pp = ironlake_get_pp_control(intel_dp);
5220
5221 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5222
5223 if (pp & EDP_FORCE_VDD)
5224 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5225
5226 pp &= ~EDP_FORCE_VDD;
5227
5228 I915_WRITE(regs.pp_ctrl, pp);
5229 }
5230
5231 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5232 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5233 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5234 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5235 /* Compute the divisor for the pp clock, simply match the Bspec
5236 * formula. */
5237 if (IS_GEN9_LP(dev_priv)) {
5238 pp_div = I915_READ(regs.pp_ctrl);
5239 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5240 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5241 << BXT_POWER_CYCLE_DELAY_SHIFT);
5242 } else {
5243 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5244 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5245 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5246 }
5247
5248 /* Haswell doesn't have any port selection bits for the panel
5249 * power sequencer any more. */
5250 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5251 port_sel = PANEL_PORT_SELECT_VLV(port);
5252 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5253 if (port == PORT_A)
5254 port_sel = PANEL_PORT_SELECT_DPA;
5255 else
5256 port_sel = PANEL_PORT_SELECT_DPD;
5257 }
5258
5259 pp_on |= port_sel;
5260
5261 I915_WRITE(regs.pp_on, pp_on);
5262 I915_WRITE(regs.pp_off, pp_off);
5263 if (IS_GEN9_LP(dev_priv))
5264 I915_WRITE(regs.pp_ctrl, pp_div);
5265 else
5266 I915_WRITE(regs.pp_div, pp_div);
5267
5268 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5269 I915_READ(regs.pp_on),
5270 I915_READ(regs.pp_off),
5271 IS_GEN9_LP(dev_priv) ?
5272 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5273 I915_READ(regs.pp_div));
5274 }
5275
5276 static void intel_dp_pps_init(struct drm_device *dev,
5277 struct intel_dp *intel_dp)
5278 {
5279 struct drm_i915_private *dev_priv = to_i915(dev);
5280
5281 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5282 vlv_initial_power_sequencer_setup(intel_dp);
5283 } else {
5284 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5285 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5286 }
5287 }
5288
5289 /**
5290 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5291 * @dev_priv: i915 device
5292 * @crtc_state: a pointer to the active intel_crtc_state
5293 * @refresh_rate: RR to be programmed
5294 *
5295 * This function gets called when refresh rate (RR) has to be changed from
5296 * one frequency to another. Switches can be between high and low RR
5297 * supported by the panel or to any other RR based on media playback (in
5298 * this case, RR value needs to be passed from user space).
5299 *
5300 * The caller of this function needs to take a lock on dev_priv->drrs.
5301 */
5302 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5303 struct intel_crtc_state *crtc_state,
5304 int refresh_rate)
5305 {
5306 struct intel_encoder *encoder;
5307 struct intel_digital_port *dig_port = NULL;
5308 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5310 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5311
5312 if (refresh_rate <= 0) {
5313 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5314 return;
5315 }
5316
5317 if (intel_dp == NULL) {
5318 DRM_DEBUG_KMS("DRRS not supported.\n");
5319 return;
5320 }
5321
5322 /*
5323 * FIXME: This needs proper synchronization with psr state for some
5324 * platforms that cannot have PSR and DRRS enabled at the same time.
5325 */
5326
5327 dig_port = dp_to_dig_port(intel_dp);
5328 encoder = &dig_port->base;
5329 intel_crtc = to_intel_crtc(encoder->base.crtc);
5330
5331 if (!intel_crtc) {
5332 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5333 return;
5334 }
5335
5336 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5337 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5338 return;
5339 }
5340
5341 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5342 refresh_rate)
5343 index = DRRS_LOW_RR;
5344
5345 if (index == dev_priv->drrs.refresh_rate_type) {
5346 DRM_DEBUG_KMS(
5347 "DRRS requested for previously set RR...ignoring\n");
5348 return;
5349 }
5350
5351 if (!crtc_state->base.active) {
5352 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5353 return;
5354 }
5355
5356 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5357 switch (index) {
5358 case DRRS_HIGH_RR:
5359 intel_dp_set_m_n(intel_crtc, M1_N1);
5360 break;
5361 case DRRS_LOW_RR:
5362 intel_dp_set_m_n(intel_crtc, M2_N2);
5363 break;
5364 case DRRS_MAX_RR:
5365 default:
5366 DRM_ERROR("Unsupported refreshrate type\n");
5367 }
5368 } else if (INTEL_GEN(dev_priv) > 6) {
5369 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5370 u32 val;
5371
5372 val = I915_READ(reg);
5373 if (index > DRRS_HIGH_RR) {
5374 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5375 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5376 else
5377 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5378 } else {
5379 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5380 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5381 else
5382 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5383 }
5384 I915_WRITE(reg, val);
5385 }
5386
5387 dev_priv->drrs.refresh_rate_type = index;
5388
5389 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5390 }
5391
5392 /**
5393 * intel_edp_drrs_enable - init drrs struct if supported
5394 * @intel_dp: DP struct
5395 * @crtc_state: A pointer to the active crtc state.
5396 *
5397 * Initializes frontbuffer_bits and drrs.dp
5398 */
5399 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5400 struct intel_crtc_state *crtc_state)
5401 {
5402 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5403 struct drm_i915_private *dev_priv = to_i915(dev);
5404
5405 if (!crtc_state->has_drrs) {
5406 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5407 return;
5408 }
5409
5410 mutex_lock(&dev_priv->drrs.mutex);
5411 if (WARN_ON(dev_priv->drrs.dp)) {
5412 DRM_ERROR("DRRS already enabled\n");
5413 goto unlock;
5414 }
5415
5416 dev_priv->drrs.busy_frontbuffer_bits = 0;
5417
5418 dev_priv->drrs.dp = intel_dp;
5419
5420 unlock:
5421 mutex_unlock(&dev_priv->drrs.mutex);
5422 }
5423
5424 /**
5425 * intel_edp_drrs_disable - Disable DRRS
5426 * @intel_dp: DP struct
5427 * @old_crtc_state: Pointer to old crtc_state.
5428 *
5429 */
5430 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5431 struct intel_crtc_state *old_crtc_state)
5432 {
5433 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5434 struct drm_i915_private *dev_priv = to_i915(dev);
5435
5436 if (!old_crtc_state->has_drrs)
5437 return;
5438
5439 mutex_lock(&dev_priv->drrs.mutex);
5440 if (!dev_priv->drrs.dp) {
5441 mutex_unlock(&dev_priv->drrs.mutex);
5442 return;
5443 }
5444
5445 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5446 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5447 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5448
5449 dev_priv->drrs.dp = NULL;
5450 mutex_unlock(&dev_priv->drrs.mutex);
5451
5452 cancel_delayed_work_sync(&dev_priv->drrs.work);
5453 }
5454
5455 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5456 {
5457 struct drm_i915_private *dev_priv =
5458 container_of(work, typeof(*dev_priv), drrs.work.work);
5459 struct intel_dp *intel_dp;
5460
5461 mutex_lock(&dev_priv->drrs.mutex);
5462
5463 intel_dp = dev_priv->drrs.dp;
5464
5465 if (!intel_dp)
5466 goto unlock;
5467
5468 /*
5469 * The delayed work can race with an invalidate hence we need to
5470 * recheck.
5471 */
5472
5473 if (dev_priv->drrs.busy_frontbuffer_bits)
5474 goto unlock;
5475
5476 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5477 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5478
5479 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5480 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5481 }
5482
5483 unlock:
5484 mutex_unlock(&dev_priv->drrs.mutex);
5485 }
5486
5487 /**
5488 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5489 * @dev_priv: i915 device
5490 * @frontbuffer_bits: frontbuffer plane tracking bits
5491 *
5492 * This function gets called everytime rendering on the given planes start.
5493 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5494 *
5495 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5496 */
5497 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5498 unsigned int frontbuffer_bits)
5499 {
5500 struct drm_crtc *crtc;
5501 enum pipe pipe;
5502
5503 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5504 return;
5505
5506 cancel_delayed_work(&dev_priv->drrs.work);
5507
5508 mutex_lock(&dev_priv->drrs.mutex);
5509 if (!dev_priv->drrs.dp) {
5510 mutex_unlock(&dev_priv->drrs.mutex);
5511 return;
5512 }
5513
5514 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5515 pipe = to_intel_crtc(crtc)->pipe;
5516
5517 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5518 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5519
5520 /* invalidate means busy screen hence upclock */
5521 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5522 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5523 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5524
5525 mutex_unlock(&dev_priv->drrs.mutex);
5526 }
5527
5528 /**
5529 * intel_edp_drrs_flush - Restart Idleness DRRS
5530 * @dev_priv: i915 device
5531 * @frontbuffer_bits: frontbuffer plane tracking bits
5532 *
5533 * This function gets called every time rendering on the given planes has
5534 * completed or flip on a crtc is completed. So DRRS should be upclocked
5535 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5536 * if no other planes are dirty.
5537 *
5538 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5539 */
5540 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5541 unsigned int frontbuffer_bits)
5542 {
5543 struct drm_crtc *crtc;
5544 enum pipe pipe;
5545
5546 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5547 return;
5548
5549 cancel_delayed_work(&dev_priv->drrs.work);
5550
5551 mutex_lock(&dev_priv->drrs.mutex);
5552 if (!dev_priv->drrs.dp) {
5553 mutex_unlock(&dev_priv->drrs.mutex);
5554 return;
5555 }
5556
5557 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5558 pipe = to_intel_crtc(crtc)->pipe;
5559
5560 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5561 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5562
5563 /* flush means busy screen hence upclock */
5564 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5565 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5566 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5567
5568 /*
5569 * flush also means no more activity hence schedule downclock, if all
5570 * other fbs are quiescent too
5571 */
5572 if (!dev_priv->drrs.busy_frontbuffer_bits)
5573 schedule_delayed_work(&dev_priv->drrs.work,
5574 msecs_to_jiffies(1000));
5575 mutex_unlock(&dev_priv->drrs.mutex);
5576 }
5577
5578 /**
5579 * DOC: Display Refresh Rate Switching (DRRS)
5580 *
5581 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5582 * which enables swtching between low and high refresh rates,
5583 * dynamically, based on the usage scenario. This feature is applicable
5584 * for internal panels.
5585 *
5586 * Indication that the panel supports DRRS is given by the panel EDID, which
5587 * would list multiple refresh rates for one resolution.
5588 *
5589 * DRRS is of 2 types - static and seamless.
5590 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5591 * (may appear as a blink on screen) and is used in dock-undock scenario.
5592 * Seamless DRRS involves changing RR without any visual effect to the user
5593 * and can be used during normal system usage. This is done by programming
5594 * certain registers.
5595 *
5596 * Support for static/seamless DRRS may be indicated in the VBT based on
5597 * inputs from the panel spec.
5598 *
5599 * DRRS saves power by switching to low RR based on usage scenarios.
5600 *
5601 * The implementation is based on frontbuffer tracking implementation. When
5602 * there is a disturbance on the screen triggered by user activity or a periodic
5603 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5604 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5605 * made.
5606 *
5607 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5608 * and intel_edp_drrs_flush() are called.
5609 *
5610 * DRRS can be further extended to support other internal panels and also
5611 * the scenario of video playback wherein RR is set based on the rate
5612 * requested by userspace.
5613 */
5614
5615 /**
5616 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5617 * @intel_connector: eDP connector
5618 * @fixed_mode: preferred mode of panel
5619 *
5620 * This function is called only once at driver load to initialize basic
5621 * DRRS stuff.
5622 *
5623 * Returns:
5624 * Downclock mode if panel supports it, else return NULL.
5625 * DRRS support is determined by the presence of downclock mode (apart
5626 * from VBT setting).
5627 */
5628 static struct drm_display_mode *
5629 intel_dp_drrs_init(struct intel_connector *intel_connector,
5630 struct drm_display_mode *fixed_mode)
5631 {
5632 struct drm_connector *connector = &intel_connector->base;
5633 struct drm_device *dev = connector->dev;
5634 struct drm_i915_private *dev_priv = to_i915(dev);
5635 struct drm_display_mode *downclock_mode = NULL;
5636
5637 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5638 mutex_init(&dev_priv->drrs.mutex);
5639
5640 if (INTEL_GEN(dev_priv) <= 6) {
5641 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5642 return NULL;
5643 }
5644
5645 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5646 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5647 return NULL;
5648 }
5649
5650 downclock_mode = intel_find_panel_downclock
5651 (dev_priv, fixed_mode, connector);
5652
5653 if (!downclock_mode) {
5654 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5655 return NULL;
5656 }
5657
5658 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5659
5660 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5661 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5662 return downclock_mode;
5663 }
5664
5665 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5666 struct intel_connector *intel_connector)
5667 {
5668 struct drm_connector *connector = &intel_connector->base;
5669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5670 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5671 struct drm_device *dev = intel_encoder->base.dev;
5672 struct drm_i915_private *dev_priv = to_i915(dev);
5673 struct drm_display_mode *fixed_mode = NULL;
5674 struct drm_display_mode *downclock_mode = NULL;
5675 bool has_dpcd;
5676 struct drm_display_mode *scan;
5677 struct edid *edid;
5678 enum pipe pipe = INVALID_PIPE;
5679
5680 if (!is_edp(intel_dp))
5681 return true;
5682
5683 /*
5684 * On IBX/CPT we may get here with LVDS already registered. Since the
5685 * driver uses the only internal power sequencer available for both
5686 * eDP and LVDS bail out early in this case to prevent interfering
5687 * with an already powered-on LVDS power sequencer.
5688 */
5689 if (intel_get_lvds_encoder(dev)) {
5690 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5691 DRM_INFO("LVDS was detected, not registering eDP\n");
5692
5693 return false;
5694 }
5695
5696 pps_lock(intel_dp);
5697
5698 intel_dp_init_panel_power_timestamps(intel_dp);
5699 intel_dp_pps_init(dev, intel_dp);
5700 intel_edp_panel_vdd_sanitize(intel_dp);
5701
5702 pps_unlock(intel_dp);
5703
5704 /* Cache DPCD and EDID for edp. */
5705 has_dpcd = intel_edp_init_dpcd(intel_dp);
5706
5707 if (!has_dpcd) {
5708 /* if this fails, presume the device is a ghost */
5709 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5710 goto out_vdd_off;
5711 }
5712
5713 mutex_lock(&dev->mode_config.mutex);
5714 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5715 if (edid) {
5716 if (drm_add_edid_modes(connector, edid)) {
5717 drm_mode_connector_update_edid_property(connector,
5718 edid);
5719 drm_edid_to_eld(connector, edid);
5720 } else {
5721 kfree(edid);
5722 edid = ERR_PTR(-EINVAL);
5723 }
5724 } else {
5725 edid = ERR_PTR(-ENOENT);
5726 }
5727 intel_connector->edid = edid;
5728
5729 /* prefer fixed mode from EDID if available */
5730 list_for_each_entry(scan, &connector->probed_modes, head) {
5731 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5732 fixed_mode = drm_mode_duplicate(dev, scan);
5733 downclock_mode = intel_dp_drrs_init(
5734 intel_connector, fixed_mode);
5735 break;
5736 }
5737 }
5738
5739 /* fallback to VBT if available for eDP */
5740 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5741 fixed_mode = drm_mode_duplicate(dev,
5742 dev_priv->vbt.lfp_lvds_vbt_mode);
5743 if (fixed_mode) {
5744 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5745 connector->display_info.width_mm = fixed_mode->width_mm;
5746 connector->display_info.height_mm = fixed_mode->height_mm;
5747 }
5748 }
5749 mutex_unlock(&dev->mode_config.mutex);
5750
5751 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5752 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5753 register_reboot_notifier(&intel_dp->edp_notifier);
5754
5755 /*
5756 * Figure out the current pipe for the initial backlight setup.
5757 * If the current pipe isn't valid, try the PPS pipe, and if that
5758 * fails just assume pipe A.
5759 */
5760 pipe = vlv_active_pipe(intel_dp);
5761
5762 if (pipe != PIPE_A && pipe != PIPE_B)
5763 pipe = intel_dp->pps_pipe;
5764
5765 if (pipe != PIPE_A && pipe != PIPE_B)
5766 pipe = PIPE_A;
5767
5768 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5769 pipe_name(pipe));
5770 }
5771
5772 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5773 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5774 intel_panel_setup_backlight(connector, pipe);
5775
5776 return true;
5777
5778 out_vdd_off:
5779 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5780 /*
5781 * vdd might still be enabled do to the delayed vdd off.
5782 * Make sure vdd is actually turned off here.
5783 */
5784 pps_lock(intel_dp);
5785 edp_panel_vdd_off_sync(intel_dp);
5786 pps_unlock(intel_dp);
5787
5788 return false;
5789 }
5790
5791 bool
5792 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5793 struct intel_connector *intel_connector)
5794 {
5795 struct drm_connector *connector = &intel_connector->base;
5796 struct intel_dp *intel_dp = &intel_dig_port->dp;
5797 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5798 struct drm_device *dev = intel_encoder->base.dev;
5799 struct drm_i915_private *dev_priv = to_i915(dev);
5800 enum port port = intel_dig_port->port;
5801 int type;
5802
5803 if (WARN(intel_dig_port->max_lanes < 1,
5804 "Not enough lanes (%d) for DP on port %c\n",
5805 intel_dig_port->max_lanes, port_name(port)))
5806 return false;
5807
5808 intel_dp->pps_pipe = INVALID_PIPE;
5809 intel_dp->active_pipe = INVALID_PIPE;
5810
5811 /* intel_dp vfuncs */
5812 if (INTEL_GEN(dev_priv) >= 9)
5813 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5814 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5815 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5816 else if (HAS_PCH_SPLIT(dev_priv))
5817 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5818 else
5819 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5820
5821 if (INTEL_GEN(dev_priv) >= 9)
5822 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5823 else
5824 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5825
5826 if (HAS_DDI(dev_priv))
5827 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5828
5829 /* Preserve the current hw state. */
5830 intel_dp->DP = I915_READ(intel_dp->output_reg);
5831 intel_dp->attached_connector = intel_connector;
5832
5833 if (intel_dp_is_edp(dev_priv, port))
5834 type = DRM_MODE_CONNECTOR_eDP;
5835 else
5836 type = DRM_MODE_CONNECTOR_DisplayPort;
5837
5838 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5839 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5840
5841 /*
5842 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5843 * for DP the encoder type can be set by the caller to
5844 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5845 */
5846 if (type == DRM_MODE_CONNECTOR_eDP)
5847 intel_encoder->type = INTEL_OUTPUT_EDP;
5848
5849 /* eDP only on port B and/or C on vlv/chv */
5850 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5851 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5852 return false;
5853
5854 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5855 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5856 port_name(port));
5857
5858 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5859 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5860
5861 connector->interlace_allowed = true;
5862 connector->doublescan_allowed = 0;
5863
5864 intel_dp_aux_init(intel_dp);
5865
5866 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5867 edp_panel_vdd_work);
5868
5869 intel_connector_attach_encoder(intel_connector, intel_encoder);
5870
5871 if (HAS_DDI(dev_priv))
5872 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5873 else
5874 intel_connector->get_hw_state = intel_connector_get_hw_state;
5875
5876 /* Set up the hotplug pin. */
5877 switch (port) {
5878 case PORT_A:
5879 intel_encoder->hpd_pin = HPD_PORT_A;
5880 break;
5881 case PORT_B:
5882 intel_encoder->hpd_pin = HPD_PORT_B;
5883 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
5884 intel_encoder->hpd_pin = HPD_PORT_A;
5885 break;
5886 case PORT_C:
5887 intel_encoder->hpd_pin = HPD_PORT_C;
5888 break;
5889 case PORT_D:
5890 intel_encoder->hpd_pin = HPD_PORT_D;
5891 break;
5892 case PORT_E:
5893 intel_encoder->hpd_pin = HPD_PORT_E;
5894 break;
5895 default:
5896 BUG();
5897 }
5898
5899 /* init MST on ports that can support it */
5900 if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
5901 (port == PORT_B || port == PORT_C || port == PORT_D))
5902 intel_dp_mst_encoder_init(intel_dig_port,
5903 intel_connector->base.base.id);
5904
5905 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5906 intel_dp_aux_fini(intel_dp);
5907 intel_dp_mst_encoder_cleanup(intel_dig_port);
5908 goto fail;
5909 }
5910
5911 intel_dp_add_properties(intel_dp, connector);
5912
5913 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5914 * 0xd. Failure to do so will result in spurious interrupts being
5915 * generated on the port when a cable is not attached.
5916 */
5917 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
5918 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5919 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5920 }
5921
5922 return true;
5923
5924 fail:
5925 drm_connector_cleanup(connector);
5926
5927 return false;
5928 }
5929
5930 bool intel_dp_init(struct drm_i915_private *dev_priv,
5931 i915_reg_t output_reg,
5932 enum port port)
5933 {
5934 struct intel_digital_port *intel_dig_port;
5935 struct intel_encoder *intel_encoder;
5936 struct drm_encoder *encoder;
5937 struct intel_connector *intel_connector;
5938
5939 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5940 if (!intel_dig_port)
5941 return false;
5942
5943 intel_connector = intel_connector_alloc();
5944 if (!intel_connector)
5945 goto err_connector_alloc;
5946
5947 intel_encoder = &intel_dig_port->base;
5948 encoder = &intel_encoder->base;
5949
5950 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
5951 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
5952 "DP %c", port_name(port)))
5953 goto err_encoder_init;
5954
5955 intel_encoder->compute_config = intel_dp_compute_config;
5956 intel_encoder->disable = intel_disable_dp;
5957 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5958 intel_encoder->get_config = intel_dp_get_config;
5959 intel_encoder->suspend = intel_dp_encoder_suspend;
5960 if (IS_CHERRYVIEW(dev_priv)) {
5961 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5962 intel_encoder->pre_enable = chv_pre_enable_dp;
5963 intel_encoder->enable = vlv_enable_dp;
5964 intel_encoder->post_disable = chv_post_disable_dp;
5965 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5966 } else if (IS_VALLEYVIEW(dev_priv)) {
5967 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5968 intel_encoder->pre_enable = vlv_pre_enable_dp;
5969 intel_encoder->enable = vlv_enable_dp;
5970 intel_encoder->post_disable = vlv_post_disable_dp;
5971 } else {
5972 intel_encoder->pre_enable = g4x_pre_enable_dp;
5973 intel_encoder->enable = g4x_enable_dp;
5974 if (INTEL_GEN(dev_priv) >= 5)
5975 intel_encoder->post_disable = ilk_post_disable_dp;
5976 }
5977
5978 intel_dig_port->port = port;
5979 intel_dig_port->dp.output_reg = output_reg;
5980 intel_dig_port->max_lanes = 4;
5981
5982 intel_encoder->type = INTEL_OUTPUT_DP;
5983 if (IS_CHERRYVIEW(dev_priv)) {
5984 if (port == PORT_D)
5985 intel_encoder->crtc_mask = 1 << 2;
5986 else
5987 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5988 } else {
5989 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5990 }
5991 intel_encoder->cloneable = 0;
5992 intel_encoder->port = port;
5993
5994 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5995 dev_priv->hotplug.irq_port[port] = intel_dig_port;
5996
5997 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5998 goto err_init_connector;
5999
6000 return true;
6001
6002 err_init_connector:
6003 drm_encoder_cleanup(encoder);
6004 err_encoder_init:
6005 kfree(intel_connector);
6006 err_connector_alloc:
6007 kfree(intel_dig_port);
6008 return false;
6009 }
6010
6011 void intel_dp_mst_suspend(struct drm_device *dev)
6012 {
6013 struct drm_i915_private *dev_priv = to_i915(dev);
6014 int i;
6015
6016 /* disable MST */
6017 for (i = 0; i < I915_MAX_PORTS; i++) {
6018 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6019
6020 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6021 continue;
6022
6023 if (intel_dig_port->dp.is_mst)
6024 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6025 }
6026 }
6027
6028 void intel_dp_mst_resume(struct drm_device *dev)
6029 {
6030 struct drm_i915_private *dev_priv = to_i915(dev);
6031 int i;
6032
6033 for (i = 0; i < I915_MAX_PORTS; i++) {
6034 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6035 int ret;
6036
6037 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6038 continue;
6039
6040 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6041 if (ret)
6042 intel_dp_check_mst_status(&intel_dig_port->dp);
6043 }
6044 }
Linux with added FPC-III support