2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_mipi_dsi.h>
30 #include "intel_drv.h"
32 /* Dual Link support */
33 #define DSI_DUAL_LINK_NONE 0
34 #define DSI_DUAL_LINK_FRONT_BACK 1
35 #define DSI_DUAL_LINK_PIXEL_ALT 2
37 struct intel_dsi_host
;
40 struct intel_encoder base
;
42 struct drm_panel
*panel
;
43 struct intel_dsi_host
*dsi_hosts
[I915_MAX_PORTS
];
45 /* GPIO Desc for CRC based Panel control */
46 struct gpio_desc
*gpio_panel
;
48 struct intel_connector
*attached_connector
;
50 /* bit mask of ports being driven */
53 /* if true, use HS mode, otherwise LP */
59 /* Video mode or command mode */
62 /* number of DSI lanes */
63 unsigned int lane_count
;
66 * video mode pixel format
68 * XXX: consolidate on .format in struct mipi_dsi_device.
70 enum mipi_dsi_pixel_format pixel_format
;
72 /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
73 u32 video_mode_format
;
75 /* eot for MIPI_EOT_DISABLE register */
82 u16 dcs_backlight_ports
;
89 u32 video_frmt_cfg_bits
;
92 /* timeouts in byte clocks */
97 u16 clk_lp_to_hs_count
;
98 u16 clk_hs_to_lp_count
;
102 u16 burst_mode_ratio
;
104 /* all delays in ms */
105 u16 backlight_off_delay
;
106 u16 backlight_on_delay
;
109 u16 panel_pwr_cycle_delay
;
112 struct intel_dsi_host
{
113 struct mipi_dsi_host base
;
114 struct intel_dsi
*intel_dsi
;
117 /* our little hack */
118 struct mipi_dsi_device
*device
;
121 static inline struct intel_dsi_host
*to_intel_dsi_host(struct mipi_dsi_host
*h
)
123 return container_of(h
, struct intel_dsi_host
, base
);
126 #define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
128 static inline struct intel_dsi
*enc_to_intel_dsi(struct drm_encoder
*encoder
)
130 return container_of(encoder
, struct intel_dsi
, base
.base
);
133 bool intel_dsi_pll_is_enabled(struct drm_i915_private
*dev_priv
);
134 int intel_compute_dsi_pll(struct intel_encoder
*encoder
,
135 struct intel_crtc_state
*config
);
136 void intel_enable_dsi_pll(struct intel_encoder
*encoder
,
137 const struct intel_crtc_state
*config
);
138 void intel_disable_dsi_pll(struct intel_encoder
*encoder
);
139 u32
intel_dsi_get_pclk(struct intel_encoder
*encoder
, int pipe_bpp
,
140 struct intel_crtc_state
*config
);
141 void intel_dsi_reset_clocks(struct intel_encoder
*encoder
,
144 struct drm_panel
*vbt_panel_init(struct intel_dsi
*intel_dsi
, u16 panel_id
);
145 enum mipi_dsi_pixel_format
pixel_format_from_register_bits(u32 fmt
);
147 #endif /* _INTEL_DSI_H */