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drm/exynos: Stop using drm_framebuffer_unregister_private
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_ttm.c
blob1888144d0fed0ea5c977645d7c7e5c47cf26719b
1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <ttm/ttm_bo_api.h>
33 #include <ttm/ttm_bo_driver.h>
34 #include <ttm/ttm_placement.h>
35 #include <ttm/ttm_module.h>
36 #include <ttm/ttm_page_alloc.h>
37 #include <drm/drmP.h>
38 #include <drm/radeon_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swiotlb.h>
42 #include <linux/swap.h>
43 #include <linux/pagemap.h>
44 #include <linux/debugfs.h>
45 #include "radeon_reg.h"
46 #include "radeon.h"
47
48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
51 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
52
53 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
54 {
55 struct radeon_mman *mman;
56 struct radeon_device *rdev;
57
58 mman = container_of(bdev, struct radeon_mman, bdev);
59 rdev = container_of(mman, struct radeon_device, mman);
60 return rdev;
61 }
62
63
64 /*
65 * Global memory.
66 */
67 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
68 {
69 return ttm_mem_global_init(ref->object);
70 }
71
72 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
73 {
74 ttm_mem_global_release(ref->object);
75 }
76
77 static int radeon_ttm_global_init(struct radeon_device *rdev)
78 {
79 struct drm_global_reference *global_ref;
80 int r;
81
82 rdev->mman.mem_global_referenced = false;
83 global_ref = &rdev->mman.mem_global_ref;
84 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
85 global_ref->size = sizeof(struct ttm_mem_global);
86 global_ref->init = &radeon_ttm_mem_global_init;
87 global_ref->release = &radeon_ttm_mem_global_release;
88 r = drm_global_item_ref(global_ref);
89 if (r != 0) {
90 DRM_ERROR("Failed setting up TTM memory accounting "
91 "subsystem.\n");
92 return r;
93 }
94
95 rdev->mman.bo_global_ref.mem_glob =
96 rdev->mman.mem_global_ref.object;
97 global_ref = &rdev->mman.bo_global_ref.ref;
98 global_ref->global_type = DRM_GLOBAL_TTM_BO;
99 global_ref->size = sizeof(struct ttm_bo_global);
100 global_ref->init = &ttm_bo_global_init;
101 global_ref->release = &ttm_bo_global_release;
102 r = drm_global_item_ref(global_ref);
103 if (r != 0) {
104 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
105 drm_global_item_unref(&rdev->mman.mem_global_ref);
106 return r;
107 }
108
109 rdev->mman.mem_global_referenced = true;
110 return 0;
111 }
112
113 static void radeon_ttm_global_fini(struct radeon_device *rdev)
114 {
115 if (rdev->mman.mem_global_referenced) {
116 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
117 drm_global_item_unref(&rdev->mman.mem_global_ref);
118 rdev->mman.mem_global_referenced = false;
119 }
120 }
121
122 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
123 {
124 return 0;
125 }
126
127 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
128 struct ttm_mem_type_manager *man)
129 {
130 struct radeon_device *rdev;
131
132 rdev = radeon_get_rdev(bdev);
133
134 switch (type) {
135 case TTM_PL_SYSTEM:
136 /* System memory */
137 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
138 man->available_caching = TTM_PL_MASK_CACHING;
139 man->default_caching = TTM_PL_FLAG_CACHED;
140 break;
141 case TTM_PL_TT:
142 man->func = &ttm_bo_manager_func;
143 man->gpu_offset = rdev->mc.gtt_start;
144 man->available_caching = TTM_PL_MASK_CACHING;
145 man->default_caching = TTM_PL_FLAG_CACHED;
146 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
147 #if IS_ENABLED(CONFIG_AGP)
148 if (rdev->flags & RADEON_IS_AGP) {
149 if (!rdev->ddev->agp) {
150 DRM_ERROR("AGP is not enabled for memory type %u\n",
151 (unsigned)type);
152 return -EINVAL;
153 }
154 if (!rdev->ddev->agp->cant_use_aperture)
155 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
156 man->available_caching = TTM_PL_FLAG_UNCACHED |
157 TTM_PL_FLAG_WC;
158 man->default_caching = TTM_PL_FLAG_WC;
159 }
160 #endif
161 break;
162 case TTM_PL_VRAM:
163 /* "On-card" video ram */
164 man->func = &ttm_bo_manager_func;
165 man->gpu_offset = rdev->mc.vram_start;
166 man->flags = TTM_MEMTYPE_FLAG_FIXED |
167 TTM_MEMTYPE_FLAG_MAPPABLE;
168 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
169 man->default_caching = TTM_PL_FLAG_WC;
170 break;
171 default:
172 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
173 return -EINVAL;
174 }
175 return 0;
176 }
177
178 static void radeon_evict_flags(struct ttm_buffer_object *bo,
179 struct ttm_placement *placement)
180 {
181 static struct ttm_place placements = {
182 .fpfn = 0,
183 .lpfn = 0,
184 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
185 };
186
187 struct radeon_bo *rbo;
188
189 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
190 placement->placement = &placements;
191 placement->busy_placement = &placements;
192 placement->num_placement = 1;
193 placement->num_busy_placement = 1;
194 return;
195 }
196 rbo = container_of(bo, struct radeon_bo, tbo);
197 switch (bo->mem.mem_type) {
198 case TTM_PL_VRAM:
199 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
200 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
201 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
202 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
203 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
204 int i;
205
206 /* Try evicting to the CPU inaccessible part of VRAM
207 * first, but only set GTT as busy placement, so this
208 * BO will be evicted to GTT rather than causing other
209 * BOs to be evicted from VRAM
210 */
211 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
212 RADEON_GEM_DOMAIN_GTT);
213 rbo->placement.num_busy_placement = 0;
214 for (i = 0; i < rbo->placement.num_placement; i++) {
215 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
216 if (rbo->placements[0].fpfn < fpfn)
217 rbo->placements[0].fpfn = fpfn;
218 } else {
219 rbo->placement.busy_placement =
220 &rbo->placements[i];
221 rbo->placement.num_busy_placement = 1;
222 }
223 }
224 } else
225 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
226 break;
227 case TTM_PL_TT:
228 default:
229 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
230 }
231 *placement = rbo->placement;
232 }
233
234 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
235 {
236 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
237
238 if (radeon_ttm_tt_has_userptr(bo->ttm))
239 return -EPERM;
240 return drm_vma_node_verify_access(&rbo->gem_base.vma_node,
241 filp->private_data);
242 }
243
244 static void radeon_move_null(struct ttm_buffer_object *bo,
245 struct ttm_mem_reg *new_mem)
246 {
247 struct ttm_mem_reg *old_mem = &bo->mem;
248
249 BUG_ON(old_mem->mm_node != NULL);
250 *old_mem = *new_mem;
251 new_mem->mm_node = NULL;
252 }
253
254 static int radeon_move_blit(struct ttm_buffer_object *bo,
255 bool evict, bool no_wait_gpu,
256 struct ttm_mem_reg *new_mem,
257 struct ttm_mem_reg *old_mem)
258 {
259 struct radeon_device *rdev;
260 uint64_t old_start, new_start;
261 struct radeon_fence *fence;
262 unsigned num_pages;
263 int r, ridx;
264
265 rdev = radeon_get_rdev(bo->bdev);
266 ridx = radeon_copy_ring_index(rdev);
267 old_start = (u64)old_mem->start << PAGE_SHIFT;
268 new_start = (u64)new_mem->start << PAGE_SHIFT;
269
270 switch (old_mem->mem_type) {
271 case TTM_PL_VRAM:
272 old_start += rdev->mc.vram_start;
273 break;
274 case TTM_PL_TT:
275 old_start += rdev->mc.gtt_start;
276 break;
277 default:
278 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
279 return -EINVAL;
280 }
281 switch (new_mem->mem_type) {
282 case TTM_PL_VRAM:
283 new_start += rdev->mc.vram_start;
284 break;
285 case TTM_PL_TT:
286 new_start += rdev->mc.gtt_start;
287 break;
288 default:
289 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
290 return -EINVAL;
291 }
292 if (!rdev->ring[ridx].ready) {
293 DRM_ERROR("Trying to move memory with ring turned off.\n");
294 return -EINVAL;
295 }
296
297 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
298
299 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
300 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
301 if (IS_ERR(fence))
302 return PTR_ERR(fence);
303
304 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem);
305 radeon_fence_unref(&fence);
306 return r;
307 }
308
309 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
310 bool evict, bool interruptible,
311 bool no_wait_gpu,
312 struct ttm_mem_reg *new_mem)
313 {
314 struct radeon_device *rdev;
315 struct ttm_mem_reg *old_mem = &bo->mem;
316 struct ttm_mem_reg tmp_mem;
317 struct ttm_place placements;
318 struct ttm_placement placement;
319 int r;
320
321 rdev = radeon_get_rdev(bo->bdev);
322 tmp_mem = *new_mem;
323 tmp_mem.mm_node = NULL;
324 placement.num_placement = 1;
325 placement.placement = &placements;
326 placement.num_busy_placement = 1;
327 placement.busy_placement = &placements;
328 placements.fpfn = 0;
329 placements.lpfn = 0;
330 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
331 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
332 interruptible, no_wait_gpu);
333 if (unlikely(r)) {
334 return r;
335 }
336
337 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
338 if (unlikely(r)) {
339 goto out_cleanup;
340 }
341
342 r = ttm_tt_bind(bo->ttm, &tmp_mem);
343 if (unlikely(r)) {
344 goto out_cleanup;
345 }
346 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
347 if (unlikely(r)) {
348 goto out_cleanup;
349 }
350 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
351 out_cleanup:
352 ttm_bo_mem_put(bo, &tmp_mem);
353 return r;
354 }
355
356 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
357 bool evict, bool interruptible,
358 bool no_wait_gpu,
359 struct ttm_mem_reg *new_mem)
360 {
361 struct radeon_device *rdev;
362 struct ttm_mem_reg *old_mem = &bo->mem;
363 struct ttm_mem_reg tmp_mem;
364 struct ttm_placement placement;
365 struct ttm_place placements;
366 int r;
367
368 rdev = radeon_get_rdev(bo->bdev);
369 tmp_mem = *new_mem;
370 tmp_mem.mm_node = NULL;
371 placement.num_placement = 1;
372 placement.placement = &placements;
373 placement.num_busy_placement = 1;
374 placement.busy_placement = &placements;
375 placements.fpfn = 0;
376 placements.lpfn = 0;
377 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
378 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
379 interruptible, no_wait_gpu);
380 if (unlikely(r)) {
381 return r;
382 }
383 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
384 if (unlikely(r)) {
385 goto out_cleanup;
386 }
387 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
388 if (unlikely(r)) {
389 goto out_cleanup;
390 }
391 out_cleanup:
392 ttm_bo_mem_put(bo, &tmp_mem);
393 return r;
394 }
395
396 static int radeon_bo_move(struct ttm_buffer_object *bo,
397 bool evict, bool interruptible,
398 bool no_wait_gpu,
399 struct ttm_mem_reg *new_mem)
400 {
401 struct radeon_device *rdev;
402 struct radeon_bo *rbo;
403 struct ttm_mem_reg *old_mem = &bo->mem;
404 int r;
405
406 r = ttm_bo_wait(bo, interruptible, no_wait_gpu);
407 if (r)
408 return r;
409
410 /* Can't move a pinned BO */
411 rbo = container_of(bo, struct radeon_bo, tbo);
412 if (WARN_ON_ONCE(rbo->pin_count > 0))
413 return -EINVAL;
414
415 rdev = radeon_get_rdev(bo->bdev);
416 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
417 radeon_move_null(bo, new_mem);
418 return 0;
419 }
420 if ((old_mem->mem_type == TTM_PL_TT &&
421 new_mem->mem_type == TTM_PL_SYSTEM) ||
422 (old_mem->mem_type == TTM_PL_SYSTEM &&
423 new_mem->mem_type == TTM_PL_TT)) {
424 /* bind is enough */
425 radeon_move_null(bo, new_mem);
426 return 0;
427 }
428 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
429 rdev->asic->copy.copy == NULL) {
430 /* use memcpy */
431 goto memcpy;
432 }
433
434 if (old_mem->mem_type == TTM_PL_VRAM &&
435 new_mem->mem_type == TTM_PL_SYSTEM) {
436 r = radeon_move_vram_ram(bo, evict, interruptible,
437 no_wait_gpu, new_mem);
438 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
439 new_mem->mem_type == TTM_PL_VRAM) {
440 r = radeon_move_ram_vram(bo, evict, interruptible,
441 no_wait_gpu, new_mem);
442 } else {
443 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
444 }
445
446 if (r) {
447 memcpy:
448 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
449 if (r) {
450 return r;
451 }
452 }
453
454 /* update statistics */
455 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
456 return 0;
457 }
458
459 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
460 {
461 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
462 struct radeon_device *rdev = radeon_get_rdev(bdev);
463
464 mem->bus.addr = NULL;
465 mem->bus.offset = 0;
466 mem->bus.size = mem->num_pages << PAGE_SHIFT;
467 mem->bus.base = 0;
468 mem->bus.is_iomem = false;
469 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
470 return -EINVAL;
471 switch (mem->mem_type) {
472 case TTM_PL_SYSTEM:
473 /* system memory */
474 return 0;
475 case TTM_PL_TT:
476 #if IS_ENABLED(CONFIG_AGP)
477 if (rdev->flags & RADEON_IS_AGP) {
478 /* RADEON_IS_AGP is set only if AGP is active */
479 mem->bus.offset = mem->start << PAGE_SHIFT;
480 mem->bus.base = rdev->mc.agp_base;
481 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
482 }
483 #endif
484 break;
485 case TTM_PL_VRAM:
486 mem->bus.offset = mem->start << PAGE_SHIFT;
487 /* check if it's visible */
488 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
489 return -EINVAL;
490 mem->bus.base = rdev->mc.aper_base;
491 mem->bus.is_iomem = true;
492 #ifdef __alpha__
493 /*
494 * Alpha: use bus.addr to hold the ioremap() return,
495 * so we can modify bus.base below.
496 */
497 if (mem->placement & TTM_PL_FLAG_WC)
498 mem->bus.addr =
499 ioremap_wc(mem->bus.base + mem->bus.offset,
500 mem->bus.size);
501 else
502 mem->bus.addr =
503 ioremap_nocache(mem->bus.base + mem->bus.offset,
504 mem->bus.size);
505
506 /*
507 * Alpha: Use just the bus offset plus
508 * the hose/domain memory base for bus.base.
509 * It then can be used to build PTEs for VRAM
510 * access, as done in ttm_bo_vm_fault().
511 */
512 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
513 rdev->ddev->hose->dense_mem_base;
514 #endif
515 break;
516 default:
517 return -EINVAL;
518 }
519 return 0;
520 }
521
522 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
523 {
524 }
525
526 /*
527 * TTM backend functions.
528 */
529 struct radeon_ttm_tt {
530 struct ttm_dma_tt ttm;
531 struct radeon_device *rdev;
532 u64 offset;
533
534 uint64_t userptr;
535 struct mm_struct *usermm;
536 uint32_t userflags;
537 };
538
539 /* prepare the sg table with the user pages */
540 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
541 {
542 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
543 struct radeon_ttm_tt *gtt = (void *)ttm;
544 unsigned pinned = 0, nents;
545 int r;
546
547 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
548 enum dma_data_direction direction = write ?
549 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
550
551 if (current->mm != gtt->usermm)
552 return -EPERM;
553
554 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
555 /* check that we only pin down anonymous memory
556 to prevent problems with writeback */
557 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
558 struct vm_area_struct *vma;
559 vma = find_vma(gtt->usermm, gtt->userptr);
560 if (!vma || vma->vm_file || vma->vm_end < end)
561 return -EPERM;
562 }
563
564 do {
565 unsigned num_pages = ttm->num_pages - pinned;
566 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
567 struct page **pages = ttm->pages + pinned;
568
569 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
570 pages, NULL);
571 if (r < 0)
572 goto release_pages;
573
574 pinned += r;
575
576 } while (pinned < ttm->num_pages);
577
578 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
579 ttm->num_pages << PAGE_SHIFT,
580 GFP_KERNEL);
581 if (r)
582 goto release_sg;
583
584 r = -ENOMEM;
585 nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
586 if (nents != ttm->sg->nents)
587 goto release_sg;
588
589 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
590 gtt->ttm.dma_address, ttm->num_pages);
591
592 return 0;
593
594 release_sg:
595 kfree(ttm->sg);
596
597 release_pages:
598 release_pages(ttm->pages, pinned, 0);
599 return r;
600 }
601
602 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
603 {
604 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
605 struct radeon_ttm_tt *gtt = (void *)ttm;
606 struct sg_page_iter sg_iter;
607
608 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
609 enum dma_data_direction direction = write ?
610 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
611
612 /* double check that we don't free the table twice */
613 if (!ttm->sg->sgl)
614 return;
615
616 /* free the sg table and pages again */
617 dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
618
619 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
620 struct page *page = sg_page_iter_page(&sg_iter);
621 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
622 set_page_dirty(page);
623
624 mark_page_accessed(page);
625 put_page(page);
626 }
627
628 sg_free_table(ttm->sg);
629 }
630
631 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
632 struct ttm_mem_reg *bo_mem)
633 {
634 struct radeon_ttm_tt *gtt = (void*)ttm;
635 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
636 RADEON_GART_PAGE_WRITE;
637 int r;
638
639 if (gtt->userptr) {
640 radeon_ttm_tt_pin_userptr(ttm);
641 flags &= ~RADEON_GART_PAGE_WRITE;
642 }
643
644 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
645 if (!ttm->num_pages) {
646 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
647 ttm->num_pages, bo_mem, ttm);
648 }
649 if (ttm->caching_state == tt_cached)
650 flags |= RADEON_GART_PAGE_SNOOP;
651 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
652 ttm->pages, gtt->ttm.dma_address, flags);
653 if (r) {
654 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
655 ttm->num_pages, (unsigned)gtt->offset);
656 return r;
657 }
658 return 0;
659 }
660
661 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
662 {
663 struct radeon_ttm_tt *gtt = (void *)ttm;
664
665 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
666
667 if (gtt->userptr)
668 radeon_ttm_tt_unpin_userptr(ttm);
669
670 return 0;
671 }
672
673 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
674 {
675 struct radeon_ttm_tt *gtt = (void *)ttm;
676
677 ttm_dma_tt_fini(&gtt->ttm);
678 kfree(gtt);
679 }
680
681 static struct ttm_backend_func radeon_backend_func = {
682 .bind = &radeon_ttm_backend_bind,
683 .unbind = &radeon_ttm_backend_unbind,
684 .destroy = &radeon_ttm_backend_destroy,
685 };
686
687 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
688 unsigned long size, uint32_t page_flags,
689 struct page *dummy_read_page)
690 {
691 struct radeon_device *rdev;
692 struct radeon_ttm_tt *gtt;
693
694 rdev = radeon_get_rdev(bdev);
695 #if IS_ENABLED(CONFIG_AGP)
696 if (rdev->flags & RADEON_IS_AGP) {
697 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
698 size, page_flags, dummy_read_page);
699 }
700 #endif
701
702 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
703 if (gtt == NULL) {
704 return NULL;
705 }
706 gtt->ttm.ttm.func = &radeon_backend_func;
707 gtt->rdev = rdev;
708 if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
709 kfree(gtt);
710 return NULL;
711 }
712 return &gtt->ttm.ttm;
713 }
714
715 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
716 {
717 if (!ttm || ttm->func != &radeon_backend_func)
718 return NULL;
719 return (struct radeon_ttm_tt *)ttm;
720 }
721
722 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
723 {
724 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
725 struct radeon_device *rdev;
726 unsigned i;
727 int r;
728 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
729
730 if (ttm->state != tt_unpopulated)
731 return 0;
732
733 if (gtt && gtt->userptr) {
734 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
735 if (!ttm->sg)
736 return -ENOMEM;
737
738 ttm->page_flags |= TTM_PAGE_FLAG_SG;
739 ttm->state = tt_unbound;
740 return 0;
741 }
742
743 if (slave && ttm->sg) {
744 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
745 gtt->ttm.dma_address, ttm->num_pages);
746 ttm->state = tt_unbound;
747 return 0;
748 }
749
750 rdev = radeon_get_rdev(ttm->bdev);
751 #if IS_ENABLED(CONFIG_AGP)
752 if (rdev->flags & RADEON_IS_AGP) {
753 return ttm_agp_tt_populate(ttm);
754 }
755 #endif
756
757 #ifdef CONFIG_SWIOTLB
758 if (swiotlb_nr_tbl()) {
759 return ttm_dma_populate(&gtt->ttm, rdev->dev);
760 }
761 #endif
762
763 r = ttm_pool_populate(ttm);
764 if (r) {
765 return r;
766 }
767
768 for (i = 0; i < ttm->num_pages; i++) {
769 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
770 0, PAGE_SIZE,
771 PCI_DMA_BIDIRECTIONAL);
772 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
773 while (i--) {
774 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
775 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
776 gtt->ttm.dma_address[i] = 0;
777 }
778 ttm_pool_unpopulate(ttm);
779 return -EFAULT;
780 }
781 }
782 return 0;
783 }
784
785 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
786 {
787 struct radeon_device *rdev;
788 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
789 unsigned i;
790 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
791
792 if (gtt && gtt->userptr) {
793 kfree(ttm->sg);
794 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
795 return;
796 }
797
798 if (slave)
799 return;
800
801 rdev = radeon_get_rdev(ttm->bdev);
802 #if IS_ENABLED(CONFIG_AGP)
803 if (rdev->flags & RADEON_IS_AGP) {
804 ttm_agp_tt_unpopulate(ttm);
805 return;
806 }
807 #endif
808
809 #ifdef CONFIG_SWIOTLB
810 if (swiotlb_nr_tbl()) {
811 ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
812 return;
813 }
814 #endif
815
816 for (i = 0; i < ttm->num_pages; i++) {
817 if (gtt->ttm.dma_address[i]) {
818 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
819 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
820 }
821 }
822
823 ttm_pool_unpopulate(ttm);
824 }
825
826 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
827 uint32_t flags)
828 {
829 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
830
831 if (gtt == NULL)
832 return -EINVAL;
833
834 gtt->userptr = addr;
835 gtt->usermm = current->mm;
836 gtt->userflags = flags;
837 return 0;
838 }
839
840 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
841 {
842 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
843
844 if (gtt == NULL)
845 return false;
846
847 return !!gtt->userptr;
848 }
849
850 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
851 {
852 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
853
854 if (gtt == NULL)
855 return false;
856
857 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
858 }
859
860 static struct ttm_bo_driver radeon_bo_driver = {
861 .ttm_tt_create = &radeon_ttm_tt_create,
862 .ttm_tt_populate = &radeon_ttm_tt_populate,
863 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
864 .invalidate_caches = &radeon_invalidate_caches,
865 .init_mem_type = &radeon_init_mem_type,
866 .eviction_valuable = ttm_bo_eviction_valuable,
867 .evict_flags = &radeon_evict_flags,
868 .move = &radeon_bo_move,
869 .verify_access = &radeon_verify_access,
870 .move_notify = &radeon_bo_move_notify,
871 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
872 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
873 .io_mem_free = &radeon_ttm_io_mem_free,
874 .lru_tail = &ttm_bo_default_lru_tail,
875 .swap_lru_tail = &ttm_bo_default_swap_lru_tail,
876 };
877
878 int radeon_ttm_init(struct radeon_device *rdev)
879 {
880 int r;
881
882 r = radeon_ttm_global_init(rdev);
883 if (r) {
884 return r;
885 }
886 /* No others user of address space so set it to 0 */
887 r = ttm_bo_device_init(&rdev->mman.bdev,
888 rdev->mman.bo_global_ref.ref.object,
889 &radeon_bo_driver,
890 rdev->ddev->anon_inode->i_mapping,
891 DRM_FILE_PAGE_OFFSET,
892 rdev->need_dma32);
893 if (r) {
894 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
895 return r;
896 }
897 rdev->mman.initialized = true;
898 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
899 rdev->mc.real_vram_size >> PAGE_SHIFT);
900 if (r) {
901 DRM_ERROR("Failed initializing VRAM heap.\n");
902 return r;
903 }
904 /* Change the size here instead of the init above so only lpfn is affected */
905 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
906
907 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
908 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
909 NULL, &rdev->stollen_vga_memory);
910 if (r) {
911 return r;
912 }
913 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
914 if (r)
915 return r;
916 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
917 radeon_bo_unreserve(rdev->stollen_vga_memory);
918 if (r) {
919 radeon_bo_unref(&rdev->stollen_vga_memory);
920 return r;
921 }
922 DRM_INFO("radeon: %uM of VRAM memory ready\n",
923 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
924 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
925 rdev->mc.gtt_size >> PAGE_SHIFT);
926 if (r) {
927 DRM_ERROR("Failed initializing GTT heap.\n");
928 return r;
929 }
930 DRM_INFO("radeon: %uM of GTT memory ready.\n",
931 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
932
933 r = radeon_ttm_debugfs_init(rdev);
934 if (r) {
935 DRM_ERROR("Failed to init debugfs\n");
936 return r;
937 }
938 return 0;
939 }
940
941 void radeon_ttm_fini(struct radeon_device *rdev)
942 {
943 int r;
944
945 if (!rdev->mman.initialized)
946 return;
947 radeon_ttm_debugfs_fini(rdev);
948 if (rdev->stollen_vga_memory) {
949 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
950 if (r == 0) {
951 radeon_bo_unpin(rdev->stollen_vga_memory);
952 radeon_bo_unreserve(rdev->stollen_vga_memory);
953 }
954 radeon_bo_unref(&rdev->stollen_vga_memory);
955 }
956 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
957 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
958 ttm_bo_device_release(&rdev->mman.bdev);
959 radeon_gart_fini(rdev);
960 radeon_ttm_global_fini(rdev);
961 rdev->mman.initialized = false;
962 DRM_INFO("radeon: ttm finalized\n");
963 }
964
965 /* this should only be called at bootup or when userspace
966 * isn't running */
967 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
968 {
969 struct ttm_mem_type_manager *man;
970
971 if (!rdev->mman.initialized)
972 return;
973
974 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
975 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
976 man->size = size >> PAGE_SHIFT;
977 }
978
979 static struct vm_operations_struct radeon_ttm_vm_ops;
980 static const struct vm_operations_struct *ttm_vm_ops = NULL;
981
982 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
983 {
984 struct ttm_buffer_object *bo;
985 struct radeon_device *rdev;
986 int r;
987
988 bo = (struct ttm_buffer_object *)vma->vm_private_data;
989 if (bo == NULL) {
990 return VM_FAULT_NOPAGE;
991 }
992 rdev = radeon_get_rdev(bo->bdev);
993 down_read(&rdev->pm.mclk_lock);
994 r = ttm_vm_ops->fault(vma, vmf);
995 up_read(&rdev->pm.mclk_lock);
996 return r;
997 }
998
999 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
1000 {
1001 struct drm_file *file_priv;
1002 struct radeon_device *rdev;
1003 int r;
1004
1005 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
1006 return -EINVAL;
1007 }
1008
1009 file_priv = filp->private_data;
1010 rdev = file_priv->minor->dev->dev_private;
1011 if (rdev == NULL) {
1012 return -EINVAL;
1013 }
1014 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
1015 if (unlikely(r != 0)) {
1016 return r;
1017 }
1018 if (unlikely(ttm_vm_ops == NULL)) {
1019 ttm_vm_ops = vma->vm_ops;
1020 radeon_ttm_vm_ops = *ttm_vm_ops;
1021 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
1022 }
1023 vma->vm_ops = &radeon_ttm_vm_ops;
1024 return 0;
1025 }
1026
1027 #if defined(CONFIG_DEBUG_FS)
1028
1029 static int radeon_mm_dump_table(struct seq_file *m, void *data)
1030 {
1031 struct drm_info_node *node = (struct drm_info_node *)m->private;
1032 unsigned ttm_pl = *(int *)node->info_ent->data;
1033 struct drm_device *dev = node->minor->dev;
1034 struct radeon_device *rdev = dev->dev_private;
1035 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
1036 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
1037 struct drm_printer p = drm_seq_file_printer(m);
1038
1039 spin_lock(&glob->lru_lock);
1040 drm_mm_print(mm, &p);
1041 spin_unlock(&glob->lru_lock);
1042 return 0;
1043 }
1044
1045 static int ttm_pl_vram = TTM_PL_VRAM;
1046 static int ttm_pl_tt = TTM_PL_TT;
1047
1048 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1049 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1050 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1051 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1052 #ifdef CONFIG_SWIOTLB
1053 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1054 #endif
1055 };
1056
1057 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1058 {
1059 struct radeon_device *rdev = inode->i_private;
1060 i_size_write(inode, rdev->mc.mc_vram_size);
1061 filep->private_data = inode->i_private;
1062 return 0;
1063 }
1064
1065 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1066 size_t size, loff_t *pos)
1067 {
1068 struct radeon_device *rdev = f->private_data;
1069 ssize_t result = 0;
1070 int r;
1071
1072 if (size & 0x3 || *pos & 0x3)
1073 return -EINVAL;
1074
1075 while (size) {
1076 unsigned long flags;
1077 uint32_t value;
1078
1079 if (*pos >= rdev->mc.mc_vram_size)
1080 return result;
1081
1082 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1083 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1084 if (rdev->family >= CHIP_CEDAR)
1085 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1086 value = RREG32(RADEON_MM_DATA);
1087 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1088
1089 r = put_user(value, (uint32_t *)buf);
1090 if (r)
1091 return r;
1092
1093 result += 4;
1094 buf += 4;
1095 *pos += 4;
1096 size -= 4;
1097 }
1098
1099 return result;
1100 }
1101
1102 static const struct file_operations radeon_ttm_vram_fops = {
1103 .owner = THIS_MODULE,
1104 .open = radeon_ttm_vram_open,
1105 .read = radeon_ttm_vram_read,
1106 .llseek = default_llseek
1107 };
1108
1109 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1110 {
1111 struct radeon_device *rdev = inode->i_private;
1112 i_size_write(inode, rdev->mc.gtt_size);
1113 filep->private_data = inode->i_private;
1114 return 0;
1115 }
1116
1117 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1118 size_t size, loff_t *pos)
1119 {
1120 struct radeon_device *rdev = f->private_data;
1121 ssize_t result = 0;
1122 int r;
1123
1124 while (size) {
1125 loff_t p = *pos / PAGE_SIZE;
1126 unsigned off = *pos & ~PAGE_MASK;
1127 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1128 struct page *page;
1129 void *ptr;
1130
1131 if (p >= rdev->gart.num_cpu_pages)
1132 return result;
1133
1134 page = rdev->gart.pages[p];
1135 if (page) {
1136 ptr = kmap(page);
1137 ptr += off;
1138
1139 r = copy_to_user(buf, ptr, cur_size);
1140 kunmap(rdev->gart.pages[p]);
1141 } else
1142 r = clear_user(buf, cur_size);
1143
1144 if (r)
1145 return -EFAULT;
1146
1147 result += cur_size;
1148 buf += cur_size;
1149 *pos += cur_size;
1150 size -= cur_size;
1151 }
1152
1153 return result;
1154 }
1155
1156 static const struct file_operations radeon_ttm_gtt_fops = {
1157 .owner = THIS_MODULE,
1158 .open = radeon_ttm_gtt_open,
1159 .read = radeon_ttm_gtt_read,
1160 .llseek = default_llseek
1161 };
1162
1163 #endif
1164
1165 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1166 {
1167 #if defined(CONFIG_DEBUG_FS)
1168 unsigned count;
1169
1170 struct drm_minor *minor = rdev->ddev->primary;
1171 struct dentry *ent, *root = minor->debugfs_root;
1172
1173 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1174 rdev, &radeon_ttm_vram_fops);
1175 if (IS_ERR(ent))
1176 return PTR_ERR(ent);
1177 rdev->mman.vram = ent;
1178
1179 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1180 rdev, &radeon_ttm_gtt_fops);
1181 if (IS_ERR(ent))
1182 return PTR_ERR(ent);
1183 rdev->mman.gtt = ent;
1184
1185 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1186
1187 #ifdef CONFIG_SWIOTLB
1188 if (!swiotlb_nr_tbl())
1189 --count;
1190 #endif
1191
1192 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1193 #else
1194
1195 return 0;
1196 #endif
1197 }
1198
1199 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1200 {
1201 #if defined(CONFIG_DEBUG_FS)
1202
1203 debugfs_remove(rdev->mman.vram);
1204 rdev->mman.vram = NULL;
1205
1206 debugfs_remove(rdev->mman.gtt);
1207 rdev->mman.gtt = NULL;
1208 #endif
1209 }
Linux with added FPC-III support