drivers/gpu/drm/sti/sti_mixer.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2014
   3  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
   4  *          Fabien Dessenne <fabien.dessenne@st.com>
   5  *          for STMicroelectronics.
   6  * License terms:  GNU General Public License (GPL), version 2
   7  */
   8 #include <linux/seq_file.h>
   9
  10 #include "sti_compositor.h"
  11 #include "sti_mixer.h"
  12 #include "sti_vtg.h"
  13
  14 /* Module parameter to set the background color of the mixer */
  15 static unsigned int bkg_color = 0x000000;
  16 MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB");
  17 module_param_named(bkgcolor, bkg_color, int, 0644);
  18
  19 /* regs offset */
  20 #define GAM_MIXER_CTL      0x00
  21 #define GAM_MIXER_BKC      0x04
  22 #define GAM_MIXER_BCO      0x0C
  23 #define GAM_MIXER_BCS      0x10
  24 #define GAM_MIXER_AVO      0x28
  25 #define GAM_MIXER_AVS      0x2C
  26 #define GAM_MIXER_CRB      0x34
  27 #define GAM_MIXER_ACT      0x38
  28 #define GAM_MIXER_MBP      0x3C
  29 #define GAM_MIXER_MX0      0x80
  30
  31 /* id for depth of CRB reg */
  32 #define GAM_DEPTH_VID0_ID  1
  33 #define GAM_DEPTH_VID1_ID  2
  34 #define GAM_DEPTH_GDP0_ID  3
  35 #define GAM_DEPTH_GDP1_ID  4
  36 #define GAM_DEPTH_GDP2_ID  5
  37 #define GAM_DEPTH_GDP3_ID  6
  38 #define GAM_DEPTH_MASK_ID  7
  39
  40 /* mask in CTL reg */
  41 #define GAM_CTL_BACK_MASK  BIT(0)
  42 #define GAM_CTL_VID0_MASK  BIT(1)
  43 #define GAM_CTL_VID1_MASK  BIT(2)
  44 #define GAM_CTL_GDP0_MASK  BIT(3)
  45 #define GAM_CTL_GDP1_MASK  BIT(4)
  46 #define GAM_CTL_GDP2_MASK  BIT(5)
  47 #define GAM_CTL_GDP3_MASK  BIT(6)
  48 #define GAM_CTL_CURSOR_MASK BIT(9)
  49
  50 const char *sti_mixer_to_str(struct sti_mixer *mixer)
  51 {
  52         switch (mixer->id) {
  53         case STI_MIXER_MAIN:
  54                 return "MAIN_MIXER";
  55         case STI_MIXER_AUX:
  56                 return "AUX_MIXER";
  57         default:
  58                 return "<UNKNOWN MIXER>";
  59         }
  60 }
  61
  62 static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
  63 {
  64         return readl(mixer->regs + reg_id);
  65 }
  66
  67 static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
  68                                        u32 reg_id, u32 val)
  69 {
  70         writel(val, mixer->regs + reg_id);
  71 }
  72
  73 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
  74                                    sti_mixer_reg_read(mixer, reg))
  75
  76 static void mixer_dbg_ctl(struct seq_file *s, int val)
  77 {
  78         unsigned int i;
  79         int count = 0;
  80         char *const disp_layer[] = {"BKG", "VID0", "VID1", "GDP0",
  81                                     "GDP1", "GDP2", "GDP3"};
  82
  83         seq_puts(s, "\tEnabled: ");
  84         for (i = 0; i < 7; i++) {
  85                 if (val & 1) {
  86                         seq_printf(s, "%s ", disp_layer[i]);
  87                         count++;
  88                 }
  89                 val = val >> 1;
  90         }
  91
  92         val = val >> 2;
  93         if (val & 1) {
  94                 seq_puts(s, "CURS ");
  95                 count++;
  96         }
  97         if (!count)
  98                 seq_puts(s, "Nothing");
  99 }
 100
 101 static void mixer_dbg_crb(struct seq_file *s, int val)
 102 {
 103         int i;
 104
 105         seq_puts(s, "\tDepth: ");
 106         for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
 107                 switch (val & GAM_DEPTH_MASK_ID) {
 108                 case GAM_DEPTH_VID0_ID:
 109                         seq_puts(s, "VID0");
 110                         break;
 111                 case GAM_DEPTH_VID1_ID:
 112                         seq_puts(s, "VID1");
 113                         break;
 114                 case GAM_DEPTH_GDP0_ID:
 115                         seq_puts(s, "GDP0");
 116                         break;
 117                 case GAM_DEPTH_GDP1_ID:
 118                         seq_puts(s, "GDP1");
 119                         break;
 120                 case GAM_DEPTH_GDP2_ID:
 121                         seq_puts(s, "GDP2");
 122                         break;
 123                 case GAM_DEPTH_GDP3_ID:
 124                         seq_puts(s, "GDP3");
 125                         break;
 126                 default:
 127                         seq_puts(s, "---");
 128                 }
 129
 130                 if (i < GAM_MIXER_NB_DEPTH_LEVEL - 1)
 131                         seq_puts(s, " < ");
 132                 val = val >> 3;
 133         }
 134 }
 135
 136 static void mixer_dbg_mxn(struct seq_file *s, void *addr)
 137 {
 138         int i;
 139
 140         for (i = 1; i < 8; i++)
 141                 seq_printf(s, "-0x%08X", (int)readl(addr + i * 4));
 142 }
 143
 144 static int mixer_dbg_show(struct seq_file *s, void *arg)
 145 {
 146         struct drm_info_node *node = s->private;
 147         struct sti_mixer *mixer = (struct sti_mixer *)node->info_ent->data;
 148
 149         seq_printf(s, "%s: (vaddr = 0x%p)",
 150                    sti_mixer_to_str(mixer), mixer->regs);
 151
 152         DBGFS_DUMP(GAM_MIXER_CTL);
 153         mixer_dbg_ctl(s, sti_mixer_reg_read(mixer, GAM_MIXER_CTL));
 154         DBGFS_DUMP(GAM_MIXER_BKC);
 155         DBGFS_DUMP(GAM_MIXER_BCO);
 156         DBGFS_DUMP(GAM_MIXER_BCS);
 157         DBGFS_DUMP(GAM_MIXER_AVO);
 158         DBGFS_DUMP(GAM_MIXER_AVS);
 159         DBGFS_DUMP(GAM_MIXER_CRB);
 160         mixer_dbg_crb(s, sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
 161         DBGFS_DUMP(GAM_MIXER_ACT);
 162         DBGFS_DUMP(GAM_MIXER_MBP);
 163         DBGFS_DUMP(GAM_MIXER_MX0);
 164         mixer_dbg_mxn(s, mixer->regs + GAM_MIXER_MX0);
 165         seq_puts(s, "\n");
 166
 167         return 0;
 168 }
 169
 170 static struct drm_info_list mixer0_debugfs_files[] = {
 171         { "mixer_main", mixer_dbg_show, 0, NULL },
 172 };
 173
 174 static struct drm_info_list mixer1_debugfs_files[] = {
 175         { "mixer_aux", mixer_dbg_show, 0, NULL },
 176 };
 177
 178 int sti_mixer_debugfs_init(struct sti_mixer *mixer, struct drm_minor *minor)
 179 {
 180         unsigned int i;
 181         struct drm_info_list *mixer_debugfs_files;
 182         int nb_files;
 183
 184         switch (mixer->id) {
 185         case STI_MIXER_MAIN:
 186                 mixer_debugfs_files = mixer0_debugfs_files;
 187                 nb_files = ARRAY_SIZE(mixer0_debugfs_files);
 188                 break;
 189         case STI_MIXER_AUX:
 190                 mixer_debugfs_files = mixer1_debugfs_files;
 191                 nb_files = ARRAY_SIZE(mixer1_debugfs_files);
 192                 break;
 193         default:
 194                 return -EINVAL;
 195         }
 196
 197         for (i = 0; i < nb_files; i++)
 198                 mixer_debugfs_files[i].data = mixer;
 199
 200         return drm_debugfs_create_files(mixer_debugfs_files,
 201                                         nb_files,
 202                                         minor->debugfs_root, minor);
 203 }
 204
 205 void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
 206 {
 207         u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
 208
 209         val &= ~GAM_CTL_BACK_MASK;
 210         val |= enable;
 211         sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
 212 }
 213
 214 static void sti_mixer_set_background_color(struct sti_mixer *mixer,
 215                                            unsigned int rgb)
 216 {
 217         sti_mixer_reg_write(mixer, GAM_MIXER_BKC, rgb);
 218 }
 219
 220 static void sti_mixer_set_background_area(struct sti_mixer *mixer,
 221                                           struct drm_display_mode *mode)
 222 {
 223         u32 ydo, xdo, yds, xds;
 224
 225         ydo = sti_vtg_get_line_number(*mode, 0);
 226         yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
 227         xdo = sti_vtg_get_pixel_number(*mode, 0);
 228         xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
 229
 230         sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
 231         sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
 232 }
 233
 234 int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane)
 235 {
 236         int plane_id, depth = plane->drm_plane.state->normalized_zpos;
 237         unsigned int i;
 238         u32 mask, val;
 239
 240         switch (plane->desc) {
 241         case STI_GDP_0:
 242                 plane_id = GAM_DEPTH_GDP0_ID;
 243                 break;
 244         case STI_GDP_1:
 245                 plane_id = GAM_DEPTH_GDP1_ID;
 246                 break;
 247         case STI_GDP_2:
 248                 plane_id = GAM_DEPTH_GDP2_ID;
 249                 break;
 250         case STI_GDP_3:
 251                 plane_id = GAM_DEPTH_GDP3_ID;
 252                 break;
 253         case STI_HQVDP_0:
 254                 plane_id = GAM_DEPTH_VID0_ID;
 255                 break;
 256         case STI_CURSOR:
 257                 /* no need to set depth for cursor */
 258                 return 0;
 259         default:
 260                 DRM_ERROR("Unknown plane %d\n", plane->desc);
 261                 return 1;
 262         }
 263
 264         /* Search if a previous depth was already assigned to the plane */
 265         val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
 266         for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
 267                 mask = GAM_DEPTH_MASK_ID << (3 * i);
 268                 if ((val & mask) == plane_id << (3 * i))
 269                         break;
 270         }
 271
 272         mask |= GAM_DEPTH_MASK_ID << (3 * depth);
 273         plane_id = plane_id << (3 * depth);
 274
 275         DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
 276                          sti_plane_to_str(plane), depth);
 277         dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
 278                 plane_id, mask);
 279
 280         val &= ~mask;
 281         val |= plane_id;
 282         sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
 283
 284         dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
 285                 sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
 286         return 0;
 287 }
 288
 289 int sti_mixer_active_video_area(struct sti_mixer *mixer,
 290                                 struct drm_display_mode *mode)
 291 {
 292         u32 ydo, xdo, yds, xds;
 293
 294         ydo = sti_vtg_get_line_number(*mode, 0);
 295         yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
 296         xdo = sti_vtg_get_pixel_number(*mode, 0);
 297         xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
 298
 299         DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
 300                          sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
 301         sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
 302         sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);
 303
 304         sti_mixer_set_background_color(mixer, bkg_color);
 305
 306         sti_mixer_set_background_area(mixer, mode);
 307         sti_mixer_set_background_status(mixer, true);
 308         return 0;
 309 }
 310
 311 static u32 sti_mixer_get_plane_mask(struct sti_plane *plane)
 312 {
 313         switch (plane->desc) {
 314         case STI_BACK:
 315                 return GAM_CTL_BACK_MASK;
 316         case STI_GDP_0:
 317                 return GAM_CTL_GDP0_MASK;
 318         case STI_GDP_1:
 319                 return GAM_CTL_GDP1_MASK;
 320         case STI_GDP_2:
 321                 return GAM_CTL_GDP2_MASK;
 322         case STI_GDP_3:
 323                 return GAM_CTL_GDP3_MASK;
 324         case STI_HQVDP_0:
 325                 return GAM_CTL_VID0_MASK;
 326         case STI_CURSOR:
 327                 return GAM_CTL_CURSOR_MASK;
 328         default:
 329                 return 0;
 330         }
 331 }
 332
 333 int sti_mixer_set_plane_status(struct sti_mixer *mixer,
 334                                struct sti_plane *plane, bool status)
 335 {
 336         u32 mask, val;
 337
 338         DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
 339                          sti_mixer_to_str(mixer), sti_plane_to_str(plane));
 340
 341         mask = sti_mixer_get_plane_mask(plane);
 342         if (!mask) {
 343                 DRM_ERROR("Can't find layer mask\n");
 344                 return -EINVAL;
 345         }
 346
 347         val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
 348         val &= ~mask;
 349         val |= status ? mask : 0;
 350         sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
 351
 352         return 0;
 353 }
 354
 355 struct sti_mixer *sti_mixer_create(struct device *dev,
 356                                    struct drm_device *drm_dev,
 357                                    int id,
 358                                    void __iomem *baseaddr)
 359 {
 360         struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
 361
 362         dev_dbg(dev, "%s\n", __func__);
 363         if (!mixer) {
 364                 DRM_ERROR("Failed to allocated memory for mixer\n");
 365                 return NULL;
 366         }
 367         mixer->regs = baseaddr;
 368         mixer->dev = dev;
 369         mixer->id = id;
 370
 371         DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
 372                          sti_mixer_to_str(mixer), mixer->regs);
 373
 374         return mixer;
 375 }