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drm/exynos: Stop using drm_framebuffer_unregister_private
[linux/fpc-iii.git] / drivers / gpu / drm / tegra / sor.c
bloba8f528925009e67938dc7e7b84b7d33b418733a3
1 /*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
13 #include <linux/io.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19
20 #include <soc/tegra/pmc.h>
21
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_dp_helper.h>
24 #include <drm/drm_panel.h>
25
26 #include "dc.h"
27 #include "drm.h"
28 #include "sor.h"
29
30 #define SOR_REKEY 0x38
31
32 struct tegra_sor_hdmi_settings {
33 unsigned long frequency;
34
35 u8 vcocap;
36 u8 ichpmp;
37 u8 loadadj;
38 u8 termadj;
39 u8 tx_pu;
40 u8 bg_vref;
41
42 u8 drive_current[4];
43 u8 preemphasis[4];
44 };
45
46 #if 1
47 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
48 {
49 .frequency = 54000000,
50 .vcocap = 0x0,
51 .ichpmp = 0x1,
52 .loadadj = 0x3,
53 .termadj = 0x9,
54 .tx_pu = 0x10,
55 .bg_vref = 0x8,
56 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
57 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
58 }, {
59 .frequency = 75000000,
60 .vcocap = 0x3,
61 .ichpmp = 0x1,
62 .loadadj = 0x3,
63 .termadj = 0x9,
64 .tx_pu = 0x40,
65 .bg_vref = 0x8,
66 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
67 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
68 }, {
69 .frequency = 150000000,
70 .vcocap = 0x3,
71 .ichpmp = 0x1,
72 .loadadj = 0x3,
73 .termadj = 0x9,
74 .tx_pu = 0x66,
75 .bg_vref = 0x8,
76 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
77 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
78 }, {
79 .frequency = 300000000,
80 .vcocap = 0x3,
81 .ichpmp = 0x1,
82 .loadadj = 0x3,
83 .termadj = 0x9,
84 .tx_pu = 0x66,
85 .bg_vref = 0xa,
86 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
87 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
88 }, {
89 .frequency = 600000000,
90 .vcocap = 0x3,
91 .ichpmp = 0x1,
92 .loadadj = 0x3,
93 .termadj = 0x9,
94 .tx_pu = 0x66,
95 .bg_vref = 0x8,
96 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
97 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
98 },
99 };
100 #else
101 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
102 {
103 .frequency = 75000000,
104 .vcocap = 0x3,
105 .ichpmp = 0x1,
106 .loadadj = 0x3,
107 .termadj = 0x9,
108 .tx_pu = 0x40,
109 .bg_vref = 0x8,
110 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
111 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
112 }, {
113 .frequency = 150000000,
114 .vcocap = 0x3,
115 .ichpmp = 0x1,
116 .loadadj = 0x3,
117 .termadj = 0x9,
118 .tx_pu = 0x66,
119 .bg_vref = 0x8,
120 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
121 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
122 }, {
123 .frequency = 300000000,
124 .vcocap = 0x3,
125 .ichpmp = 0x6,
126 .loadadj = 0x3,
127 .termadj = 0x9,
128 .tx_pu = 0x66,
129 .bg_vref = 0xf,
130 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
131 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
132 }, {
133 .frequency = 600000000,
134 .vcocap = 0x3,
135 .ichpmp = 0xa,
136 .loadadj = 0x3,
137 .termadj = 0xb,
138 .tx_pu = 0x66,
139 .bg_vref = 0xe,
140 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
141 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
142 },
143 };
144 #endif
145
146 struct tegra_sor_soc {
147 bool supports_edp;
148 bool supports_lvds;
149 bool supports_hdmi;
150 bool supports_dp;
151
152 const struct tegra_sor_hdmi_settings *settings;
153 unsigned int num_settings;
154
155 const u8 *xbar_cfg;
156 };
157
158 struct tegra_sor;
159
160 struct tegra_sor_ops {
161 const char *name;
162 int (*probe)(struct tegra_sor *sor);
163 int (*remove)(struct tegra_sor *sor);
164 };
165
166 struct tegra_sor {
167 struct host1x_client client;
168 struct tegra_output output;
169 struct device *dev;
170
171 const struct tegra_sor_soc *soc;
172 void __iomem *regs;
173
174 struct reset_control *rst;
175 struct clk *clk_parent;
176 struct clk *clk_brick;
177 struct clk *clk_safe;
178 struct clk *clk_src;
179 struct clk *clk_dp;
180 struct clk *clk;
181
182 struct drm_dp_aux *aux;
183
184 struct drm_info_list *debugfs_files;
185 struct drm_minor *minor;
186 struct dentry *debugfs;
187
188 const struct tegra_sor_ops *ops;
189
190 /* for HDMI 2.0 */
191 struct tegra_sor_hdmi_settings *settings;
192 unsigned int num_settings;
193
194 struct regulator *avdd_io_supply;
195 struct regulator *vdd_pll_supply;
196 struct regulator *hdmi_supply;
197 };
198
199 struct tegra_sor_state {
200 struct drm_connector_state base;
201
202 unsigned int bpc;
203 };
204
205 static inline struct tegra_sor_state *
206 to_sor_state(struct drm_connector_state *state)
207 {
208 return container_of(state, struct tegra_sor_state, base);
209 }
210
211 struct tegra_sor_config {
212 u32 bits_per_pixel;
213
214 u32 active_polarity;
215 u32 active_count;
216 u32 tu_size;
217 u32 active_frac;
218 u32 watermark;
219
220 u32 hblank_symbols;
221 u32 vblank_symbols;
222 };
223
224 static inline struct tegra_sor *
225 host1x_client_to_sor(struct host1x_client *client)
226 {
227 return container_of(client, struct tegra_sor, client);
228 }
229
230 static inline struct tegra_sor *to_sor(struct tegra_output *output)
231 {
232 return container_of(output, struct tegra_sor, output);
233 }
234
235 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset)
236 {
237 return readl(sor->regs + (offset << 2));
238 }
239
240 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
241 unsigned long offset)
242 {
243 writel(value, sor->regs + (offset << 2));
244 }
245
246 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
247 {
248 int err;
249
250 clk_disable_unprepare(sor->clk);
251
252 err = clk_set_parent(sor->clk, parent);
253 if (err < 0)
254 return err;
255
256 err = clk_prepare_enable(sor->clk);
257 if (err < 0)
258 return err;
259
260 return 0;
261 }
262
263 struct tegra_clk_sor_brick {
264 struct clk_hw hw;
265 struct tegra_sor *sor;
266 };
267
268 static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw)
269 {
270 return container_of(hw, struct tegra_clk_sor_brick, hw);
271 }
272
273 static const char * const tegra_clk_sor_brick_parents[] = {
274 "pll_d2_out0", "pll_dp"
275 };
276
277 static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index)
278 {
279 struct tegra_clk_sor_brick *brick = to_brick(hw);
280 struct tegra_sor *sor = brick->sor;
281 u32 value;
282
283 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
284 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
285
286 switch (index) {
287 case 0:
288 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
289 break;
290
291 case 1:
292 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
293 break;
294 }
295
296 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
297
298 return 0;
299 }
300
301 static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw)
302 {
303 struct tegra_clk_sor_brick *brick = to_brick(hw);
304 struct tegra_sor *sor = brick->sor;
305 u8 parent = U8_MAX;
306 u32 value;
307
308 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
309
310 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
311 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
312 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
313 parent = 0;
314 break;
315
316 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
317 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
318 parent = 1;
319 break;
320 }
321
322 return parent;
323 }
324
325 static const struct clk_ops tegra_clk_sor_brick_ops = {
326 .set_parent = tegra_clk_sor_brick_set_parent,
327 .get_parent = tegra_clk_sor_brick_get_parent,
328 };
329
330 static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor,
331 const char *name)
332 {
333 struct tegra_clk_sor_brick *brick;
334 struct clk_init_data init;
335 struct clk *clk;
336
337 brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL);
338 if (!brick)
339 return ERR_PTR(-ENOMEM);
340
341 brick->sor = sor;
342
343 init.name = name;
344 init.flags = 0;
345 init.parent_names = tegra_clk_sor_brick_parents;
346 init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents);
347 init.ops = &tegra_clk_sor_brick_ops;
348
349 brick->hw.init = &init;
350
351 clk = devm_clk_register(sor->dev, &brick->hw);
352
353 return clk;
354 }
355
356 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
357 struct drm_dp_link *link)
358 {
359 unsigned int i;
360 u8 pattern;
361 u32 value;
362 int err;
363
364 /* setup lane parameters */
365 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
366 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
367 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
368 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
369 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
370
371 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
372 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
373 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
374 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
375 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
376
377 value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
378 SOR_LANE_POSTCURSOR_LANE2(0x00) |
379 SOR_LANE_POSTCURSOR_LANE1(0x00) |
380 SOR_LANE_POSTCURSOR_LANE0(0x00);
381 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
382
383 /* disable LVDS mode */
384 tegra_sor_writel(sor, 0, SOR_LVDS);
385
386 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
387 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
388 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
389 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
390 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
391
392 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
393 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
394 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
395 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
396
397 usleep_range(10, 100);
398
399 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
400 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
401 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
402 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
403
404 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
405 if (err < 0)
406 return err;
407
408 for (i = 0, value = 0; i < link->num_lanes; i++) {
409 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
410 SOR_DP_TPG_SCRAMBLER_NONE |
411 SOR_DP_TPG_PATTERN_TRAIN1;
412 value = (value << 8) | lane;
413 }
414
415 tegra_sor_writel(sor, value, SOR_DP_TPG);
416
417 pattern = DP_TRAINING_PATTERN_1;
418
419 err = drm_dp_aux_train(sor->aux, link, pattern);
420 if (err < 0)
421 return err;
422
423 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
424 value |= SOR_DP_SPARE_SEQ_ENABLE;
425 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
426 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
427 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
428
429 for (i = 0, value = 0; i < link->num_lanes; i++) {
430 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
431 SOR_DP_TPG_SCRAMBLER_NONE |
432 SOR_DP_TPG_PATTERN_TRAIN2;
433 value = (value << 8) | lane;
434 }
435
436 tegra_sor_writel(sor, value, SOR_DP_TPG);
437
438 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
439
440 err = drm_dp_aux_train(sor->aux, link, pattern);
441 if (err < 0)
442 return err;
443
444 for (i = 0, value = 0; i < link->num_lanes; i++) {
445 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
446 SOR_DP_TPG_SCRAMBLER_GALIOS |
447 SOR_DP_TPG_PATTERN_NONE;
448 value = (value << 8) | lane;
449 }
450
451 tegra_sor_writel(sor, value, SOR_DP_TPG);
452
453 pattern = DP_TRAINING_PATTERN_DISABLE;
454
455 err = drm_dp_aux_train(sor->aux, link, pattern);
456 if (err < 0)
457 return err;
458
459 return 0;
460 }
461
462 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
463 {
464 u32 mask = 0x08, adj = 0, value;
465
466 /* enable pad calibration logic */
467 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
468 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
469 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
470
471 value = tegra_sor_readl(sor, SOR_PLL1);
472 value |= SOR_PLL1_TMDS_TERM;
473 tegra_sor_writel(sor, value, SOR_PLL1);
474
475 while (mask) {
476 adj |= mask;
477
478 value = tegra_sor_readl(sor, SOR_PLL1);
479 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
480 value |= SOR_PLL1_TMDS_TERMADJ(adj);
481 tegra_sor_writel(sor, value, SOR_PLL1);
482
483 usleep_range(100, 200);
484
485 value = tegra_sor_readl(sor, SOR_PLL1);
486 if (value & SOR_PLL1_TERM_COMPOUT)
487 adj &= ~mask;
488
489 mask >>= 1;
490 }
491
492 value = tegra_sor_readl(sor, SOR_PLL1);
493 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
494 value |= SOR_PLL1_TMDS_TERMADJ(adj);
495 tegra_sor_writel(sor, value, SOR_PLL1);
496
497 /* disable pad calibration logic */
498 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
499 value |= SOR_DP_PADCTL_PAD_CAL_PD;
500 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
501 }
502
503 static void tegra_sor_super_update(struct tegra_sor *sor)
504 {
505 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
506 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
507 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
508 }
509
510 static void tegra_sor_update(struct tegra_sor *sor)
511 {
512 tegra_sor_writel(sor, 0, SOR_STATE0);
513 tegra_sor_writel(sor, 1, SOR_STATE0);
514 tegra_sor_writel(sor, 0, SOR_STATE0);
515 }
516
517 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
518 {
519 u32 value;
520
521 value = tegra_sor_readl(sor, SOR_PWM_DIV);
522 value &= ~SOR_PWM_DIV_MASK;
523 value |= 0x400; /* period */
524 tegra_sor_writel(sor, value, SOR_PWM_DIV);
525
526 value = tegra_sor_readl(sor, SOR_PWM_CTL);
527 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
528 value |= 0x400; /* duty cycle */
529 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
530 value |= SOR_PWM_CTL_TRIGGER;
531 tegra_sor_writel(sor, value, SOR_PWM_CTL);
532
533 timeout = jiffies + msecs_to_jiffies(timeout);
534
535 while (time_before(jiffies, timeout)) {
536 value = tegra_sor_readl(sor, SOR_PWM_CTL);
537 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
538 return 0;
539
540 usleep_range(25, 100);
541 }
542
543 return -ETIMEDOUT;
544 }
545
546 static int tegra_sor_attach(struct tegra_sor *sor)
547 {
548 unsigned long value, timeout;
549
550 /* wake up in normal mode */
551 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
552 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
553 value |= SOR_SUPER_STATE_MODE_NORMAL;
554 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
555 tegra_sor_super_update(sor);
556
557 /* attach */
558 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
559 value |= SOR_SUPER_STATE_ATTACHED;
560 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
561 tegra_sor_super_update(sor);
562
563 timeout = jiffies + msecs_to_jiffies(250);
564
565 while (time_before(jiffies, timeout)) {
566 value = tegra_sor_readl(sor, SOR_TEST);
567 if ((value & SOR_TEST_ATTACHED) != 0)
568 return 0;
569
570 usleep_range(25, 100);
571 }
572
573 return -ETIMEDOUT;
574 }
575
576 static int tegra_sor_wakeup(struct tegra_sor *sor)
577 {
578 unsigned long value, timeout;
579
580 timeout = jiffies + msecs_to_jiffies(250);
581
582 /* wait for head to wake up */
583 while (time_before(jiffies, timeout)) {
584 value = tegra_sor_readl(sor, SOR_TEST);
585 value &= SOR_TEST_HEAD_MODE_MASK;
586
587 if (value == SOR_TEST_HEAD_MODE_AWAKE)
588 return 0;
589
590 usleep_range(25, 100);
591 }
592
593 return -ETIMEDOUT;
594 }
595
596 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
597 {
598 u32 value;
599
600 value = tegra_sor_readl(sor, SOR_PWR);
601 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
602 tegra_sor_writel(sor, value, SOR_PWR);
603
604 timeout = jiffies + msecs_to_jiffies(timeout);
605
606 while (time_before(jiffies, timeout)) {
607 value = tegra_sor_readl(sor, SOR_PWR);
608 if ((value & SOR_PWR_TRIGGER) == 0)
609 return 0;
610
611 usleep_range(25, 100);
612 }
613
614 return -ETIMEDOUT;
615 }
616
617 struct tegra_sor_params {
618 /* number of link clocks per line */
619 unsigned int num_clocks;
620 /* ratio between input and output */
621 u64 ratio;
622 /* precision factor */
623 u64 precision;
624
625 unsigned int active_polarity;
626 unsigned int active_count;
627 unsigned int active_frac;
628 unsigned int tu_size;
629 unsigned int error;
630 };
631
632 static int tegra_sor_compute_params(struct tegra_sor *sor,
633 struct tegra_sor_params *params,
634 unsigned int tu_size)
635 {
636 u64 active_sym, active_count, frac, approx;
637 u32 active_polarity, active_frac = 0;
638 const u64 f = params->precision;
639 s64 error;
640
641 active_sym = params->ratio * tu_size;
642 active_count = div_u64(active_sym, f) * f;
643 frac = active_sym - active_count;
644
645 /* fraction < 0.5 */
646 if (frac >= (f / 2)) {
647 active_polarity = 1;
648 frac = f - frac;
649 } else {
650 active_polarity = 0;
651 }
652
653 if (frac != 0) {
654 frac = div_u64(f * f, frac); /* 1/fraction */
655 if (frac <= (15 * f)) {
656 active_frac = div_u64(frac, f);
657
658 /* round up */
659 if (active_polarity)
660 active_frac++;
661 } else {
662 active_frac = active_polarity ? 1 : 15;
663 }
664 }
665
666 if (active_frac == 1)
667 active_polarity = 0;
668
669 if (active_polarity == 1) {
670 if (active_frac) {
671 approx = active_count + (active_frac * (f - 1)) * f;
672 approx = div_u64(approx, active_frac * f);
673 } else {
674 approx = active_count + f;
675 }
676 } else {
677 if (active_frac)
678 approx = active_count + div_u64(f, active_frac);
679 else
680 approx = active_count;
681 }
682
683 error = div_s64(active_sym - approx, tu_size);
684 error *= params->num_clocks;
685
686 if (error <= 0 && abs(error) < params->error) {
687 params->active_count = div_u64(active_count, f);
688 params->active_polarity = active_polarity;
689 params->active_frac = active_frac;
690 params->error = abs(error);
691 params->tu_size = tu_size;
692
693 if (error == 0)
694 return true;
695 }
696
697 return false;
698 }
699
700 static int tegra_sor_compute_config(struct tegra_sor *sor,
701 const struct drm_display_mode *mode,
702 struct tegra_sor_config *config,
703 struct drm_dp_link *link)
704 {
705 const u64 f = 100000, link_rate = link->rate * 1000;
706 const u64 pclk = mode->clock * 1000;
707 u64 input, output, watermark, num;
708 struct tegra_sor_params params;
709 u32 num_syms_per_line;
710 unsigned int i;
711
712 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
713 return -EINVAL;
714
715 output = link_rate * 8 * link->num_lanes;
716 input = pclk * config->bits_per_pixel;
717
718 if (input >= output)
719 return -ERANGE;
720
721 memset(&params, 0, sizeof(params));
722 params.ratio = div64_u64(input * f, output);
723 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
724 params.precision = f;
725 params.error = 64 * f;
726 params.tu_size = 64;
727
728 for (i = params.tu_size; i >= 32; i--)
729 if (tegra_sor_compute_params(sor, &params, i))
730 break;
731
732 if (params.active_frac == 0) {
733 config->active_polarity = 0;
734 config->active_count = params.active_count;
735
736 if (!params.active_polarity)
737 config->active_count--;
738
739 config->tu_size = params.tu_size;
740 config->active_frac = 1;
741 } else {
742 config->active_polarity = params.active_polarity;
743 config->active_count = params.active_count;
744 config->active_frac = params.active_frac;
745 config->tu_size = params.tu_size;
746 }
747
748 dev_dbg(sor->dev,
749 "polarity: %d active count: %d tu size: %d active frac: %d\n",
750 config->active_polarity, config->active_count,
751 config->tu_size, config->active_frac);
752
753 watermark = params.ratio * config->tu_size * (f - params.ratio);
754 watermark = div_u64(watermark, f);
755
756 watermark = div_u64(watermark + params.error, f);
757 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
758 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
759 (link->num_lanes * 8);
760
761 if (config->watermark > 30) {
762 config->watermark = 30;
763 dev_err(sor->dev,
764 "unable to compute TU size, forcing watermark to %u\n",
765 config->watermark);
766 } else if (config->watermark > num_syms_per_line) {
767 config->watermark = num_syms_per_line;
768 dev_err(sor->dev, "watermark too high, forcing to %u\n",
769 config->watermark);
770 }
771
772 /* compute the number of symbols per horizontal blanking interval */
773 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
774 config->hblank_symbols = div_u64(num, pclk);
775
776 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
777 config->hblank_symbols -= 3;
778
779 config->hblank_symbols -= 12 / link->num_lanes;
780
781 /* compute the number of symbols per vertical blanking interval */
782 num = (mode->hdisplay - 25) * link_rate;
783 config->vblank_symbols = div_u64(num, pclk);
784 config->vblank_symbols -= 36 / link->num_lanes + 4;
785
786 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
787 config->vblank_symbols);
788
789 return 0;
790 }
791
792 static void tegra_sor_apply_config(struct tegra_sor *sor,
793 const struct tegra_sor_config *config)
794 {
795 u32 value;
796
797 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
798 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
799 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
800 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
801
802 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
803 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
804 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
805
806 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
807 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
808
809 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
810 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
811
812 if (config->active_polarity)
813 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
814 else
815 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
816
817 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
818 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
819 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
820
821 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
822 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
823 value |= config->hblank_symbols & 0xffff;
824 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
825
826 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
827 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
828 value |= config->vblank_symbols & 0xffff;
829 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
830 }
831
832 static void tegra_sor_mode_set(struct tegra_sor *sor,
833 const struct drm_display_mode *mode,
834 struct tegra_sor_state *state)
835 {
836 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
837 unsigned int vbe, vse, hbe, hse, vbs, hbs;
838 u32 value;
839
840 value = tegra_sor_readl(sor, SOR_STATE1);
841 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
842 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
843 value &= ~SOR_STATE_ASY_OWNER_MASK;
844
845 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
846 SOR_STATE_ASY_OWNER(dc->pipe + 1);
847
848 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
849 value &= ~SOR_STATE_ASY_HSYNCPOL;
850
851 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
852 value |= SOR_STATE_ASY_HSYNCPOL;
853
854 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
855 value &= ~SOR_STATE_ASY_VSYNCPOL;
856
857 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
858 value |= SOR_STATE_ASY_VSYNCPOL;
859
860 switch (state->bpc) {
861 case 16:
862 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
863 break;
864
865 case 12:
866 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
867 break;
868
869 case 10:
870 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
871 break;
872
873 case 8:
874 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
875 break;
876
877 case 6:
878 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
879 break;
880
881 default:
882 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
883 break;
884 }
885
886 tegra_sor_writel(sor, value, SOR_STATE1);
887
888 /*
889 * TODO: The video timing programming below doesn't seem to match the
890 * register definitions.
891 */
892
893 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
894 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));
895
896 /* sync end = sync width - 1 */
897 vse = mode->vsync_end - mode->vsync_start - 1;
898 hse = mode->hsync_end - mode->hsync_start - 1;
899
900 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
901 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));
902
903 /* blank end = sync end + back porch */
904 vbe = vse + (mode->vtotal - mode->vsync_end);
905 hbe = hse + (mode->htotal - mode->hsync_end);
906
907 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
908 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));
909
910 /* blank start = blank end + active */
911 vbs = vbe + mode->vdisplay;
912 hbs = hbe + mode->hdisplay;
913
914 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
915 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));
916
917 /* XXX interlacing support */
918 tegra_sor_writel(sor, 0x001, SOR_HEAD_STATE5(dc->pipe));
919 }
920
921 static int tegra_sor_detach(struct tegra_sor *sor)
922 {
923 unsigned long value, timeout;
924
925 /* switch to safe mode */
926 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
927 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
928 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
929 tegra_sor_super_update(sor);
930
931 timeout = jiffies + msecs_to_jiffies(250);
932
933 while (time_before(jiffies, timeout)) {
934 value = tegra_sor_readl(sor, SOR_PWR);
935 if (value & SOR_PWR_MODE_SAFE)
936 break;
937 }
938
939 if ((value & SOR_PWR_MODE_SAFE) == 0)
940 return -ETIMEDOUT;
941
942 /* go to sleep */
943 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
944 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
945 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
946 tegra_sor_super_update(sor);
947
948 /* detach */
949 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
950 value &= ~SOR_SUPER_STATE_ATTACHED;
951 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
952 tegra_sor_super_update(sor);
953
954 timeout = jiffies + msecs_to_jiffies(250);
955
956 while (time_before(jiffies, timeout)) {
957 value = tegra_sor_readl(sor, SOR_TEST);
958 if ((value & SOR_TEST_ATTACHED) == 0)
959 break;
960
961 usleep_range(25, 100);
962 }
963
964 if ((value & SOR_TEST_ATTACHED) != 0)
965 return -ETIMEDOUT;
966
967 return 0;
968 }
969
970 static int tegra_sor_power_down(struct tegra_sor *sor)
971 {
972 unsigned long value, timeout;
973 int err;
974
975 value = tegra_sor_readl(sor, SOR_PWR);
976 value &= ~SOR_PWR_NORMAL_STATE_PU;
977 value |= SOR_PWR_TRIGGER;
978 tegra_sor_writel(sor, value, SOR_PWR);
979
980 timeout = jiffies + msecs_to_jiffies(250);
981
982 while (time_before(jiffies, timeout)) {
983 value = tegra_sor_readl(sor, SOR_PWR);
984 if ((value & SOR_PWR_TRIGGER) == 0)
985 return 0;
986
987 usleep_range(25, 100);
988 }
989
990 if ((value & SOR_PWR_TRIGGER) != 0)
991 return -ETIMEDOUT;
992
993 /* switch to safe parent clock */
994 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
995 if (err < 0)
996 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
997
998 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
999 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1000 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1001 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1002
1003 /* stop lane sequencer */
1004 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1005 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1006 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1007
1008 timeout = jiffies + msecs_to_jiffies(250);
1009
1010 while (time_before(jiffies, timeout)) {
1011 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1012 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1013 break;
1014
1015 usleep_range(25, 100);
1016 }
1017
1018 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1019 return -ETIMEDOUT;
1020
1021 value = tegra_sor_readl(sor, SOR_PLL2);
1022 value |= SOR_PLL2_PORT_POWERDOWN;
1023 tegra_sor_writel(sor, value, SOR_PLL2);
1024
1025 usleep_range(20, 100);
1026
1027 value = tegra_sor_readl(sor, SOR_PLL0);
1028 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1029 tegra_sor_writel(sor, value, SOR_PLL0);
1030
1031 value = tegra_sor_readl(sor, SOR_PLL2);
1032 value |= SOR_PLL2_SEQ_PLLCAPPD;
1033 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1034 tegra_sor_writel(sor, value, SOR_PLL2);
1035
1036 usleep_range(20, 100);
1037
1038 return 0;
1039 }
1040
1041 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1042 {
1043 u32 value;
1044
1045 timeout = jiffies + msecs_to_jiffies(timeout);
1046
1047 while (time_before(jiffies, timeout)) {
1048 value = tegra_sor_readl(sor, SOR_CRCA);
1049 if (value & SOR_CRCA_VALID)
1050 return 0;
1051
1052 usleep_range(100, 200);
1053 }
1054
1055 return -ETIMEDOUT;
1056 }
1057
1058 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1059 {
1060 struct drm_info_node *node = s->private;
1061 struct tegra_sor *sor = node->info_ent->data;
1062 struct drm_crtc *crtc = sor->output.encoder.crtc;
1063 struct drm_device *drm = node->minor->dev;
1064 int err = 0;
1065 u32 value;
1066
1067 drm_modeset_lock_all(drm);
1068
1069 if (!crtc || !crtc->state->active) {
1070 err = -EBUSY;
1071 goto unlock;
1072 }
1073
1074 value = tegra_sor_readl(sor, SOR_STATE1);
1075 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1076 tegra_sor_writel(sor, value, SOR_STATE1);
1077
1078 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1079 value |= SOR_CRC_CNTRL_ENABLE;
1080 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1081
1082 value = tegra_sor_readl(sor, SOR_TEST);
1083 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1084 tegra_sor_writel(sor, value, SOR_TEST);
1085
1086 err = tegra_sor_crc_wait(sor, 100);
1087 if (err < 0)
1088 goto unlock;
1089
1090 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1091 value = tegra_sor_readl(sor, SOR_CRCB);
1092
1093 seq_printf(s, "%08x\n", value);
1094
1095 unlock:
1096 drm_modeset_unlock_all(drm);
1097 return err;
1098 }
1099
1100 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1101 {
1102 struct drm_info_node *node = s->private;
1103 struct tegra_sor *sor = node->info_ent->data;
1104 struct drm_crtc *crtc = sor->output.encoder.crtc;
1105 struct drm_device *drm = node->minor->dev;
1106 int err = 0;
1107
1108 drm_modeset_lock_all(drm);
1109
1110 if (!crtc || !crtc->state->active) {
1111 err = -EBUSY;
1112 goto unlock;
1113 }
1114
1115 #define DUMP_REG(name) \
1116 seq_printf(s, "%-38s %#05x %08x\n", #name, name, \
1117 tegra_sor_readl(sor, name))
1118
1119 DUMP_REG(SOR_CTXSW);
1120 DUMP_REG(SOR_SUPER_STATE0);
1121 DUMP_REG(SOR_SUPER_STATE1);
1122 DUMP_REG(SOR_STATE0);
1123 DUMP_REG(SOR_STATE1);
1124 DUMP_REG(SOR_HEAD_STATE0(0));
1125 DUMP_REG(SOR_HEAD_STATE0(1));
1126 DUMP_REG(SOR_HEAD_STATE1(0));
1127 DUMP_REG(SOR_HEAD_STATE1(1));
1128 DUMP_REG(SOR_HEAD_STATE2(0));
1129 DUMP_REG(SOR_HEAD_STATE2(1));
1130 DUMP_REG(SOR_HEAD_STATE3(0));
1131 DUMP_REG(SOR_HEAD_STATE3(1));
1132 DUMP_REG(SOR_HEAD_STATE4(0));
1133 DUMP_REG(SOR_HEAD_STATE4(1));
1134 DUMP_REG(SOR_HEAD_STATE5(0));
1135 DUMP_REG(SOR_HEAD_STATE5(1));
1136 DUMP_REG(SOR_CRC_CNTRL);
1137 DUMP_REG(SOR_DP_DEBUG_MVID);
1138 DUMP_REG(SOR_CLK_CNTRL);
1139 DUMP_REG(SOR_CAP);
1140 DUMP_REG(SOR_PWR);
1141 DUMP_REG(SOR_TEST);
1142 DUMP_REG(SOR_PLL0);
1143 DUMP_REG(SOR_PLL1);
1144 DUMP_REG(SOR_PLL2);
1145 DUMP_REG(SOR_PLL3);
1146 DUMP_REG(SOR_CSTM);
1147 DUMP_REG(SOR_LVDS);
1148 DUMP_REG(SOR_CRCA);
1149 DUMP_REG(SOR_CRCB);
1150 DUMP_REG(SOR_BLANK);
1151 DUMP_REG(SOR_SEQ_CTL);
1152 DUMP_REG(SOR_LANE_SEQ_CTL);
1153 DUMP_REG(SOR_SEQ_INST(0));
1154 DUMP_REG(SOR_SEQ_INST(1));
1155 DUMP_REG(SOR_SEQ_INST(2));
1156 DUMP_REG(SOR_SEQ_INST(3));
1157 DUMP_REG(SOR_SEQ_INST(4));
1158 DUMP_REG(SOR_SEQ_INST(5));
1159 DUMP_REG(SOR_SEQ_INST(6));
1160 DUMP_REG(SOR_SEQ_INST(7));
1161 DUMP_REG(SOR_SEQ_INST(8));
1162 DUMP_REG(SOR_SEQ_INST(9));
1163 DUMP_REG(SOR_SEQ_INST(10));
1164 DUMP_REG(SOR_SEQ_INST(11));
1165 DUMP_REG(SOR_SEQ_INST(12));
1166 DUMP_REG(SOR_SEQ_INST(13));
1167 DUMP_REG(SOR_SEQ_INST(14));
1168 DUMP_REG(SOR_SEQ_INST(15));
1169 DUMP_REG(SOR_PWM_DIV);
1170 DUMP_REG(SOR_PWM_CTL);
1171 DUMP_REG(SOR_VCRC_A0);
1172 DUMP_REG(SOR_VCRC_A1);
1173 DUMP_REG(SOR_VCRC_B0);
1174 DUMP_REG(SOR_VCRC_B1);
1175 DUMP_REG(SOR_CCRC_A0);
1176 DUMP_REG(SOR_CCRC_A1);
1177 DUMP_REG(SOR_CCRC_B0);
1178 DUMP_REG(SOR_CCRC_B1);
1179 DUMP_REG(SOR_EDATA_A0);
1180 DUMP_REG(SOR_EDATA_A1);
1181 DUMP_REG(SOR_EDATA_B0);
1182 DUMP_REG(SOR_EDATA_B1);
1183 DUMP_REG(SOR_COUNT_A0);
1184 DUMP_REG(SOR_COUNT_A1);
1185 DUMP_REG(SOR_COUNT_B0);
1186 DUMP_REG(SOR_COUNT_B1);
1187 DUMP_REG(SOR_DEBUG_A0);
1188 DUMP_REG(SOR_DEBUG_A1);
1189 DUMP_REG(SOR_DEBUG_B0);
1190 DUMP_REG(SOR_DEBUG_B1);
1191 DUMP_REG(SOR_TRIG);
1192 DUMP_REG(SOR_MSCHECK);
1193 DUMP_REG(SOR_XBAR_CTRL);
1194 DUMP_REG(SOR_XBAR_POL);
1195 DUMP_REG(SOR_DP_LINKCTL0);
1196 DUMP_REG(SOR_DP_LINKCTL1);
1197 DUMP_REG(SOR_LANE_DRIVE_CURRENT0);
1198 DUMP_REG(SOR_LANE_DRIVE_CURRENT1);
1199 DUMP_REG(SOR_LANE4_DRIVE_CURRENT0);
1200 DUMP_REG(SOR_LANE4_DRIVE_CURRENT1);
1201 DUMP_REG(SOR_LANE_PREEMPHASIS0);
1202 DUMP_REG(SOR_LANE_PREEMPHASIS1);
1203 DUMP_REG(SOR_LANE4_PREEMPHASIS0);
1204 DUMP_REG(SOR_LANE4_PREEMPHASIS1);
1205 DUMP_REG(SOR_LANE_POSTCURSOR0);
1206 DUMP_REG(SOR_LANE_POSTCURSOR1);
1207 DUMP_REG(SOR_DP_CONFIG0);
1208 DUMP_REG(SOR_DP_CONFIG1);
1209 DUMP_REG(SOR_DP_MN0);
1210 DUMP_REG(SOR_DP_MN1);
1211 DUMP_REG(SOR_DP_PADCTL0);
1212 DUMP_REG(SOR_DP_PADCTL1);
1213 DUMP_REG(SOR_DP_DEBUG0);
1214 DUMP_REG(SOR_DP_DEBUG1);
1215 DUMP_REG(SOR_DP_SPARE0);
1216 DUMP_REG(SOR_DP_SPARE1);
1217 DUMP_REG(SOR_DP_AUDIO_CTRL);
1218 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);
1219 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);
1220 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);
1221 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0);
1222 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1);
1223 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2);
1224 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3);
1225 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4);
1226 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5);
1227 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6);
1228 DUMP_REG(SOR_DP_TPG);
1229 DUMP_REG(SOR_DP_TPG_CONFIG);
1230 DUMP_REG(SOR_DP_LQ_CSTM0);
1231 DUMP_REG(SOR_DP_LQ_CSTM1);
1232 DUMP_REG(SOR_DP_LQ_CSTM2);
1233
1234 #undef DUMP_REG
1235
1236 unlock:
1237 drm_modeset_unlock_all(drm);
1238 return err;
1239 }
1240
1241 static const struct drm_info_list debugfs_files[] = {
1242 { "crc", tegra_sor_show_crc, 0, NULL },
1243 { "regs", tegra_sor_show_regs, 0, NULL },
1244 };
1245
1246 static int tegra_sor_debugfs_init(struct tegra_sor *sor,
1247 struct drm_minor *minor)
1248 {
1249 const char *name = sor->soc->supports_dp ? "sor1" : "sor";
1250 unsigned int i;
1251 int err;
1252
1253 sor->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1254 if (!sor->debugfs)
1255 return -ENOMEM;
1256
1257 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1258 GFP_KERNEL);
1259 if (!sor->debugfs_files) {
1260 err = -ENOMEM;
1261 goto remove;
1262 }
1263
1264 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1265 sor->debugfs_files[i].data = sor;
1266
1267 err = drm_debugfs_create_files(sor->debugfs_files,
1268 ARRAY_SIZE(debugfs_files),
1269 sor->debugfs, minor);
1270 if (err < 0)
1271 goto free;
1272
1273 sor->minor = minor;
1274
1275 return 0;
1276
1277 free:
1278 kfree(sor->debugfs_files);
1279 sor->debugfs_files = NULL;
1280 remove:
1281 debugfs_remove_recursive(sor->debugfs);
1282 sor->debugfs = NULL;
1283 return err;
1284 }
1285
1286 static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
1287 {
1288 drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files),
1289 sor->minor);
1290 sor->minor = NULL;
1291
1292 kfree(sor->debugfs_files);
1293 sor->debugfs_files = NULL;
1294
1295 debugfs_remove_recursive(sor->debugfs);
1296 sor->debugfs = NULL;
1297 }
1298
1299 static void tegra_sor_connector_reset(struct drm_connector *connector)
1300 {
1301 struct tegra_sor_state *state;
1302
1303 state = kzalloc(sizeof(*state), GFP_KERNEL);
1304 if (!state)
1305 return;
1306
1307 if (connector->state) {
1308 __drm_atomic_helper_connector_destroy_state(connector->state);
1309 kfree(connector->state);
1310 }
1311
1312 __drm_atomic_helper_connector_reset(connector, &state->base);
1313 }
1314
1315 static enum drm_connector_status
1316 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1317 {
1318 struct tegra_output *output = connector_to_output(connector);
1319 struct tegra_sor *sor = to_sor(output);
1320
1321 if (sor->aux)
1322 return drm_dp_aux_detect(sor->aux);
1323
1324 return tegra_output_connector_detect(connector, force);
1325 }
1326
1327 static struct drm_connector_state *
1328 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1329 {
1330 struct tegra_sor_state *state = to_sor_state(connector->state);
1331 struct tegra_sor_state *copy;
1332
1333 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1334 if (!copy)
1335 return NULL;
1336
1337 __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1338
1339 return &copy->base;
1340 }
1341
1342 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1343 .dpms = drm_atomic_helper_connector_dpms,
1344 .reset = tegra_sor_connector_reset,
1345 .detect = tegra_sor_connector_detect,
1346 .fill_modes = drm_helper_probe_single_connector_modes,
1347 .destroy = tegra_output_connector_destroy,
1348 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1349 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1350 };
1351
1352 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1353 {
1354 struct tegra_output *output = connector_to_output(connector);
1355 struct tegra_sor *sor = to_sor(output);
1356 int err;
1357
1358 if (sor->aux)
1359 drm_dp_aux_enable(sor->aux);
1360
1361 err = tegra_output_connector_get_modes(connector);
1362
1363 if (sor->aux)
1364 drm_dp_aux_disable(sor->aux);
1365
1366 return err;
1367 }
1368
1369 static enum drm_mode_status
1370 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1371 struct drm_display_mode *mode)
1372 {
1373 /* HDMI 2.0 modes are not yet supported */
1374 if (mode->clock > 340000)
1375 return MODE_NOCLOCK;
1376
1377 return MODE_OK;
1378 }
1379
1380 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1381 .get_modes = tegra_sor_connector_get_modes,
1382 .mode_valid = tegra_sor_connector_mode_valid,
1383 };
1384
1385 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1386 .destroy = tegra_output_encoder_destroy,
1387 };
1388
1389 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1390 {
1391 struct tegra_output *output = encoder_to_output(encoder);
1392 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1393 struct tegra_sor *sor = to_sor(output);
1394 u32 value;
1395 int err;
1396
1397 if (output->panel)
1398 drm_panel_disable(output->panel);
1399
1400 err = tegra_sor_detach(sor);
1401 if (err < 0)
1402 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1403
1404 tegra_sor_writel(sor, 0, SOR_STATE1);
1405 tegra_sor_update(sor);
1406
1407 /*
1408 * The following accesses registers of the display controller, so make
1409 * sure it's only executed when the output is attached to one.
1410 */
1411 if (dc) {
1412 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1413 value &= ~SOR_ENABLE;
1414 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1415
1416 tegra_dc_commit(dc);
1417 }
1418
1419 err = tegra_sor_power_down(sor);
1420 if (err < 0)
1421 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1422
1423 if (sor->aux) {
1424 err = drm_dp_aux_disable(sor->aux);
1425 if (err < 0)
1426 dev_err(sor->dev, "failed to disable DP: %d\n", err);
1427 }
1428
1429 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1430 if (err < 0)
1431 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
1432
1433 if (output->panel)
1434 drm_panel_unprepare(output->panel);
1435
1436 pm_runtime_put(sor->dev);
1437 }
1438
1439 #if 0
1440 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1441 unsigned int *value)
1442 {
1443 unsigned int hfp, hsw, hbp, a = 0, b;
1444
1445 hfp = mode->hsync_start - mode->hdisplay;
1446 hsw = mode->hsync_end - mode->hsync_start;
1447 hbp = mode->htotal - mode->hsync_end;
1448
1449 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1450
1451 b = hfp - 1;
1452
1453 pr_info("a: %u, b: %u\n", a, b);
1454 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1455
1456 if (a + hsw + hbp <= 11) {
1457 a = 1 + 11 - hsw - hbp;
1458 pr_info("a: %u\n", a);
1459 }
1460
1461 if (a > b)
1462 return -EINVAL;
1463
1464 if (hsw < 1)
1465 return -EINVAL;
1466
1467 if (mode->hdisplay < 16)
1468 return -EINVAL;
1469
1470 if (value) {
1471 if (b > a && a % 2)
1472 *value = a + 1;
1473 else
1474 *value = a;
1475 }
1476
1477 return 0;
1478 }
1479 #endif
1480
1481 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1482 {
1483 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1484 struct tegra_output *output = encoder_to_output(encoder);
1485 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1486 struct tegra_sor *sor = to_sor(output);
1487 struct tegra_sor_config config;
1488 struct tegra_sor_state *state;
1489 struct drm_dp_link link;
1490 u8 rate, lanes;
1491 unsigned int i;
1492 int err = 0;
1493 u32 value;
1494
1495 state = to_sor_state(output->connector.state);
1496
1497 pm_runtime_get_sync(sor->dev);
1498
1499 if (output->panel)
1500 drm_panel_prepare(output->panel);
1501
1502 err = drm_dp_aux_enable(sor->aux);
1503 if (err < 0)
1504 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1505
1506 err = drm_dp_link_probe(sor->aux, &link);
1507 if (err < 0) {
1508 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1509 return;
1510 }
1511
1512 /* switch to safe parent clock */
1513 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1514 if (err < 0)
1515 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1516
1517 memset(&config, 0, sizeof(config));
1518 config.bits_per_pixel = state->bpc * 3;
1519
1520 err = tegra_sor_compute_config(sor, mode, &config, &link);
1521 if (err < 0)
1522 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1523
1524 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1525 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1526 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1527 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1528
1529 value = tegra_sor_readl(sor, SOR_PLL2);
1530 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1531 tegra_sor_writel(sor, value, SOR_PLL2);
1532 usleep_range(20, 100);
1533
1534 value = tegra_sor_readl(sor, SOR_PLL3);
1535 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1536 tegra_sor_writel(sor, value, SOR_PLL3);
1537
1538 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1539 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1540 tegra_sor_writel(sor, value, SOR_PLL0);
1541
1542 value = tegra_sor_readl(sor, SOR_PLL2);
1543 value |= SOR_PLL2_SEQ_PLLCAPPD;
1544 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1545 value |= SOR_PLL2_LVDS_ENABLE;
1546 tegra_sor_writel(sor, value, SOR_PLL2);
1547
1548 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1549 tegra_sor_writel(sor, value, SOR_PLL1);
1550
1551 while (true) {
1552 value = tegra_sor_readl(sor, SOR_PLL2);
1553 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1554 break;
1555
1556 usleep_range(250, 1000);
1557 }
1558
1559 value = tegra_sor_readl(sor, SOR_PLL2);
1560 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1561 value &= ~SOR_PLL2_PORT_POWERDOWN;
1562 tegra_sor_writel(sor, value, SOR_PLL2);
1563
1564 /*
1565 * power up
1566 */
1567
1568 /* set safe link bandwidth (1.62 Gbps) */
1569 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1570 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1571 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1572 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1573
1574 /* step 1 */
1575 value = tegra_sor_readl(sor, SOR_PLL2);
1576 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1577 SOR_PLL2_BANDGAP_POWERDOWN;
1578 tegra_sor_writel(sor, value, SOR_PLL2);
1579
1580 value = tegra_sor_readl(sor, SOR_PLL0);
1581 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1582 tegra_sor_writel(sor, value, SOR_PLL0);
1583
1584 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1585 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1586 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1587
1588 /* step 2 */
1589 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
1590 if (err < 0)
1591 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
1592
1593 usleep_range(5, 100);
1594
1595 /* step 3 */
1596 value = tegra_sor_readl(sor, SOR_PLL2);
1597 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1598 tegra_sor_writel(sor, value, SOR_PLL2);
1599
1600 usleep_range(20, 100);
1601
1602 /* step 4 */
1603 value = tegra_sor_readl(sor, SOR_PLL0);
1604 value &= ~SOR_PLL0_VCOPD;
1605 value &= ~SOR_PLL0_PWR;
1606 tegra_sor_writel(sor, value, SOR_PLL0);
1607
1608 value = tegra_sor_readl(sor, SOR_PLL2);
1609 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1610 tegra_sor_writel(sor, value, SOR_PLL2);
1611
1612 usleep_range(200, 1000);
1613
1614 /* step 5 */
1615 value = tegra_sor_readl(sor, SOR_PLL2);
1616 value &= ~SOR_PLL2_PORT_POWERDOWN;
1617 tegra_sor_writel(sor, value, SOR_PLL2);
1618
1619 /* XXX not in TRM */
1620 for (value = 0, i = 0; i < 5; i++)
1621 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
1622 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1623
1624 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1625 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1626
1627 /* switch to DP parent clock */
1628 err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1629 if (err < 0)
1630 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1631
1632 /* power DP lanes */
1633 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1634
1635 if (link.num_lanes <= 2)
1636 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1637 else
1638 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1639
1640 if (link.num_lanes <= 1)
1641 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1642 else
1643 value |= SOR_DP_PADCTL_PD_TXD_1;
1644
1645 if (link.num_lanes == 0)
1646 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1647 else
1648 value |= SOR_DP_PADCTL_PD_TXD_0;
1649
1650 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1651
1652 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1653 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1654 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1655 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1656
1657 /* start lane sequencer */
1658 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1659 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1660 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1661
1662 while (true) {
1663 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1664 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1665 break;
1666
1667 usleep_range(250, 1000);
1668 }
1669
1670 /* set link bandwidth */
1671 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1672 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1673 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1674 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1675
1676 tegra_sor_apply_config(sor, &config);
1677
1678 /* enable link */
1679 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1680 value |= SOR_DP_LINKCTL_ENABLE;
1681 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1682 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1683
1684 for (i = 0, value = 0; i < 4; i++) {
1685 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1686 SOR_DP_TPG_SCRAMBLER_GALIOS |
1687 SOR_DP_TPG_PATTERN_NONE;
1688 value = (value << 8) | lane;
1689 }
1690
1691 tegra_sor_writel(sor, value, SOR_DP_TPG);
1692
1693 /* enable pad calibration logic */
1694 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1695 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1696 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1697
1698 err = drm_dp_link_probe(sor->aux, &link);
1699 if (err < 0)
1700 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1701
1702 err = drm_dp_link_power_up(sor->aux, &link);
1703 if (err < 0)
1704 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1705
1706 err = drm_dp_link_configure(sor->aux, &link);
1707 if (err < 0)
1708 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1709
1710 rate = drm_dp_link_rate_to_bw_code(link.rate);
1711 lanes = link.num_lanes;
1712
1713 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1714 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1715 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1716 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1717
1718 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1719 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1720 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1721
1722 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1723 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1724
1725 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1726
1727 /* disable training pattern generator */
1728
1729 for (i = 0; i < link.num_lanes; i++) {
1730 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1731 SOR_DP_TPG_SCRAMBLER_GALIOS |
1732 SOR_DP_TPG_PATTERN_NONE;
1733 value = (value << 8) | lane;
1734 }
1735
1736 tegra_sor_writel(sor, value, SOR_DP_TPG);
1737
1738 err = tegra_sor_dp_train_fast(sor, &link);
1739 if (err < 0)
1740 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1741
1742 dev_dbg(sor->dev, "fast link training succeeded\n");
1743
1744 err = tegra_sor_power_up(sor, 250);
1745 if (err < 0)
1746 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1747
1748 /* CSTM (LVDS, link A/B, upper) */
1749 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1750 SOR_CSTM_UPPER;
1751 tegra_sor_writel(sor, value, SOR_CSTM);
1752
1753 /* use DP-A protocol */
1754 value = tegra_sor_readl(sor, SOR_STATE1);
1755 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1756 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1757 tegra_sor_writel(sor, value, SOR_STATE1);
1758
1759 tegra_sor_mode_set(sor, mode, state);
1760
1761 /* PWM setup */
1762 err = tegra_sor_setup_pwm(sor, 250);
1763 if (err < 0)
1764 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1765
1766 tegra_sor_update(sor);
1767
1768 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1769 value |= SOR_ENABLE;
1770 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1771
1772 tegra_dc_commit(dc);
1773
1774 err = tegra_sor_attach(sor);
1775 if (err < 0)
1776 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1777
1778 err = tegra_sor_wakeup(sor);
1779 if (err < 0)
1780 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1781
1782 if (output->panel)
1783 drm_panel_enable(output->panel);
1784 }
1785
1786 static int
1787 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1788 struct drm_crtc_state *crtc_state,
1789 struct drm_connector_state *conn_state)
1790 {
1791 struct tegra_output *output = encoder_to_output(encoder);
1792 struct tegra_sor_state *state = to_sor_state(conn_state);
1793 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1794 unsigned long pclk = crtc_state->mode.clock * 1000;
1795 struct tegra_sor *sor = to_sor(output);
1796 struct drm_display_info *info;
1797 int err;
1798
1799 info = &output->connector.display_info;
1800
1801 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1802 pclk, 0);
1803 if (err < 0) {
1804 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1805 return err;
1806 }
1807
1808 switch (info->bpc) {
1809 case 8:
1810 case 6:
1811 state->bpc = info->bpc;
1812 break;
1813
1814 default:
1815 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1816 state->bpc = 8;
1817 break;
1818 }
1819
1820 return 0;
1821 }
1822
1823 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
1824 .disable = tegra_sor_edp_disable,
1825 .enable = tegra_sor_edp_enable,
1826 .atomic_check = tegra_sor_encoder_atomic_check,
1827 };
1828
1829 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1830 {
1831 u32 value = 0;
1832 size_t i;
1833
1834 for (i = size; i > 0; i--)
1835 value = (value << 8) | ptr[i - 1];
1836
1837 return value;
1838 }
1839
1840 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1841 const void *data, size_t size)
1842 {
1843 const u8 *ptr = data;
1844 unsigned long offset;
1845 size_t i, j;
1846 u32 value;
1847
1848 switch (ptr[0]) {
1849 case HDMI_INFOFRAME_TYPE_AVI:
1850 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1851 break;
1852
1853 case HDMI_INFOFRAME_TYPE_AUDIO:
1854 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1855 break;
1856
1857 case HDMI_INFOFRAME_TYPE_VENDOR:
1858 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1859 break;
1860
1861 default:
1862 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1863 ptr[0]);
1864 return;
1865 }
1866
1867 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1868 INFOFRAME_HEADER_VERSION(ptr[1]) |
1869 INFOFRAME_HEADER_LEN(ptr[2]);
1870 tegra_sor_writel(sor, value, offset);
1871 offset++;
1872
1873 /*
1874 * Each subpack contains 7 bytes, divided into:
1875 * - subpack_low: bytes 0 - 3
1876 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1877 */
1878 for (i = 3, j = 0; i < size; i += 7, j += 8) {
1879 size_t rem = size - i, num = min_t(size_t, rem, 4);
1880
1881 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1882 tegra_sor_writel(sor, value, offset++);
1883
1884 num = min_t(size_t, rem - num, 3);
1885
1886 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1887 tegra_sor_writel(sor, value, offset++);
1888 }
1889 }
1890
1891 static int
1892 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1893 const struct drm_display_mode *mode)
1894 {
1895 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1896 struct hdmi_avi_infoframe frame;
1897 u32 value;
1898 int err;
1899
1900 /* disable AVI infoframe */
1901 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1902 value &= ~INFOFRAME_CTRL_SINGLE;
1903 value &= ~INFOFRAME_CTRL_OTHER;
1904 value &= ~INFOFRAME_CTRL_ENABLE;
1905 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1906
1907 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1908 if (err < 0) {
1909 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1910 return err;
1911 }
1912
1913 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1914 if (err < 0) {
1915 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1916 return err;
1917 }
1918
1919 tegra_sor_hdmi_write_infopack(sor, buffer, err);
1920
1921 /* enable AVI infoframe */
1922 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1923 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1924 value |= INFOFRAME_CTRL_ENABLE;
1925 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1926
1927 return 0;
1928 }
1929
1930 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
1931 {
1932 u32 value;
1933
1934 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1935 value &= ~INFOFRAME_CTRL_ENABLE;
1936 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1937 }
1938
1939 static struct tegra_sor_hdmi_settings *
1940 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
1941 {
1942 unsigned int i;
1943
1944 for (i = 0; i < sor->num_settings; i++)
1945 if (frequency <= sor->settings[i].frequency)
1946 return &sor->settings[i];
1947
1948 return NULL;
1949 }
1950
1951 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1952 {
1953 struct tegra_output *output = encoder_to_output(encoder);
1954 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1955 struct tegra_sor *sor = to_sor(output);
1956 u32 value;
1957 int err;
1958
1959 err = tegra_sor_detach(sor);
1960 if (err < 0)
1961 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1962
1963 tegra_sor_writel(sor, 0, SOR_STATE1);
1964 tegra_sor_update(sor);
1965
1966 /* disable display to SOR clock */
1967 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1968 value &= ~SOR1_TIMING_CYA;
1969 value &= ~SOR1_ENABLE;
1970 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1971
1972 tegra_dc_commit(dc);
1973
1974 err = tegra_sor_power_down(sor);
1975 if (err < 0)
1976 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1977
1978 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI);
1979 if (err < 0)
1980 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err);
1981
1982 pm_runtime_put(sor->dev);
1983 }
1984
1985 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
1986 {
1987 struct tegra_output *output = encoder_to_output(encoder);
1988 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
1989 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1990 struct tegra_sor_hdmi_settings *settings;
1991 struct tegra_sor *sor = to_sor(output);
1992 struct tegra_sor_state *state;
1993 struct drm_display_mode *mode;
1994 unsigned int div, i;
1995 u32 value;
1996 int err;
1997
1998 state = to_sor_state(output->connector.state);
1999 mode = &encoder->crtc->state->adjusted_mode;
2000
2001 pm_runtime_get_sync(sor->dev);
2002
2003 /* switch to safe parent clock */
2004 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2005 if (err < 0)
2006 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2007
2008 div = clk_get_rate(sor->clk) / 1000000 * 4;
2009
2010 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI);
2011 if (err < 0)
2012 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err);
2013
2014 usleep_range(20, 100);
2015
2016 value = tegra_sor_readl(sor, SOR_PLL2);
2017 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2018 tegra_sor_writel(sor, value, SOR_PLL2);
2019
2020 usleep_range(20, 100);
2021
2022 value = tegra_sor_readl(sor, SOR_PLL3);
2023 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2024 tegra_sor_writel(sor, value, SOR_PLL3);
2025
2026 value = tegra_sor_readl(sor, SOR_PLL0);
2027 value &= ~SOR_PLL0_VCOPD;
2028 value &= ~SOR_PLL0_PWR;
2029 tegra_sor_writel(sor, value, SOR_PLL0);
2030
2031 value = tegra_sor_readl(sor, SOR_PLL2);
2032 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2033 tegra_sor_writel(sor, value, SOR_PLL2);
2034
2035 usleep_range(200, 400);
2036
2037 value = tegra_sor_readl(sor, SOR_PLL2);
2038 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2039 value &= ~SOR_PLL2_PORT_POWERDOWN;
2040 tegra_sor_writel(sor, value, SOR_PLL2);
2041
2042 usleep_range(20, 100);
2043
2044 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2045 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2046 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2047 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2048
2049 while (true) {
2050 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2051 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2052 break;
2053
2054 usleep_range(250, 1000);
2055 }
2056
2057 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2058 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2059 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2060
2061 while (true) {
2062 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2063 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2064 break;
2065
2066 usleep_range(250, 1000);
2067 }
2068
2069 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2070 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2071 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2072
2073 if (mode->clock < 340000)
2074 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2075 else
2076 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2077
2078 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2079 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2080
2081 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2082 value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2083 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2084 value |= SOR_DP_SPARE_SEQ_ENABLE;
2085 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2086
2087 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2088 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2089 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2090
2091 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2092 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2093 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2094 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2095
2096 /* program the reference clock */
2097 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2098 tegra_sor_writel(sor, value, SOR_REFCLK);
2099
2100 /* XXX not in TRM */
2101 for (value = 0, i = 0; i < 5; i++)
2102 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2103 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2104
2105 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2106 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2107
2108 /* switch to parent clock */
2109 err = clk_set_parent(sor->clk_src, sor->clk_parent);
2110 if (err < 0)
2111 dev_err(sor->dev, "failed to set source clock: %d\n", err);
2112
2113 err = tegra_sor_set_parent_clock(sor, sor->clk_src);
2114 if (err < 0)
2115 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2116
2117 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2118
2119 /* XXX is this the proper check? */
2120 if (mode->clock < 75000)
2121 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2122
2123 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2124
2125 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2126
2127 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2128 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2129 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2130
2131 /* H_PULSE2 setup */
2132 pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) +
2133 (mode->htotal - mode->hsync_end) - 10;
2134
2135 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2136 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2137 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2138
2139 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2140 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2141
2142 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2143 value |= H_PULSE2_ENABLE;
2144 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2145
2146 /* infoframe setup */
2147 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2148 if (err < 0)
2149 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2150
2151 /* XXX HDMI audio support not implemented yet */
2152 tegra_sor_hdmi_disable_audio_infoframe(sor);
2153
2154 /* use single TMDS protocol */
2155 value = tegra_sor_readl(sor, SOR_STATE1);
2156 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2157 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2158 tegra_sor_writel(sor, value, SOR_STATE1);
2159
2160 /* power up pad calibration */
2161 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2162 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2163 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2164
2165 /* production settings */
2166 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2167 if (!settings) {
2168 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2169 mode->clock * 1000);
2170 return;
2171 }
2172
2173 value = tegra_sor_readl(sor, SOR_PLL0);
2174 value &= ~SOR_PLL0_ICHPMP_MASK;
2175 value &= ~SOR_PLL0_VCOCAP_MASK;
2176 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2177 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2178 tegra_sor_writel(sor, value, SOR_PLL0);
2179
2180 tegra_sor_dp_term_calibrate(sor);
2181
2182 value = tegra_sor_readl(sor, SOR_PLL1);
2183 value &= ~SOR_PLL1_LOADADJ_MASK;
2184 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2185 tegra_sor_writel(sor, value, SOR_PLL1);
2186
2187 value = tegra_sor_readl(sor, SOR_PLL3);
2188 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2189 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref);
2190 tegra_sor_writel(sor, value, SOR_PLL3);
2191
2192 value = settings->drive_current[0] << 24 |
2193 settings->drive_current[1] << 16 |
2194 settings->drive_current[2] << 8 |
2195 settings->drive_current[3] << 0;
2196 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2197
2198 value = settings->preemphasis[0] << 24 |
2199 settings->preemphasis[1] << 16 |
2200 settings->preemphasis[2] << 8 |
2201 settings->preemphasis[3] << 0;
2202 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2203
2204 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2205 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2206 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2207 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu);
2208 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2209
2210 /* power down pad calibration */
2211 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2212 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2213 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2214
2215 /* miscellaneous display controller settings */
2216 value = VSYNC_H_POSITION(1);
2217 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2218
2219 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2220 value &= ~DITHER_CONTROL_MASK;
2221 value &= ~BASE_COLOR_SIZE_MASK;
2222
2223 switch (state->bpc) {
2224 case 6:
2225 value |= BASE_COLOR_SIZE_666;
2226 break;
2227
2228 case 8:
2229 value |= BASE_COLOR_SIZE_888;
2230 break;
2231
2232 default:
2233 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2234 value |= BASE_COLOR_SIZE_888;
2235 break;
2236 }
2237
2238 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2239
2240 err = tegra_sor_power_up(sor, 250);
2241 if (err < 0)
2242 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2243
2244 /* configure dynamic range of output */
2245 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2246 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2247 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2248 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2249
2250 /* configure colorspace */
2251 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2252 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2253 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2254 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2255
2256 tegra_sor_mode_set(sor, mode, state);
2257
2258 tegra_sor_update(sor);
2259
2260 err = tegra_sor_attach(sor);
2261 if (err < 0)
2262 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2263
2264 /* enable display to SOR clock and generate HDMI preamble */
2265 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2266 value |= SOR1_ENABLE | SOR1_TIMING_CYA;
2267 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2268
2269 tegra_dc_commit(dc);
2270
2271 err = tegra_sor_wakeup(sor);
2272 if (err < 0)
2273 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2274 }
2275
2276 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2277 .disable = tegra_sor_hdmi_disable,
2278 .enable = tegra_sor_hdmi_enable,
2279 .atomic_check = tegra_sor_encoder_atomic_check,
2280 };
2281
2282 static int tegra_sor_init(struct host1x_client *client)
2283 {
2284 struct drm_device *drm = dev_get_drvdata(client->parent);
2285 const struct drm_encoder_helper_funcs *helpers = NULL;
2286 struct tegra_sor *sor = host1x_client_to_sor(client);
2287 int connector = DRM_MODE_CONNECTOR_Unknown;
2288 int encoder = DRM_MODE_ENCODER_NONE;
2289 int err;
2290
2291 if (!sor->aux) {
2292 if (sor->soc->supports_hdmi) {
2293 connector = DRM_MODE_CONNECTOR_HDMIA;
2294 encoder = DRM_MODE_ENCODER_TMDS;
2295 helpers = &tegra_sor_hdmi_helpers;
2296 } else if (sor->soc->supports_lvds) {
2297 connector = DRM_MODE_CONNECTOR_LVDS;
2298 encoder = DRM_MODE_ENCODER_LVDS;
2299 }
2300 } else {
2301 if (sor->soc->supports_edp) {
2302 connector = DRM_MODE_CONNECTOR_eDP;
2303 encoder = DRM_MODE_ENCODER_TMDS;
2304 helpers = &tegra_sor_edp_helpers;
2305 } else if (sor->soc->supports_dp) {
2306 connector = DRM_MODE_CONNECTOR_DisplayPort;
2307 encoder = DRM_MODE_ENCODER_TMDS;
2308 }
2309 }
2310
2311 sor->output.dev = sor->dev;
2312
2313 drm_connector_init(drm, &sor->output.connector,
2314 &tegra_sor_connector_funcs,
2315 connector);
2316 drm_connector_helper_add(&sor->output.connector,
2317 &tegra_sor_connector_helper_funcs);
2318 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2319
2320 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2321 encoder, NULL);
2322 drm_encoder_helper_add(&sor->output.encoder, helpers);
2323
2324 drm_mode_connector_attach_encoder(&sor->output.connector,
2325 &sor->output.encoder);
2326 drm_connector_register(&sor->output.connector);
2327
2328 err = tegra_output_init(drm, &sor->output);
2329 if (err < 0) {
2330 dev_err(client->dev, "failed to initialize output: %d\n", err);
2331 return err;
2332 }
2333
2334 sor->output.encoder.possible_crtcs = 0x3;
2335
2336 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2337 err = tegra_sor_debugfs_init(sor, drm->primary);
2338 if (err < 0)
2339 dev_err(sor->dev, "debugfs setup failed: %d\n", err);
2340 }
2341
2342 if (sor->aux) {
2343 err = drm_dp_aux_attach(sor->aux, &sor->output);
2344 if (err < 0) {
2345 dev_err(sor->dev, "failed to attach DP: %d\n", err);
2346 return err;
2347 }
2348 }
2349
2350 /*
2351 * XXX: Remove this reset once proper hand-over from firmware to
2352 * kernel is possible.
2353 */
2354 if (sor->rst) {
2355 err = reset_control_assert(sor->rst);
2356 if (err < 0) {
2357 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2358 err);
2359 return err;
2360 }
2361 }
2362
2363 err = clk_prepare_enable(sor->clk);
2364 if (err < 0) {
2365 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2366 return err;
2367 }
2368
2369 usleep_range(1000, 3000);
2370
2371 if (sor->rst) {
2372 err = reset_control_deassert(sor->rst);
2373 if (err < 0) {
2374 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2375 err);
2376 return err;
2377 }
2378 }
2379
2380 err = clk_prepare_enable(sor->clk_safe);
2381 if (err < 0)
2382 return err;
2383
2384 err = clk_prepare_enable(sor->clk_dp);
2385 if (err < 0)
2386 return err;
2387
2388 return 0;
2389 }
2390
2391 static int tegra_sor_exit(struct host1x_client *client)
2392 {
2393 struct tegra_sor *sor = host1x_client_to_sor(client);
2394 int err;
2395
2396 tegra_output_exit(&sor->output);
2397
2398 if (sor->aux) {
2399 err = drm_dp_aux_detach(sor->aux);
2400 if (err < 0) {
2401 dev_err(sor->dev, "failed to detach DP: %d\n", err);
2402 return err;
2403 }
2404 }
2405
2406 clk_disable_unprepare(sor->clk_safe);
2407 clk_disable_unprepare(sor->clk_dp);
2408 clk_disable_unprepare(sor->clk);
2409
2410 if (IS_ENABLED(CONFIG_DEBUG_FS))
2411 tegra_sor_debugfs_exit(sor);
2412
2413 return 0;
2414 }
2415
2416 static const struct host1x_client_ops sor_client_ops = {
2417 .init = tegra_sor_init,
2418 .exit = tegra_sor_exit,
2419 };
2420
2421 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2422 .name = "eDP",
2423 };
2424
2425 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2426 {
2427 int err;
2428
2429 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2430 if (IS_ERR(sor->avdd_io_supply)) {
2431 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2432 PTR_ERR(sor->avdd_io_supply));
2433 return PTR_ERR(sor->avdd_io_supply);
2434 }
2435
2436 err = regulator_enable(sor->avdd_io_supply);
2437 if (err < 0) {
2438 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2439 err);
2440 return err;
2441 }
2442
2443 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2444 if (IS_ERR(sor->vdd_pll_supply)) {
2445 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2446 PTR_ERR(sor->vdd_pll_supply));
2447 return PTR_ERR(sor->vdd_pll_supply);
2448 }
2449
2450 err = regulator_enable(sor->vdd_pll_supply);
2451 if (err < 0) {
2452 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2453 err);
2454 return err;
2455 }
2456
2457 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2458 if (IS_ERR(sor->hdmi_supply)) {
2459 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2460 PTR_ERR(sor->hdmi_supply));
2461 return PTR_ERR(sor->hdmi_supply);
2462 }
2463
2464 err = regulator_enable(sor->hdmi_supply);
2465 if (err < 0) {
2466 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2467 return err;
2468 }
2469
2470 return 0;
2471 }
2472
2473 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
2474 {
2475 regulator_disable(sor->hdmi_supply);
2476 regulator_disable(sor->vdd_pll_supply);
2477 regulator_disable(sor->avdd_io_supply);
2478
2479 return 0;
2480 }
2481
2482 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
2483 .name = "HDMI",
2484 .probe = tegra_sor_hdmi_probe,
2485 .remove = tegra_sor_hdmi_remove,
2486 };
2487
2488 static const u8 tegra124_sor_xbar_cfg[5] = {
2489 0, 1, 2, 3, 4
2490 };
2491
2492 static const struct tegra_sor_soc tegra124_sor = {
2493 .supports_edp = true,
2494 .supports_lvds = true,
2495 .supports_hdmi = false,
2496 .supports_dp = false,
2497 .xbar_cfg = tegra124_sor_xbar_cfg,
2498 };
2499
2500 static const struct tegra_sor_soc tegra210_sor = {
2501 .supports_edp = true,
2502 .supports_lvds = false,
2503 .supports_hdmi = false,
2504 .supports_dp = false,
2505 .xbar_cfg = tegra124_sor_xbar_cfg,
2506 };
2507
2508 static const u8 tegra210_sor_xbar_cfg[5] = {
2509 2, 1, 0, 3, 4
2510 };
2511
2512 static const struct tegra_sor_soc tegra210_sor1 = {
2513 .supports_edp = false,
2514 .supports_lvds = false,
2515 .supports_hdmi = true,
2516 .supports_dp = true,
2517
2518 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
2519 .settings = tegra210_sor_hdmi_defaults,
2520
2521 .xbar_cfg = tegra210_sor_xbar_cfg,
2522 };
2523
2524 static const struct of_device_id tegra_sor_of_match[] = {
2525 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
2526 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
2527 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
2528 { },
2529 };
2530 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
2531
2532 static int tegra_sor_probe(struct platform_device *pdev)
2533 {
2534 const struct of_device_id *match;
2535 struct device_node *np;
2536 struct tegra_sor *sor;
2537 struct resource *regs;
2538 int err;
2539
2540 match = of_match_device(tegra_sor_of_match, &pdev->dev);
2541
2542 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
2543 if (!sor)
2544 return -ENOMEM;
2545
2546 sor->output.dev = sor->dev = &pdev->dev;
2547 sor->soc = match->data;
2548
2549 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
2550 sor->soc->num_settings *
2551 sizeof(*sor->settings),
2552 GFP_KERNEL);
2553 if (!sor->settings)
2554 return -ENOMEM;
2555
2556 sor->num_settings = sor->soc->num_settings;
2557
2558 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
2559 if (np) {
2560 sor->aux = drm_dp_aux_find_by_of_node(np);
2561 of_node_put(np);
2562
2563 if (!sor->aux)
2564 return -EPROBE_DEFER;
2565 }
2566
2567 if (!sor->aux) {
2568 if (sor->soc->supports_hdmi) {
2569 sor->ops = &tegra_sor_hdmi_ops;
2570 } else if (sor->soc->supports_lvds) {
2571 dev_err(&pdev->dev, "LVDS not supported yet\n");
2572 return -ENODEV;
2573 } else {
2574 dev_err(&pdev->dev, "unknown (non-DP) support\n");
2575 return -ENODEV;
2576 }
2577 } else {
2578 if (sor->soc->supports_edp) {
2579 sor->ops = &tegra_sor_edp_ops;
2580 } else if (sor->soc->supports_dp) {
2581 dev_err(&pdev->dev, "DisplayPort not supported yet\n");
2582 return -ENODEV;
2583 } else {
2584 dev_err(&pdev->dev, "unknown (DP) support\n");
2585 return -ENODEV;
2586 }
2587 }
2588
2589 err = tegra_output_probe(&sor->output);
2590 if (err < 0) {
2591 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
2592 return err;
2593 }
2594
2595 if (sor->ops && sor->ops->probe) {
2596 err = sor->ops->probe(sor);
2597 if (err < 0) {
2598 dev_err(&pdev->dev, "failed to probe %s: %d\n",
2599 sor->ops->name, err);
2600 goto output;
2601 }
2602 }
2603
2604 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2605 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
2606 if (IS_ERR(sor->regs)) {
2607 err = PTR_ERR(sor->regs);
2608 goto remove;
2609 }
2610
2611 if (!pdev->dev.pm_domain) {
2612 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
2613 if (IS_ERR(sor->rst)) {
2614 err = PTR_ERR(sor->rst);
2615 dev_err(&pdev->dev, "failed to get reset control: %d\n",
2616 err);
2617 goto remove;
2618 }
2619 }
2620
2621 sor->clk = devm_clk_get(&pdev->dev, NULL);
2622 if (IS_ERR(sor->clk)) {
2623 err = PTR_ERR(sor->clk);
2624 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
2625 goto remove;
2626 }
2627
2628 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
2629 sor->clk_src = devm_clk_get(&pdev->dev, "source");
2630 if (IS_ERR(sor->clk_src)) {
2631 err = PTR_ERR(sor->clk_src);
2632 dev_err(sor->dev, "failed to get source clock: %d\n",
2633 err);
2634 goto remove;
2635 }
2636 }
2637
2638 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
2639 if (IS_ERR(sor->clk_parent)) {
2640 err = PTR_ERR(sor->clk_parent);
2641 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
2642 goto remove;
2643 }
2644
2645 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
2646 if (IS_ERR(sor->clk_safe)) {
2647 err = PTR_ERR(sor->clk_safe);
2648 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
2649 goto remove;
2650 }
2651
2652 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
2653 if (IS_ERR(sor->clk_dp)) {
2654 err = PTR_ERR(sor->clk_dp);
2655 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
2656 goto remove;
2657 }
2658
2659 platform_set_drvdata(pdev, sor);
2660 pm_runtime_enable(&pdev->dev);
2661
2662 pm_runtime_get_sync(&pdev->dev);
2663 sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick");
2664 pm_runtime_put(&pdev->dev);
2665
2666 if (IS_ERR(sor->clk_brick)) {
2667 err = PTR_ERR(sor->clk_brick);
2668 dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err);
2669 goto remove;
2670 }
2671
2672 INIT_LIST_HEAD(&sor->client.list);
2673 sor->client.ops = &sor_client_ops;
2674 sor->client.dev = &pdev->dev;
2675
2676 err = host1x_client_register(&sor->client);
2677 if (err < 0) {
2678 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2679 err);
2680 goto remove;
2681 }
2682
2683 return 0;
2684
2685 remove:
2686 if (sor->ops && sor->ops->remove)
2687 sor->ops->remove(sor);
2688 output:
2689 tegra_output_remove(&sor->output);
2690 return err;
2691 }
2692
2693 static int tegra_sor_remove(struct platform_device *pdev)
2694 {
2695 struct tegra_sor *sor = platform_get_drvdata(pdev);
2696 int err;
2697
2698 pm_runtime_disable(&pdev->dev);
2699
2700 err = host1x_client_unregister(&sor->client);
2701 if (err < 0) {
2702 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2703 err);
2704 return err;
2705 }
2706
2707 if (sor->ops && sor->ops->remove) {
2708 err = sor->ops->remove(sor);
2709 if (err < 0)
2710 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
2711 }
2712
2713 tegra_output_remove(&sor->output);
2714
2715 return 0;
2716 }
2717
2718 #ifdef CONFIG_PM
2719 static int tegra_sor_suspend(struct device *dev)
2720 {
2721 struct tegra_sor *sor = dev_get_drvdata(dev);
2722 int err;
2723
2724 if (sor->rst) {
2725 err = reset_control_assert(sor->rst);
2726 if (err < 0) {
2727 dev_err(dev, "failed to assert reset: %d\n", err);
2728 return err;
2729 }
2730 }
2731
2732 usleep_range(1000, 2000);
2733
2734 clk_disable_unprepare(sor->clk);
2735
2736 return 0;
2737 }
2738
2739 static int tegra_sor_resume(struct device *dev)
2740 {
2741 struct tegra_sor *sor = dev_get_drvdata(dev);
2742 int err;
2743
2744 err = clk_prepare_enable(sor->clk);
2745 if (err < 0) {
2746 dev_err(dev, "failed to enable clock: %d\n", err);
2747 return err;
2748 }
2749
2750 usleep_range(1000, 2000);
2751
2752 if (sor->rst) {
2753 err = reset_control_deassert(sor->rst);
2754 if (err < 0) {
2755 dev_err(dev, "failed to deassert reset: %d\n", err);
2756 clk_disable_unprepare(sor->clk);
2757 return err;
2758 }
2759 }
2760
2761 return 0;
2762 }
2763 #endif
2764
2765 static const struct dev_pm_ops tegra_sor_pm_ops = {
2766 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
2767 };
2768
2769 struct platform_driver tegra_sor_driver = {
2770 .driver = {
2771 .name = "tegra-sor",
2772 .of_match_table = tegra_sor_of_match,
2773 .pm = &tegra_sor_pm_ops,
2774 },
2775 .probe = tegra_sor_probe,
2776 .remove = tegra_sor_remove,
2777 };
Linux with added FPC-III support