drivers/gpu/drm/vc4/vc4_drv.h

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include "drmP.h"
  10 #include "drm_gem_cma_helper.h"
  11
  12 #include <drm/drm_encoder.h>
  13
  14 struct vc4_dev {
  15         struct drm_device *dev;
  16
  17         struct vc4_hdmi *hdmi;
  18         struct vc4_hvs *hvs;
  19         struct vc4_v3d *v3d;
  20         struct vc4_dpi *dpi;
  21         struct vc4_vec *vec;
  22
  23         struct drm_fbdev_cma *fbdev;
  24
  25         struct vc4_hang_state *hang_state;
  26
  27         /* The kernel-space BO cache.  Tracks buffers that have been
  28          * unreferenced by all other users (refcounts of 0!) but not
  29          * yet freed, so we can do cheap allocations.
  30          */
  31         struct vc4_bo_cache {
  32                 /* Array of list heads for entries in the BO cache,
  33                  * based on number of pages, so we can do O(1) lookups
  34                  * in the cache when allocating.
  35                  */
  36                 struct list_head *size_list;
  37                 uint32_t size_list_size;
  38
  39                 /* List of all BOs in the cache, ordered by age, so we
  40                  * can do O(1) lookups when trying to free old
  41                  * buffers.
  42                  */
  43                 struct list_head time_list;
  44                 struct work_struct time_work;
  45                 struct timer_list time_timer;
  46         } bo_cache;
  47
  48         struct vc4_bo_stats {
  49                 u32 num_allocated;
  50                 u32 size_allocated;
  51                 u32 num_cached;
  52                 u32 size_cached;
  53         } bo_stats;
  54
  55         /* Protects bo_cache and the BO stats. */
  56         struct mutex bo_lock;
  57
  58         /* Sequence number for the last job queued in bin_job_list.
  59          * Starts at 0 (no jobs emitted).
  60          */
  61         uint64_t emit_seqno;
  62
  63         /* Sequence number for the last completed job on the GPU.
  64          * Starts at 0 (no jobs completed).
  65          */
  66         uint64_t finished_seqno;
  67
  68         /* List of all struct vc4_exec_info for jobs to be executed in
  69          * the binner.  The first job in the list is the one currently
  70          * programmed into ct0ca for execution.
  71          */
  72         struct list_head bin_job_list;
  73
  74         /* List of all struct vc4_exec_info for jobs that have
  75          * completed binning and are ready for rendering.  The first
  76          * job in the list is the one currently programmed into ct1ca
  77          * for execution.
  78          */
  79         struct list_head render_job_list;
  80
  81         /* List of the finished vc4_exec_infos waiting to be freed by
  82          * job_done_work.
  83          */
  84         struct list_head job_done_list;
  85         /* Spinlock used to synchronize the job_list and seqno
  86          * accesses between the IRQ handler and GEM ioctls.
  87          */
  88         spinlock_t job_lock;
  89         wait_queue_head_t job_wait_queue;
  90         struct work_struct job_done_work;
  91
  92         /* List of struct vc4_seqno_cb for callbacks to be made from a
  93          * workqueue when the given seqno is passed.
  94          */
  95         struct list_head seqno_cb_list;
  96
  97         /* The binner overflow memory that's currently set up in
  98          * BPOA/BPOS registers.  When overflow occurs and a new one is
  99          * allocated, the previous one will be moved to
 100          * vc4->current_exec's free list.
 101          */
 102         struct vc4_bo *overflow_mem;
 103         struct work_struct overflow_mem_work;
 104
 105         int power_refcount;
 106
 107         /* Mutex controlling the power refcount. */
 108         struct mutex power_lock;
 109
 110         struct {
 111                 struct timer_list timer;
 112                 struct work_struct reset_work;
 113         } hangcheck;
 114
 115         struct semaphore async_modeset;
 116 };
 117
 118 static inline struct vc4_dev *
 119 to_vc4_dev(struct drm_device *dev)
 120 {
 121         return (struct vc4_dev *)dev->dev_private;
 122 }
 123
 124 struct vc4_bo {
 125         struct drm_gem_cma_object base;
 126
 127         /* seqno of the last job to render using this BO. */
 128         uint64_t seqno;
 129
 130         /* seqno of the last job to use the RCL to write to this BO.
 131          *
 132          * Note that this doesn't include binner overflow memory
 133          * writes.
 134          */
 135         uint64_t write_seqno;
 136
 137         /* List entry for the BO's position in either
 138          * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
 139          */
 140         struct list_head unref_head;
 141
 142         /* Time in jiffies when the BO was put in vc4->bo_cache. */
 143         unsigned long free_time;
 144
 145         /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
 146         struct list_head size_head;
 147
 148         /* Struct for shader validation state, if created by
 149          * DRM_IOCTL_VC4_CREATE_SHADER_BO.
 150          */
 151         struct vc4_validated_shader_info *validated_shader;
 152 };
 153
 154 static inline struct vc4_bo *
 155 to_vc4_bo(struct drm_gem_object *bo)
 156 {
 157         return (struct vc4_bo *)bo;
 158 }
 159
 160 struct vc4_seqno_cb {
 161         struct work_struct work;
 162         uint64_t seqno;
 163         void (*func)(struct vc4_seqno_cb *cb);
 164 };
 165
 166 struct vc4_v3d {
 167         struct vc4_dev *vc4;
 168         struct platform_device *pdev;
 169         void __iomem *regs;
 170 };
 171
 172 struct vc4_hvs {
 173         struct platform_device *pdev;
 174         void __iomem *regs;
 175         u32 __iomem *dlist;
 176
 177         /* Memory manager for CRTCs to allocate space in the display
 178          * list.  Units are dwords.
 179          */
 180         struct drm_mm dlist_mm;
 181         /* Memory manager for the LBM memory used by HVS scaling. */
 182         struct drm_mm lbm_mm;
 183         spinlock_t mm_lock;
 184
 185         struct drm_mm_node mitchell_netravali_filter;
 186 };
 187
 188 struct vc4_plane {
 189         struct drm_plane base;
 190 };
 191
 192 static inline struct vc4_plane *
 193 to_vc4_plane(struct drm_plane *plane)
 194 {
 195         return (struct vc4_plane *)plane;
 196 }
 197
 198 enum vc4_encoder_type {
 199         VC4_ENCODER_TYPE_NONE,
 200         VC4_ENCODER_TYPE_HDMI,
 201         VC4_ENCODER_TYPE_VEC,
 202         VC4_ENCODER_TYPE_DSI0,
 203         VC4_ENCODER_TYPE_DSI1,
 204         VC4_ENCODER_TYPE_SMI,
 205         VC4_ENCODER_TYPE_DPI,
 206 };
 207
 208 struct vc4_encoder {
 209         struct drm_encoder base;
 210         enum vc4_encoder_type type;
 211         u32 clock_select;
 212 };
 213
 214 static inline struct vc4_encoder *
 215 to_vc4_encoder(struct drm_encoder *encoder)
 216 {
 217         return container_of(encoder, struct vc4_encoder, base);
 218 }
 219
 220 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
 221 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
 222 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
 223 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
 224
 225 struct vc4_exec_info {
 226         /* Sequence number for this bin/render job. */
 227         uint64_t seqno;
 228
 229         /* Latest write_seqno of any BO that binning depends on. */
 230         uint64_t bin_dep_seqno;
 231
 232         /* Last current addresses the hardware was processing when the
 233          * hangcheck timer checked on us.
 234          */
 235         uint32_t last_ct0ca, last_ct1ca;
 236
 237         /* Kernel-space copy of the ioctl arguments */
 238         struct drm_vc4_submit_cl *args;
 239
 240         /* This is the array of BOs that were looked up at the start of exec.
 241          * Command validation will use indices into this array.
 242          */
 243         struct drm_gem_cma_object **bo;
 244         uint32_t bo_count;
 245
 246         /* List of BOs that are being written by the RCL.  Other than
 247          * the binner temporary storage, this is all the BOs written
 248          * by the job.
 249          */
 250         struct drm_gem_cma_object *rcl_write_bo[4];
 251         uint32_t rcl_write_bo_count;
 252
 253         /* Pointers for our position in vc4->job_list */
 254         struct list_head head;
 255
 256         /* List of other BOs used in the job that need to be released
 257          * once the job is complete.
 258          */
 259         struct list_head unref_list;
 260
 261         /* Current unvalidated indices into @bo loaded by the non-hardware
 262          * VC4_PACKET_GEM_HANDLES.
 263          */
 264         uint32_t bo_index[2];
 265
 266         /* This is the BO where we store the validated command lists, shader
 267          * records, and uniforms.
 268          */
 269         struct drm_gem_cma_object *exec_bo;
 270
 271         /**
 272          * This tracks the per-shader-record state (packet 64) that
 273          * determines the length of the shader record and the offset
 274          * it's expected to be found at.  It gets read in from the
 275          * command lists.
 276          */
 277         struct vc4_shader_state {
 278                 uint32_t addr;
 279                 /* Maximum vertex index referenced by any primitive using this
 280                  * shader state.
 281                  */
 282                 uint32_t max_index;
 283         } *shader_state;
 284
 285         /** How many shader states the user declared they were using. */
 286         uint32_t shader_state_size;
 287         /** How many shader state records the validator has seen. */
 288         uint32_t shader_state_count;
 289
 290         bool found_tile_binning_mode_config_packet;
 291         bool found_start_tile_binning_packet;
 292         bool found_increment_semaphore_packet;
 293         bool found_flush;
 294         uint8_t bin_tiles_x, bin_tiles_y;
 295         struct drm_gem_cma_object *tile_bo;
 296         uint32_t tile_alloc_offset;
 297
 298         /**
 299          * Computed addresses pointing into exec_bo where we start the
 300          * bin thread (ct0) and render thread (ct1).
 301          */
 302         uint32_t ct0ca, ct0ea;
 303         uint32_t ct1ca, ct1ea;
 304
 305         /* Pointer to the unvalidated bin CL (if present). */
 306         void *bin_u;
 307
 308         /* Pointers to the shader recs.  These paddr gets incremented as CL
 309          * packets are relocated in validate_gl_shader_state, and the vaddrs
 310          * (u and v) get incremented and size decremented as the shader recs
 311          * themselves are validated.
 312          */
 313         void *shader_rec_u;
 314         void *shader_rec_v;
 315         uint32_t shader_rec_p;
 316         uint32_t shader_rec_size;
 317
 318         /* Pointers to the uniform data.  These pointers are incremented, and
 319          * size decremented, as each batch of uniforms is uploaded.
 320          */
 321         void *uniforms_u;
 322         void *uniforms_v;
 323         uint32_t uniforms_p;
 324         uint32_t uniforms_size;
 325 };
 326
 327 static inline struct vc4_exec_info *
 328 vc4_first_bin_job(struct vc4_dev *vc4)
 329 {
 330         return list_first_entry_or_null(&vc4->bin_job_list,
 331                                         struct vc4_exec_info, head);
 332 }
 333
 334 static inline struct vc4_exec_info *
 335 vc4_first_render_job(struct vc4_dev *vc4)
 336 {
 337         return list_first_entry_or_null(&vc4->render_job_list,
 338                                         struct vc4_exec_info, head);
 339 }
 340
 341 static inline struct vc4_exec_info *
 342 vc4_last_render_job(struct vc4_dev *vc4)
 343 {
 344         if (list_empty(&vc4->render_job_list))
 345                 return NULL;
 346         return list_last_entry(&vc4->render_job_list,
 347                                struct vc4_exec_info, head);
 348 }
 349
 350 /**
 351  * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
 352  * setup parameters.
 353  *
 354  * This will be used at draw time to relocate the reference to the texture
 355  * contents in p0, and validate that the offset combined with
 356  * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
 357  * Note that the hardware treats unprovided config parameters as 0, so not all
 358  * of them need to be set up for every texure sample, and we'll store ~0 as
 359  * the offset to mark the unused ones.
 360  *
 361  * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
 362  * Setup") for definitions of the texture parameters.
 363  */
 364 struct vc4_texture_sample_info {
 365         bool is_direct;
 366         uint32_t p_offset[4];
 367 };
 368
 369 /**
 370  * struct vc4_validated_shader_info - information about validated shaders that
 371  * needs to be used from command list validation.
 372  *
 373  * For a given shader, each time a shader state record references it, we need
 374  * to verify that the shader doesn't read more uniforms than the shader state
 375  * record's uniform BO pointer can provide, and we need to apply relocations
 376  * and validate the shader state record's uniforms that define the texture
 377  * samples.
 378  */
 379 struct vc4_validated_shader_info {
 380         uint32_t uniforms_size;
 381         uint32_t uniforms_src_size;
 382         uint32_t num_texture_samples;
 383         struct vc4_texture_sample_info *texture_samples;
 384
 385         uint32_t num_uniform_addr_offsets;
 386         uint32_t *uniform_addr_offsets;
 387
 388         bool is_threaded;
 389 };
 390
 391 /**
 392  * _wait_for - magic (register) wait macro
 393  *
 394  * Does the right thing for modeset paths when run under kdgb or similar atomic
 395  * contexts. Note that it's important that we check the condition again after
 396  * having timed out, since the timeout could be due to preemption or similar and
 397  * we've never had a chance to check the condition before the timeout.
 398  */
 399 #define _wait_for(COND, MS, W) ({ \
 400         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
 401         int ret__ = 0;                                                  \
 402         while (!(COND)) {                                               \
 403                 if (time_after(jiffies, timeout__)) {                   \
 404                         if (!(COND))                                    \
 405                                 ret__ = -ETIMEDOUT;                     \
 406                         break;                                          \
 407                 }                                                       \
 408                 if (W && drm_can_sleep())  {                            \
 409                         msleep(W);                                      \
 410                 } else {                                                \
 411                         cpu_relax();                                    \
 412                 }                                                       \
 413         }                                                               \
 414         ret__;                                                          \
 415 })
 416
 417 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
 418
 419 /* vc4_bo.c */
 420 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
 421 void vc4_free_object(struct drm_gem_object *gem_obj);
 422 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
 423                              bool from_cache);
 424 int vc4_dumb_create(struct drm_file *file_priv,
 425                     struct drm_device *dev,
 426                     struct drm_mode_create_dumb *args);
 427 struct dma_buf *vc4_prime_export(struct drm_device *dev,
 428                                  struct drm_gem_object *obj, int flags);
 429 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 430                         struct drm_file *file_priv);
 431 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
 432                                struct drm_file *file_priv);
 433 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
 434                       struct drm_file *file_priv);
 435 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
 436                              struct drm_file *file_priv);
 437 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
 438 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
 439 void *vc4_prime_vmap(struct drm_gem_object *obj);
 440 void vc4_bo_cache_init(struct drm_device *dev);
 441 void vc4_bo_cache_destroy(struct drm_device *dev);
 442 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
 443
 444 /* vc4_crtc.c */
 445 extern struct platform_driver vc4_crtc_driver;
 446 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id);
 447 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
 448 bool vc4_event_pending(struct drm_crtc *crtc);
 449 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
 450 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 451                             unsigned int flags, int *vpos, int *hpos,
 452                             ktime_t *stime, ktime_t *etime,
 453                             const struct drm_display_mode *mode);
 454 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
 455                                   int *max_error, struct timeval *vblank_time,
 456                                   unsigned flags);
 457
 458 /* vc4_debugfs.c */
 459 int vc4_debugfs_init(struct drm_minor *minor);
 460 void vc4_debugfs_cleanup(struct drm_minor *minor);
 461
 462 /* vc4_drv.c */
 463 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
 464
 465 /* vc4_dpi.c */
 466 extern struct platform_driver vc4_dpi_driver;
 467 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
 468
 469 /* vc4_gem.c */
 470 void vc4_gem_init(struct drm_device *dev);
 471 void vc4_gem_destroy(struct drm_device *dev);
 472 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 473                         struct drm_file *file_priv);
 474 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
 475                          struct drm_file *file_priv);
 476 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
 477                       struct drm_file *file_priv);
 478 void vc4_submit_next_bin_job(struct drm_device *dev);
 479 void vc4_submit_next_render_job(struct drm_device *dev);
 480 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
 481 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
 482                        uint64_t timeout_ns, bool interruptible);
 483 void vc4_job_handle_completed(struct vc4_dev *vc4);
 484 int vc4_queue_seqno_cb(struct drm_device *dev,
 485                        struct vc4_seqno_cb *cb, uint64_t seqno,
 486                        void (*func)(struct vc4_seqno_cb *cb));
 487
 488 /* vc4_hdmi.c */
 489 extern struct platform_driver vc4_hdmi_driver;
 490 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
 491
 492 /* vc4_hdmi.c */
 493 extern struct platform_driver vc4_vec_driver;
 494 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
 495
 496 /* vc4_irq.c */
 497 irqreturn_t vc4_irq(int irq, void *arg);
 498 void vc4_irq_preinstall(struct drm_device *dev);
 499 int vc4_irq_postinstall(struct drm_device *dev);
 500 void vc4_irq_uninstall(struct drm_device *dev);
 501 void vc4_irq_reset(struct drm_device *dev);
 502
 503 /* vc4_hvs.c */
 504 extern struct platform_driver vc4_hvs_driver;
 505 void vc4_hvs_dump_state(struct drm_device *dev);
 506 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
 507
 508 /* vc4_kms.c */
 509 int vc4_kms_load(struct drm_device *dev);
 510
 511 /* vc4_plane.c */
 512 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 513                                  enum drm_plane_type type);
 514 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
 515 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
 516 void vc4_plane_async_set_fb(struct drm_plane *plane,
 517                             struct drm_framebuffer *fb);
 518
 519 /* vc4_v3d.c */
 520 extern struct platform_driver vc4_v3d_driver;
 521 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
 522 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
 523
 524 /* vc4_validate.c */
 525 int
 526 vc4_validate_bin_cl(struct drm_device *dev,
 527                     void *validated,
 528                     void *unvalidated,
 529                     struct vc4_exec_info *exec);
 530
 531 int
 532 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
 533
 534 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
 535                                       uint32_t hindex);
 536
 537 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
 538
 539 bool vc4_check_tex_size(struct vc4_exec_info *exec,
 540                         struct drm_gem_cma_object *fbo,
 541                         uint32_t offset, uint8_t tiling_format,
 542                         uint32_t width, uint32_t height, uint8_t cpp);
 543
 544 /* vc4_validate_shader.c */
 545 struct vc4_validated_shader_info *
 546 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);