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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / clk / clk-vt8500.c
blob37e928846ec5b3fb1fed8144570c1f8aeaa027bb
1 /*
2 * Clock implementation for VIA/Wondermedia SoC's
3 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #include <linux/io.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/slab.h>
20 #include <linux/bitops.h>
21 #include <linux/clkdev.h>
22 #include <linux/clk-provider.h>
23
24 #define LEGACY_PMC_BASE 0xD8130000
25
26 /* All clocks share the same lock as none can be changed concurrently */
27 static DEFINE_SPINLOCK(_lock);
28
29 struct clk_device {
30 struct clk_hw hw;
31 void __iomem *div_reg;
32 unsigned int div_mask;
33 void __iomem *en_reg;
34 int en_bit;
35 spinlock_t *lock;
36 };
37
38 /*
39 * Add new PLL_TYPE_x definitions here as required. Use the first known model
40 * to support the new type as the name.
41 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
42 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
43 */
44
45 #define PLL_TYPE_VT8500 0
46 #define PLL_TYPE_WM8650 1
47 #define PLL_TYPE_WM8750 2
48 #define PLL_TYPE_WM8850 3
49
50 struct clk_pll {
51 struct clk_hw hw;
52 void __iomem *reg;
53 spinlock_t *lock;
54 int type;
55 };
56
57 static void __iomem *pmc_base;
58
59 static __init void vtwm_set_pmc_base(void)
60 {
61 struct device_node *np =
62 of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
63
64 if (np)
65 pmc_base = of_iomap(np, 0);
66 else
67 pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
68 of_node_put(np);
69
70 if (!pmc_base)
71 pr_err("%s:of_iomap(pmc) failed\n", __func__);
72 }
73
74 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
75
76 #define VT8500_PMC_BUSY_MASK 0x18
77
78 static void vt8500_pmc_wait_busy(void)
79 {
80 while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
81 cpu_relax();
82 }
83
84 static int vt8500_dclk_enable(struct clk_hw *hw)
85 {
86 struct clk_device *cdev = to_clk_device(hw);
87 u32 en_val;
88 unsigned long flags = 0;
89
90 spin_lock_irqsave(cdev->lock, flags);
91
92 en_val = readl(cdev->en_reg);
93 en_val |= BIT(cdev->en_bit);
94 writel(en_val, cdev->en_reg);
95
96 spin_unlock_irqrestore(cdev->lock, flags);
97 return 0;
98 }
99
100 static void vt8500_dclk_disable(struct clk_hw *hw)
101 {
102 struct clk_device *cdev = to_clk_device(hw);
103 u32 en_val;
104 unsigned long flags = 0;
105
106 spin_lock_irqsave(cdev->lock, flags);
107
108 en_val = readl(cdev->en_reg);
109 en_val &= ~BIT(cdev->en_bit);
110 writel(en_val, cdev->en_reg);
111
112 spin_unlock_irqrestore(cdev->lock, flags);
113 }
114
115 static int vt8500_dclk_is_enabled(struct clk_hw *hw)
116 {
117 struct clk_device *cdev = to_clk_device(hw);
118 u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
119
120 return en_val ? 1 : 0;
121 }
122
123 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
124 unsigned long parent_rate)
125 {
126 struct clk_device *cdev = to_clk_device(hw);
127 u32 div = readl(cdev->div_reg) & cdev->div_mask;
128
129 /* Special case for SDMMC devices */
130 if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
131 div = 64 * (div & 0x1f);
132
133 /* div == 0 is actually the highest divisor */
134 if (div == 0)
135 div = (cdev->div_mask + 1);
136
137 return parent_rate / div;
138 }
139
140 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
141 unsigned long *prate)
142 {
143 struct clk_device *cdev = to_clk_device(hw);
144 u32 divisor;
145
146 if (rate == 0)
147 return 0;
148
149 divisor = *prate / rate;
150
151 /* If prate / rate would be decimal, incr the divisor */
152 if (rate * divisor < *prate)
153 divisor++;
154
155 /*
156 * If this is a request for SDMMC we have to adjust the divisor
157 * when >31 to use the fixed predivisor
158 */
159 if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
160 divisor = 64 * ((divisor / 64) + 1);
161 }
162
163 return *prate / divisor;
164 }
165
166 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
167 unsigned long parent_rate)
168 {
169 struct clk_device *cdev = to_clk_device(hw);
170 u32 divisor;
171 unsigned long flags = 0;
172
173 if (rate == 0)
174 return 0;
175
176 divisor = parent_rate / rate;
177
178 if (divisor == cdev->div_mask + 1)
179 divisor = 0;
180
181 /* SDMMC mask may need to be corrected before testing if its valid */
182 if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
183 /*
184 * Bit 5 is a fixed /64 predivisor. If the requested divisor
185 * is >31 then correct for the fixed divisor being required.
186 */
187 divisor = 0x20 + (divisor / 64);
188 }
189
190 if (divisor > cdev->div_mask) {
191 pr_err("%s: invalid divisor for clock\n", __func__);
192 return -EINVAL;
193 }
194
195 spin_lock_irqsave(cdev->lock, flags);
196
197 vt8500_pmc_wait_busy();
198 writel(divisor, cdev->div_reg);
199 vt8500_pmc_wait_busy();
200
201 spin_unlock_irqrestore(cdev->lock, flags);
202
203 return 0;
204 }
205
206
207 static const struct clk_ops vt8500_gated_clk_ops = {
208 .enable = vt8500_dclk_enable,
209 .disable = vt8500_dclk_disable,
210 .is_enabled = vt8500_dclk_is_enabled,
211 };
212
213 static const struct clk_ops vt8500_divisor_clk_ops = {
214 .round_rate = vt8500_dclk_round_rate,
215 .set_rate = vt8500_dclk_set_rate,
216 .recalc_rate = vt8500_dclk_recalc_rate,
217 };
218
219 static const struct clk_ops vt8500_gated_divisor_clk_ops = {
220 .enable = vt8500_dclk_enable,
221 .disable = vt8500_dclk_disable,
222 .is_enabled = vt8500_dclk_is_enabled,
223 .round_rate = vt8500_dclk_round_rate,
224 .set_rate = vt8500_dclk_set_rate,
225 .recalc_rate = vt8500_dclk_recalc_rate,
226 };
227
228 #define CLK_INIT_GATED BIT(0)
229 #define CLK_INIT_DIVISOR BIT(1)
230 #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
231
232 static __init void vtwm_device_clk_init(struct device_node *node)
233 {
234 u32 en_reg, div_reg;
235 struct clk *clk;
236 struct clk_device *dev_clk;
237 const char *clk_name = node->name;
238 const char *parent_name;
239 struct clk_init_data init;
240 int rc;
241 int clk_init_flags = 0;
242
243 if (!pmc_base)
244 vtwm_set_pmc_base();
245
246 dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
247 if (WARN_ON(!dev_clk))
248 return;
249
250 dev_clk->lock = &_lock;
251
252 rc = of_property_read_u32(node, "enable-reg", &en_reg);
253 if (!rc) {
254 dev_clk->en_reg = pmc_base + en_reg;
255 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
256 if (rc) {
257 pr_err("%s: enable-bit property required for gated clock\n",
258 __func__);
259 return;
260 }
261 clk_init_flags |= CLK_INIT_GATED;
262 }
263
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg);
265 if (!rc) {
266 dev_clk->div_reg = pmc_base + div_reg;
267 /*
268 * use 0x1f as the default mask since it covers
269 * almost all the clocks and reduces dts properties
270 */
271 dev_clk->div_mask = 0x1f;
272
273 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
274 clk_init_flags |= CLK_INIT_DIVISOR;
275 }
276
277 of_property_read_string(node, "clock-output-names", &clk_name);
278
279 switch (clk_init_flags) {
280 case CLK_INIT_GATED:
281 init.ops = &vt8500_gated_clk_ops;
282 break;
283 case CLK_INIT_DIVISOR:
284 init.ops = &vt8500_divisor_clk_ops;
285 break;
286 case CLK_INIT_GATED_DIVISOR:
287 init.ops = &vt8500_gated_divisor_clk_ops;
288 break;
289 default:
290 pr_err("%s: Invalid clock description in device tree\n",
291 __func__);
292 kfree(dev_clk);
293 return;
294 }
295
296 init.name = clk_name;
297 init.flags = 0;
298 parent_name = of_clk_get_parent_name(node, 0);
299 init.parent_names = &parent_name;
300 init.num_parents = 1;
301
302 dev_clk->hw.init = &init;
303
304 clk = clk_register(NULL, &dev_clk->hw);
305 if (WARN_ON(IS_ERR(clk))) {
306 kfree(dev_clk);
307 return;
308 }
309 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
310 clk_register_clkdev(clk, clk_name, NULL);
311 }
312 CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
313
314 /* PLL clock related functions */
315
316 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
317
318 /* Helper macros for PLL_VT8500 */
319 #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
320 #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
321
322 #define VT8500_BITS_TO_FREQ(r, m, d) \
323 ((r / d) * m)
324
325 #define VT8500_BITS_TO_VAL(m, d) \
326 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
327
328 /* Helper macros for PLL_WM8650 */
329 #define WM8650_PLL_MUL(x) (x & 0x3FF)
330 #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
331
332 #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
333 (r * m / (d1 * (1 << d2)))
334
335 #define WM8650_BITS_TO_VAL(m, d1, d2) \
336 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
337
338 /* Helper macros for PLL_WM8750 */
339 #define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1)
340 #define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
341
342 #define WM8750_BITS_TO_FREQ(r, m, d1, d2) \
343 (r * (m+1) / ((d1+1) * (1 << d2)))
344
345 #define WM8750_BITS_TO_VAL(f, m, d1, d2) \
346 ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
347
348 /* Helper macros for PLL_WM8850 */
349 #define WM8850_PLL_MUL(x) ((((x >> 16) & 0x7F) + 1) * 2)
350 #define WM8850_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 3)))
351
352 #define WM8850_BITS_TO_FREQ(r, m, d1, d2) \
353 (r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
354
355 #define WM8850_BITS_TO_VAL(m, d1, d2) \
356 ((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
357
358 static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
359 u32 *multiplier, u32 *prediv)
360 {
361 unsigned long tclk;
362
363 /* sanity check */
364 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
365 pr_err("%s: requested rate out of range\n", __func__);
366 *multiplier = 0;
367 *prediv = 1;
368 return;
369 }
370 if (rate <= parent_rate * 31)
371 /* use the prediv to double the resolution */
372 *prediv = 2;
373 else
374 *prediv = 1;
375
376 *multiplier = rate / (parent_rate / *prediv);
377 tclk = (parent_rate / *prediv) * *multiplier;
378
379 if (tclk != rate)
380 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
381 rate, tclk);
382 }
383
384 static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
385 u32 *multiplier, u32 *divisor1, u32 *divisor2)
386 {
387 u32 mul, div1, div2;
388 u32 best_mul, best_div1, best_div2;
389 unsigned long tclk, rate_err, best_err;
390
391 best_err = (unsigned long)-1;
392
393 /* Find the closest match (lower or equal to requested) */
394 for (div1 = 5; div1 >= 3; div1--)
395 for (div2 = 3; div2 >= 0; div2--)
396 for (mul = 3; mul <= 1023; mul++) {
397 tclk = parent_rate * mul / (div1 * (1 << div2));
398 if (tclk > rate)
399 continue;
400 /* error will always be +ve */
401 rate_err = rate - tclk;
402 if (rate_err == 0) {
403 *multiplier = mul;
404 *divisor1 = div1;
405 *divisor2 = div2;
406 return;
407 }
408
409 if (rate_err < best_err) {
410 best_err = rate_err;
411 best_mul = mul;
412 best_div1 = div1;
413 best_div2 = div2;
414 }
415 }
416
417 /* if we got here, it wasn't an exact match */
418 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
419 rate - best_err);
420 *multiplier = best_mul;
421 *divisor1 = best_div1;
422 *divisor2 = best_div2;
423 }
424
425 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
426 {
427 /* calculate frequency (MHz) after pre-divisor */
428 u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
429
430 if ((freq < 10) || (freq > 200))
431 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
432 __func__, freq);
433
434 if (freq >= 166)
435 return 7;
436 else if (freq >= 104)
437 return 6;
438 else if (freq >= 65)
439 return 5;
440 else if (freq >= 42)
441 return 4;
442 else if (freq >= 26)
443 return 3;
444 else if (freq >= 16)
445 return 2;
446 else if (freq >= 10)
447 return 1;
448
449 return 0;
450 }
451
452 static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
453 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
454 {
455 u32 mul, div1, div2;
456 u32 best_mul, best_div1, best_div2;
457 unsigned long tclk, rate_err, best_err;
458
459 best_err = (unsigned long)-1;
460
461 /* Find the closest match (lower or equal to requested) */
462 for (div1 = 1; div1 >= 0; div1--)
463 for (div2 = 7; div2 >= 0; div2--)
464 for (mul = 0; mul <= 255; mul++) {
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
466 if (tclk > rate)
467 continue;
468 /* error will always be +ve */
469 rate_err = rate - tclk;
470 if (rate_err == 0) {
471 *filter = wm8750_get_filter(parent_rate, div1);
472 *multiplier = mul;
473 *divisor1 = div1;
474 *divisor2 = div2;
475 return;
476 }
477
478 if (rate_err < best_err) {
479 best_err = rate_err;
480 best_mul = mul;
481 best_div1 = div1;
482 best_div2 = div2;
483 }
484 }
485
486 /* if we got here, it wasn't an exact match */
487 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
488 rate - best_err);
489
490 *filter = wm8750_get_filter(parent_rate, best_div1);
491 *multiplier = best_mul;
492 *divisor1 = best_div1;
493 *divisor2 = best_div2;
494 }
495
496 static void wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
497 u32 *multiplier, u32 *divisor1, u32 *divisor2)
498 {
499 u32 mul, div1, div2;
500 u32 best_mul, best_div1, best_div2;
501 unsigned long tclk, rate_err, best_err;
502
503 best_err = (unsigned long)-1;
504
505 /* Find the closest match (lower or equal to requested) */
506 for (div1 = 1; div1 >= 0; div1--)
507 for (div2 = 3; div2 >= 0; div2--)
508 for (mul = 0; mul <= 127; mul++) {
509 tclk = parent_rate * ((mul + 1) * 2) /
510 ((div1 + 1) * (1 << div2));
511 if (tclk > rate)
512 continue;
513 /* error will always be +ve */
514 rate_err = rate - tclk;
515 if (rate_err == 0) {
516 *multiplier = mul;
517 *divisor1 = div1;
518 *divisor2 = div2;
519 return;
520 }
521
522 if (rate_err < best_err) {
523 best_err = rate_err;
524 best_mul = mul;
525 best_div1 = div1;
526 best_div2 = div2;
527 }
528 }
529
530 /* if we got here, it wasn't an exact match */
531 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
532 rate - best_err);
533
534 *multiplier = best_mul;
535 *divisor1 = best_div1;
536 *divisor2 = best_div2;
537 }
538
539 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
540 unsigned long parent_rate)
541 {
542 struct clk_pll *pll = to_clk_pll(hw);
543 u32 filter, mul, div1, div2;
544 u32 pll_val;
545 unsigned long flags = 0;
546
547 /* sanity check */
548
549 switch (pll->type) {
550 case PLL_TYPE_VT8500:
551 vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
552 pll_val = VT8500_BITS_TO_VAL(mul, div1);
553 break;
554 case PLL_TYPE_WM8650:
555 wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
556 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
557 break;
558 case PLL_TYPE_WM8750:
559 wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
560 pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
561 break;
562 case PLL_TYPE_WM8850:
563 wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
564 pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
565 break;
566 default:
567 pr_err("%s: invalid pll type\n", __func__);
568 return 0;
569 }
570
571 spin_lock_irqsave(pll->lock, flags);
572
573 vt8500_pmc_wait_busy();
574 writel(pll_val, pll->reg);
575 vt8500_pmc_wait_busy();
576
577 spin_unlock_irqrestore(pll->lock, flags);
578
579 return 0;
580 }
581
582 static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
583 unsigned long *prate)
584 {
585 struct clk_pll *pll = to_clk_pll(hw);
586 u32 filter, mul, div1, div2;
587 long round_rate;
588
589 switch (pll->type) {
590 case PLL_TYPE_VT8500:
591 vt8500_find_pll_bits(rate, *prate, &mul, &div1);
592 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
593 break;
594 case PLL_TYPE_WM8650:
595 wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
596 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
597 break;
598 case PLL_TYPE_WM8750:
599 wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
600 round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
601 break;
602 case PLL_TYPE_WM8850:
603 wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
604 round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
605 break;
606 default:
607 round_rate = 0;
608 }
609
610 return round_rate;
611 }
612
613 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
614 unsigned long parent_rate)
615 {
616 struct clk_pll *pll = to_clk_pll(hw);
617 u32 pll_val = readl(pll->reg);
618 unsigned long pll_freq;
619
620 switch (pll->type) {
621 case PLL_TYPE_VT8500:
622 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
623 pll_freq /= VT8500_PLL_DIV(pll_val);
624 break;
625 case PLL_TYPE_WM8650:
626 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
627 pll_freq /= WM8650_PLL_DIV(pll_val);
628 break;
629 case PLL_TYPE_WM8750:
630 pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
631 pll_freq /= WM8750_PLL_DIV(pll_val);
632 break;
633 case PLL_TYPE_WM8850:
634 pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
635 pll_freq /= WM8850_PLL_DIV(pll_val);
636 break;
637 default:
638 pll_freq = 0;
639 }
640
641 return pll_freq;
642 }
643
644 static const struct clk_ops vtwm_pll_ops = {
645 .round_rate = vtwm_pll_round_rate,
646 .set_rate = vtwm_pll_set_rate,
647 .recalc_rate = vtwm_pll_recalc_rate,
648 };
649
650 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
651 {
652 u32 reg;
653 struct clk *clk;
654 struct clk_pll *pll_clk;
655 const char *clk_name = node->name;
656 const char *parent_name;
657 struct clk_init_data init;
658 int rc;
659
660 if (!pmc_base)
661 vtwm_set_pmc_base();
662
663 rc = of_property_read_u32(node, "reg", &reg);
664 if (WARN_ON(rc))
665 return;
666
667 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
668 if (WARN_ON(!pll_clk))
669 return;
670
671 pll_clk->reg = pmc_base + reg;
672 pll_clk->lock = &_lock;
673 pll_clk->type = pll_type;
674
675 of_property_read_string(node, "clock-output-names", &clk_name);
676
677 init.name = clk_name;
678 init.ops = &vtwm_pll_ops;
679 init.flags = 0;
680 parent_name = of_clk_get_parent_name(node, 0);
681 init.parent_names = &parent_name;
682 init.num_parents = 1;
683
684 pll_clk->hw.init = &init;
685
686 clk = clk_register(NULL, &pll_clk->hw);
687 if (WARN_ON(IS_ERR(clk))) {
688 kfree(pll_clk);
689 return;
690 }
691 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
692 clk_register_clkdev(clk, clk_name, NULL);
693 }
694
695
696 /* Wrappers for initialization functions */
697
698 static void __init vt8500_pll_init(struct device_node *node)
699 {
700 vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
701 }
702 CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
703
704 static void __init wm8650_pll_init(struct device_node *node)
705 {
706 vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
707 }
708 CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
709
710 static void __init wm8750_pll_init(struct device_node *node)
711 {
712 vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
713 }
714 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
715
716 static void __init wm8850_pll_init(struct device_node *node)
717 {
718 vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
719 }
720 CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);
Linux with added FPC-III support