ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / clk / qcom / clk-branch.h
blob284df3f3c55f76c27e7abbe4db9c953b01f7581f
1 /*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __QCOM_CLK_BRANCH_H__
15 #define __QCOM_CLK_BRANCH_H__
17 #include <linux/clk-provider.h>
19 #include "clk-regmap.h"
21 /**
22 * struct clk_branch - gating clock with status bit and dynamic hardware gating
24 * @hwcg_reg: dynamic hardware clock gating register
25 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
26 * @halt_reg: halt register
27 * @halt_bit: ANDed with @halt_reg to test for clock halted
28 * @halt_check: type of halt checking to perform
29 * @clkr: handle between common and hardware-specific interfaces
31 * Clock which can gate its output.
33 struct clk_branch {
34 u32 hwcg_reg;
35 u32 halt_reg;
36 u8 hwcg_bit;
37 u8 halt_bit;
38 u8 halt_check;
39 #define BRANCH_VOTED BIT(7) /* Delay on disable */
40 #define BRANCH_HALT 0 /* pol: 1 = halt */
41 #define BRANCH_HALT_VOTED (BRANCH_HALT | BRANCH_VOTED)
42 #define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
43 #define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED)
44 #define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */
46 struct clk_regmap clkr;
49 extern const struct clk_ops clk_branch_ops;
50 extern const struct clk_ops clk_branch2_ops;
51 extern const struct clk_ops clk_branch_simple_ops;
53 #define to_clk_branch(_hw) \
54 container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
56 #endif