drivers/clk/qcom/clk-rcg2.c

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/bug.h>
  18 #include <linux/export.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/delay.h>
  21 #include <linux/regmap.h>
  22 #include <linux/math64.h>
  23
  24 #include <asm/div64.h>
  25
  26 #include "clk-rcg.h"
  27 #include "common.h"
  28
  29 #define CMD_REG                 0x0
  30 #define CMD_UPDATE              BIT(0)
  31 #define CMD_ROOT_EN             BIT(1)
  32 #define CMD_DIRTY_CFG           BIT(4)
  33 #define CMD_DIRTY_N             BIT(5)
  34 #define CMD_DIRTY_M             BIT(6)
  35 #define CMD_DIRTY_D             BIT(7)
  36 #define CMD_ROOT_OFF            BIT(31)
  37
  38 #define CFG_REG                 0x4
  39 #define CFG_SRC_DIV_SHIFT       0
  40 #define CFG_SRC_SEL_SHIFT       8
  41 #define CFG_SRC_SEL_MASK        (0x7 << CFG_SRC_SEL_SHIFT)
  42 #define CFG_MODE_SHIFT          12
  43 #define CFG_MODE_MASK           (0x3 << CFG_MODE_SHIFT)
  44 #define CFG_MODE_DUAL_EDGE      (0x2 << CFG_MODE_SHIFT)
  45
  46 #define M_REG                   0x8
  47 #define N_REG                   0xc
  48 #define D_REG                   0x10
  49
  50 static int clk_rcg2_is_enabled(struct clk_hw *hw)
  51 {
  52         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
  53         u32 cmd;
  54         int ret;
  55
  56         ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
  57         if (ret)
  58                 return ret;
  59
  60         return (cmd & CMD_ROOT_OFF) == 0;
  61 }
  62
  63 static u8 clk_rcg2_get_parent(struct clk_hw *hw)
  64 {
  65         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
  66         int num_parents = __clk_get_num_parents(hw->clk);
  67         u32 cfg;
  68         int i, ret;
  69
  70         ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
  71         if (ret)
  72                 return ret;
  73
  74         cfg &= CFG_SRC_SEL_MASK;
  75         cfg >>= CFG_SRC_SEL_SHIFT;
  76
  77         for (i = 0; i < num_parents; i++)
  78                 if (cfg == rcg->parent_map[i])
  79                         return i;
  80
  81         return -EINVAL;
  82 }
  83
  84 static int update_config(struct clk_rcg2 *rcg)
  85 {
  86         int count, ret;
  87         u32 cmd;
  88         struct clk_hw *hw = &rcg->clkr.hw;
  89         const char *name = __clk_get_name(hw->clk);
  90
  91         ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
  92                                  CMD_UPDATE, CMD_UPDATE);
  93         if (ret)
  94                 return ret;
  95
  96         /* Wait for update to take effect */
  97         for (count = 500; count > 0; count--) {
  98                 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
  99                 if (ret)
 100                         return ret;
 101                 if (!(cmd & CMD_UPDATE))
 102                         return 0;
 103                 udelay(1);
 104         }
 105
 106         WARN(1, "%s: rcg didn't update its configuration.", name);
 107         return 0;
 108 }
 109
 110 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
 111 {
 112         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 113         int ret;
 114
 115         ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
 116                                  CFG_SRC_SEL_MASK,
 117                                  rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
 118         if (ret)
 119                 return ret;
 120
 121         return update_config(rcg);
 122 }
 123
 124 /*
 125  * Calculate m/n:d rate
 126  *
 127  *          parent_rate     m
 128  *   rate = ----------- x  ---
 129  *            hid_div       n
 130  */
 131 static unsigned long
 132 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
 133 {
 134         if (hid_div) {
 135                 rate *= 2;
 136                 rate /= hid_div + 1;
 137         }
 138
 139         if (mode) {
 140                 u64 tmp = rate;
 141                 tmp *= m;
 142                 do_div(tmp, n);
 143                 rate = tmp;
 144         }
 145
 146         return rate;
 147 }
 148
 149 static unsigned long
 150 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 151 {
 152         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 153         u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
 154
 155         regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
 156
 157         if (rcg->mnd_width) {
 158                 mask = BIT(rcg->mnd_width) - 1;
 159                 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
 160                 m &= mask;
 161                 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
 162                 n =  ~n;
 163                 n &= mask;
 164                 n += m;
 165                 mode = cfg & CFG_MODE_MASK;
 166                 mode >>= CFG_MODE_SHIFT;
 167         }
 168
 169         mask = BIT(rcg->hid_width) - 1;
 170         hid_div = cfg >> CFG_SRC_DIV_SHIFT;
 171         hid_div &= mask;
 172
 173         return calc_rate(parent_rate, m, n, mode, hid_div);
 174 }
 175
 176 static long _freq_tbl_determine_rate(struct clk_hw *hw,
 177                 const struct freq_tbl *f, unsigned long rate,
 178                 unsigned long *p_rate, struct clk_hw **p_hw)
 179 {
 180         unsigned long clk_flags;
 181         struct clk *p;
 182
 183         f = qcom_find_freq(f, rate);
 184         if (!f)
 185                 return -EINVAL;
 186
 187         clk_flags = __clk_get_flags(hw->clk);
 188         p = clk_get_parent_by_index(hw->clk, f->src);
 189         if (clk_flags & CLK_SET_RATE_PARENT) {
 190                 if (f->pre_div) {
 191                         rate /= 2;
 192                         rate *= f->pre_div + 1;
 193                 }
 194
 195                 if (f->n) {
 196                         u64 tmp = rate;
 197                         tmp = tmp * f->n;
 198                         do_div(tmp, f->m);
 199                         rate = tmp;
 200                 }
 201         } else {
 202                 rate =  __clk_get_rate(p);
 203         }
 204         *p_hw = __clk_get_hw(p);
 205         *p_rate = rate;
 206
 207         return f->freq;
 208 }
 209
 210 static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
 211                 unsigned long *p_rate, struct clk_hw **p)
 212 {
 213         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 214
 215         return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
 216 }
 217
 218 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 219 {
 220         u32 cfg, mask;
 221         int ret;
 222
 223         if (rcg->mnd_width && f->n) {
 224                 mask = BIT(rcg->mnd_width) - 1;
 225                 ret = regmap_update_bits(rcg->clkr.regmap,
 226                                 rcg->cmd_rcgr + M_REG, mask, f->m);
 227                 if (ret)
 228                         return ret;
 229
 230                 ret = regmap_update_bits(rcg->clkr.regmap,
 231                                 rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
 232                 if (ret)
 233                         return ret;
 234
 235                 ret = regmap_update_bits(rcg->clkr.regmap,
 236                                 rcg->cmd_rcgr + D_REG, mask, ~f->n);
 237                 if (ret)
 238                         return ret;
 239         }
 240
 241         mask = BIT(rcg->hid_width) - 1;
 242         mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
 243         cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
 244         cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
 245         if (rcg->mnd_width && f->n)
 246                 cfg |= CFG_MODE_DUAL_EDGE;
 247         ret = regmap_update_bits(rcg->clkr.regmap,
 248                         rcg->cmd_rcgr + CFG_REG, mask, cfg);
 249         if (ret)
 250                 return ret;
 251
 252         return update_config(rcg);
 253 }
 254
 255 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
 256 {
 257         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 258         const struct freq_tbl *f;
 259
 260         f = qcom_find_freq(rcg->freq_tbl, rate);
 261         if (!f)
 262                 return -EINVAL;
 263
 264         return clk_rcg2_configure(rcg, f);
 265 }
 266
 267 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
 268                             unsigned long parent_rate)
 269 {
 270         return __clk_rcg2_set_rate(hw, rate);
 271 }
 272
 273 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
 274                 unsigned long rate, unsigned long parent_rate, u8 index)
 275 {
 276         return __clk_rcg2_set_rate(hw, rate);
 277 }
 278
 279 const struct clk_ops clk_rcg2_ops = {
 280         .is_enabled = clk_rcg2_is_enabled,
 281         .get_parent = clk_rcg2_get_parent,
 282         .set_parent = clk_rcg2_set_parent,
 283         .recalc_rate = clk_rcg2_recalc_rate,
 284         .determine_rate = clk_rcg2_determine_rate,
 285         .set_rate = clk_rcg2_set_rate,
 286         .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
 287 };
 288 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
 289
 290 struct frac_entry {
 291         int num;
 292         int den;
 293 };
 294
 295 static const struct frac_entry frac_table_675m[] = {    /* link rate of 270M */
 296         { 52, 295 },    /* 119 M */
 297         { 11, 57 },     /* 130.25 M */
 298         { 63, 307 },    /* 138.50 M */
 299         { 11, 50 },     /* 148.50 M */
 300         { 47, 206 },    /* 154 M */
 301         { 31, 100 },    /* 205.25 M */
 302         { 107, 269 },   /* 268.50 M */
 303         { },
 304 };
 305
 306 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
 307         { 31, 211 },    /* 119 M */
 308         { 32, 199 },    /* 130.25 M */
 309         { 63, 307 },    /* 138.50 M */
 310         { 11, 60 },     /* 148.50 M */
 311         { 50, 263 },    /* 154 M */
 312         { 31, 120 },    /* 205.25 M */
 313         { 119, 359 },   /* 268.50 M */
 314         { },
 315 };
 316
 317 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 318                               unsigned long parent_rate)
 319 {
 320         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 321         struct freq_tbl f = *rcg->freq_tbl;
 322         const struct frac_entry *frac;
 323         int delta = 100000;
 324         s64 src_rate = parent_rate;
 325         s64 request;
 326         u32 mask = BIT(rcg->hid_width) - 1;
 327         u32 hid_div;
 328
 329         if (src_rate == 810000000)
 330                 frac = frac_table_810m;
 331         else
 332                 frac = frac_table_675m;
 333
 334         for (; frac->num; frac++) {
 335                 request = rate;
 336                 request *= frac->den;
 337                 request = div_s64(request, frac->num);
 338                 if ((src_rate < (request - delta)) ||
 339                     (src_rate > (request + delta)))
 340                         continue;
 341
 342                 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
 343                                 &hid_div);
 344                 f.pre_div = hid_div;
 345                 f.pre_div >>= CFG_SRC_DIV_SHIFT;
 346                 f.pre_div &= mask;
 347                 f.m = frac->num;
 348                 f.n = frac->den;
 349
 350                 return clk_rcg2_configure(rcg, &f);
 351         }
 352
 353         return -EINVAL;
 354 }
 355
 356 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
 357                 unsigned long rate, unsigned long parent_rate, u8 index)
 358 {
 359         /* Parent index is set statically in frequency table */
 360         return clk_edp_pixel_set_rate(hw, rate, parent_rate);
 361 }
 362
 363 static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
 364                                  unsigned long *p_rate, struct clk_hw **p)
 365 {
 366         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 367         const struct freq_tbl *f = rcg->freq_tbl;
 368         const struct frac_entry *frac;
 369         int delta = 100000;
 370         s64 src_rate = *p_rate;
 371         s64 request;
 372         u32 mask = BIT(rcg->hid_width) - 1;
 373         u32 hid_div;
 374
 375         /* Force the correct parent */
 376         *p = __clk_get_hw(clk_get_parent_by_index(hw->clk, f->src));
 377
 378         if (src_rate == 810000000)
 379                 frac = frac_table_810m;
 380         else
 381                 frac = frac_table_675m;
 382
 383         for (; frac->num; frac++) {
 384                 request = rate;
 385                 request *= frac->den;
 386                 request = div_s64(request, frac->num);
 387                 if ((src_rate < (request - delta)) ||
 388                     (src_rate > (request + delta)))
 389                         continue;
 390
 391                 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
 392                                 &hid_div);
 393                 hid_div >>= CFG_SRC_DIV_SHIFT;
 394                 hid_div &= mask;
 395
 396                 return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
 397                                  hid_div);
 398         }
 399
 400         return -EINVAL;
 401 }
 402
 403 const struct clk_ops clk_edp_pixel_ops = {
 404         .is_enabled = clk_rcg2_is_enabled,
 405         .get_parent = clk_rcg2_get_parent,
 406         .set_parent = clk_rcg2_set_parent,
 407         .recalc_rate = clk_rcg2_recalc_rate,
 408         .set_rate = clk_edp_pixel_set_rate,
 409         .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
 410         .determine_rate = clk_edp_pixel_determine_rate,
 411 };
 412 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
 413
 414 static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
 415                          unsigned long *p_rate, struct clk_hw **p_hw)
 416 {
 417         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 418         const struct freq_tbl *f = rcg->freq_tbl;
 419         unsigned long parent_rate, div;
 420         u32 mask = BIT(rcg->hid_width) - 1;
 421         struct clk *p;
 422
 423         if (rate == 0)
 424                 return -EINVAL;
 425
 426         p = clk_get_parent_by_index(hw->clk, f->src);
 427         *p_hw = __clk_get_hw(p);
 428         *p_rate = parent_rate = __clk_round_rate(p, rate);
 429
 430         div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
 431         div = min_t(u32, div, mask);
 432
 433         return calc_rate(parent_rate, 0, 0, 0, div);
 434 }
 435
 436 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
 437                          unsigned long parent_rate)
 438 {
 439         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 440         struct freq_tbl f = *rcg->freq_tbl;
 441         unsigned long div;
 442         u32 mask = BIT(rcg->hid_width) - 1;
 443
 444         div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
 445         div = min_t(u32, div, mask);
 446
 447         f.pre_div = div;
 448
 449         return clk_rcg2_configure(rcg, &f);
 450 }
 451
 452 static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
 453                 unsigned long rate, unsigned long parent_rate, u8 index)
 454 {
 455         /* Parent index is set statically in frequency table */
 456         return clk_byte_set_rate(hw, rate, parent_rate);
 457 }
 458
 459 const struct clk_ops clk_byte_ops = {
 460         .is_enabled = clk_rcg2_is_enabled,
 461         .get_parent = clk_rcg2_get_parent,
 462         .set_parent = clk_rcg2_set_parent,
 463         .recalc_rate = clk_rcg2_recalc_rate,
 464         .set_rate = clk_byte_set_rate,
 465         .set_rate_and_parent = clk_byte_set_rate_and_parent,
 466         .determine_rate = clk_byte_determine_rate,
 467 };
 468 EXPORT_SYMBOL_GPL(clk_byte_ops);
 469
 470 static const struct frac_entry frac_table_pixel[] = {
 471         { 3, 8 },
 472         { 2, 9 },
 473         { 4, 9 },
 474         { 1, 1 },
 475         { }
 476 };
 477
 478 static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
 479                                  unsigned long *p_rate, struct clk_hw **p)
 480 {
 481         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 482         unsigned long request, src_rate;
 483         int delta = 100000;
 484         const struct freq_tbl *f = rcg->freq_tbl;
 485         const struct frac_entry *frac = frac_table_pixel;
 486         struct clk *parent = clk_get_parent_by_index(hw->clk, f->src);
 487
 488         *p = __clk_get_hw(parent);
 489
 490         for (; frac->num; frac++) {
 491                 request = (rate * frac->den) / frac->num;
 492
 493                 src_rate = __clk_round_rate(parent, request);
 494                 if ((src_rate < (request - delta)) ||
 495                         (src_rate > (request + delta)))
 496                         continue;
 497
 498                 *p_rate = src_rate;
 499                 return (src_rate * frac->num) / frac->den;
 500         }
 501
 502         return -EINVAL;
 503 }
 504
 505 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 506                 unsigned long parent_rate)
 507 {
 508         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 509         struct freq_tbl f = *rcg->freq_tbl;
 510         const struct frac_entry *frac = frac_table_pixel;
 511         unsigned long request, src_rate;
 512         int delta = 100000;
 513         u32 mask = BIT(rcg->hid_width) - 1;
 514         u32 hid_div;
 515         struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
 516
 517         for (; frac->num; frac++) {
 518                 request = (rate * frac->den) / frac->num;
 519
 520                 src_rate = __clk_round_rate(parent, request);
 521                 if ((src_rate < (request - delta)) ||
 522                         (src_rate > (request + delta)))
 523                         continue;
 524
 525                 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
 526                                 &hid_div);
 527                 f.pre_div = hid_div;
 528                 f.pre_div >>= CFG_SRC_DIV_SHIFT;
 529                 f.pre_div &= mask;
 530                 f.m = frac->num;
 531                 f.n = frac->den;
 532
 533                 return clk_rcg2_configure(rcg, &f);
 534         }
 535         return -EINVAL;
 536 }
 537
 538 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
 539                 unsigned long parent_rate, u8 index)
 540 {
 541         /* Parent index is set statically in frequency table */
 542         return clk_pixel_set_rate(hw, rate, parent_rate);
 543 }
 544
 545 const struct clk_ops clk_pixel_ops = {
 546         .is_enabled = clk_rcg2_is_enabled,
 547         .get_parent = clk_rcg2_get_parent,
 548         .set_parent = clk_rcg2_set_parent,
 549         .recalc_rate = clk_rcg2_recalc_rate,
 550         .set_rate = clk_pixel_set_rate,
 551         .set_rate_and_parent = clk_pixel_set_rate_and_parent,
 552         .determine_rate = clk_pixel_determine_rate,
 553 };
 554 EXPORT_SYMBOL_GPL(clk_pixel_ops);