drivers/clk/samsung/clk-s5pv210.c

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
   4  *
   5  * Based on clock drivers for S3C64xx and Exynos4 SoCs.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/syscore_ops.h>
  20
  21 #include "clk.h"
  22 #include "clk-pll.h"
  23
  24 #include <dt-bindings/clock/s5pv210.h>
  25
  26 /* S5PC110/S5PV210 clock controller register offsets */
  27 #define APLL_LOCK               0x0000
  28 #define MPLL_LOCK               0x0008
  29 #define EPLL_LOCK               0x0010
  30 #define VPLL_LOCK               0x0020
  31 #define APLL_CON0               0x0100
  32 #define APLL_CON1               0x0104
  33 #define MPLL_CON                0x0108
  34 #define EPLL_CON0               0x0110
  35 #define EPLL_CON1               0x0114
  36 #define VPLL_CON                0x0120
  37 #define CLK_SRC0                0x0200
  38 #define CLK_SRC1                0x0204
  39 #define CLK_SRC2                0x0208
  40 #define CLK_SRC3                0x020c
  41 #define CLK_SRC4                0x0210
  42 #define CLK_SRC5                0x0214
  43 #define CLK_SRC6                0x0218
  44 #define CLK_SRC_MASK0           0x0280
  45 #define CLK_SRC_MASK1           0x0284
  46 #define CLK_DIV0                0x0300
  47 #define CLK_DIV1                0x0304
  48 #define CLK_DIV2                0x0308
  49 #define CLK_DIV3                0x030c
  50 #define CLK_DIV4                0x0310
  51 #define CLK_DIV5                0x0314
  52 #define CLK_DIV6                0x0318
  53 #define CLK_DIV7                0x031c
  54 #define CLK_GATE_MAIN0          0x0400
  55 #define CLK_GATE_MAIN1          0x0404
  56 #define CLK_GATE_MAIN2          0x0408
  57 #define CLK_GATE_PERI0          0x0420
  58 #define CLK_GATE_PERI1          0x0424
  59 #define CLK_GATE_SCLK0          0x0440
  60 #define CLK_GATE_SCLK1          0x0444
  61 #define CLK_GATE_IP0            0x0460
  62 #define CLK_GATE_IP1            0x0464
  63 #define CLK_GATE_IP2            0x0468
  64 #define CLK_GATE_IP3            0x046c
  65 #define CLK_GATE_IP4            0x0470
  66 #define CLK_GATE_BLOCK          0x0480
  67 #define CLK_GATE_IP5            0x0484
  68 #define CLK_OUT                 0x0500
  69 #define MISC                    0xe000
  70 #define OM_STAT                 0xe100
  71
  72 /* IDs of PLLs available on S5PV210/S5P6442 SoCs */
  73 enum {
  74         apll,
  75         mpll,
  76         epll,
  77         vpll,
  78 };
  79
  80 /* IDs of external clocks (used for legacy boards) */
  81 enum {
  82         xxti,
  83         xusbxti,
  84 };
  85
  86 static void __iomem *reg_base;
  87
  88 #ifdef CONFIG_PM_SLEEP
  89 static struct samsung_clk_reg_dump *s5pv210_clk_dump;
  90
  91 /* List of registers that need to be preserved across suspend/resume. */
  92 static unsigned long s5pv210_clk_regs[] __initdata = {
  93         CLK_SRC0,
  94         CLK_SRC1,
  95         CLK_SRC2,
  96         CLK_SRC3,
  97         CLK_SRC4,
  98         CLK_SRC5,
  99         CLK_SRC6,
 100         CLK_SRC_MASK0,
 101         CLK_SRC_MASK1,
 102         CLK_DIV0,
 103         CLK_DIV1,
 104         CLK_DIV2,
 105         CLK_DIV3,
 106         CLK_DIV4,
 107         CLK_DIV5,
 108         CLK_DIV6,
 109         CLK_DIV7,
 110         CLK_GATE_MAIN0,
 111         CLK_GATE_MAIN1,
 112         CLK_GATE_MAIN2,
 113         CLK_GATE_PERI0,
 114         CLK_GATE_PERI1,
 115         CLK_GATE_SCLK0,
 116         CLK_GATE_SCLK1,
 117         CLK_GATE_IP0,
 118         CLK_GATE_IP1,
 119         CLK_GATE_IP2,
 120         CLK_GATE_IP3,
 121         CLK_GATE_IP4,
 122         CLK_GATE_IP5,
 123         CLK_GATE_BLOCK,
 124         APLL_LOCK,
 125         MPLL_LOCK,
 126         EPLL_LOCK,
 127         VPLL_LOCK,
 128         APLL_CON0,
 129         APLL_CON1,
 130         MPLL_CON,
 131         EPLL_CON0,
 132         EPLL_CON1,
 133         VPLL_CON,
 134         CLK_OUT,
 135 };
 136
 137 static int s5pv210_clk_suspend(void)
 138 {
 139         samsung_clk_save(reg_base, s5pv210_clk_dump,
 140                                 ARRAY_SIZE(s5pv210_clk_regs));
 141         return 0;
 142 }
 143
 144 static void s5pv210_clk_resume(void)
 145 {
 146         samsung_clk_restore(reg_base, s5pv210_clk_dump,
 147                                 ARRAY_SIZE(s5pv210_clk_regs));
 148 }
 149
 150 static struct syscore_ops s5pv210_clk_syscore_ops = {
 151         .suspend = s5pv210_clk_suspend,
 152         .resume = s5pv210_clk_resume,
 153 };
 154
 155 static void s5pv210_clk_sleep_init(void)
 156 {
 157         s5pv210_clk_dump =
 158                 samsung_clk_alloc_reg_dump(s5pv210_clk_regs,
 159                                            ARRAY_SIZE(s5pv210_clk_regs));
 160         if (!s5pv210_clk_dump) {
 161                 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
 162                 return;
 163         }
 164
 165         register_syscore_ops(&s5pv210_clk_syscore_ops);
 166 }
 167 #else
 168 static inline void s5pv210_clk_sleep_init(void) { }
 169 #endif
 170
 171 /* Mux parent lists. */
 172 static const char *fin_pll_p[] __initconst = {
 173         "xxti",
 174         "xusbxti"
 175 };
 176
 177 static const char *mout_apll_p[] __initconst = {
 178         "fin_pll",
 179         "fout_apll"
 180 };
 181
 182 static const char *mout_mpll_p[] __initconst = {
 183         "fin_pll",
 184         "fout_mpll"
 185 };
 186
 187 static const char *mout_epll_p[] __initconst = {
 188         "fin_pll",
 189         "fout_epll"
 190 };
 191
 192 static const char *mout_vpllsrc_p[] __initconst = {
 193         "fin_pll",
 194         "sclk_hdmi27m"
 195 };
 196
 197 static const char *mout_vpll_p[] __initconst = {
 198         "mout_vpllsrc",
 199         "fout_vpll"
 200 };
 201
 202 static const char *mout_group1_p[] __initconst = {
 203         "dout_a2m",
 204         "mout_mpll",
 205         "mout_epll",
 206         "mout_vpll"
 207 };
 208
 209 static const char *mout_group2_p[] __initconst = {
 210         "xxti",
 211         "xusbxti",
 212         "sclk_hdmi27m",
 213         "sclk_usbphy0",
 214         "sclk_usbphy1",
 215         "sclk_hdmiphy",
 216         "mout_mpll",
 217         "mout_epll",
 218         "mout_vpll",
 219 };
 220
 221 static const char *mout_audio0_p[] __initconst = {
 222         "xxti",
 223         "pcmcdclk0",
 224         "sclk_hdmi27m",
 225         "sclk_usbphy0",
 226         "sclk_usbphy1",
 227         "sclk_hdmiphy",
 228         "mout_mpll",
 229         "mout_epll",
 230         "mout_vpll",
 231 };
 232
 233 static const char *mout_audio1_p[] __initconst = {
 234         "i2scdclk1",
 235         "pcmcdclk1",
 236         "sclk_hdmi27m",
 237         "sclk_usbphy0",
 238         "sclk_usbphy1",
 239         "sclk_hdmiphy",
 240         "mout_mpll",
 241         "mout_epll",
 242         "mout_vpll",
 243 };
 244
 245 static const char *mout_audio2_p[] __initconst = {
 246         "i2scdclk2",
 247         "pcmcdclk2",
 248         "sclk_hdmi27m",
 249         "sclk_usbphy0",
 250         "sclk_usbphy1",
 251         "sclk_hdmiphy",
 252         "mout_mpll",
 253         "mout_epll",
 254         "mout_vpll",
 255 };
 256
 257 static const char *mout_spdif_p[] __initconst = {
 258         "dout_audio0",
 259         "dout_audio1",
 260         "dout_audio3",
 261 };
 262
 263 static const char *mout_group3_p[] __initconst = {
 264         "mout_apll",
 265         "mout_mpll"
 266 };
 267
 268 static const char *mout_group4_p[] __initconst = {
 269         "mout_mpll",
 270         "dout_a2m"
 271 };
 272
 273 static const char *mout_flash_p[] __initconst = {
 274         "dout_hclkd",
 275         "dout_hclkp"
 276 };
 277
 278 static const char *mout_dac_p[] __initconst = {
 279         "mout_vpll",
 280         "sclk_hdmiphy"
 281 };
 282
 283 static const char *mout_hdmi_p[] __initconst = {
 284         "sclk_hdmiphy",
 285         "dout_tblk"
 286 };
 287
 288 static const char *mout_mixer_p[] __initconst = {
 289         "mout_dac",
 290         "mout_hdmi"
 291 };
 292
 293 static const char *mout_vpll_6442_p[] __initconst = {
 294         "fin_pll",
 295         "fout_vpll"
 296 };
 297
 298 static const char *mout_mixer_6442_p[] __initconst = {
 299         "mout_vpll",
 300         "dout_mixer"
 301 };
 302
 303 static const char *mout_d0sync_6442_p[] __initconst = {
 304         "mout_dsys",
 305         "div_apll"
 306 };
 307
 308 static const char *mout_d1sync_6442_p[] __initconst = {
 309         "mout_psys",
 310         "div_apll"
 311 };
 312
 313 static const char *mout_group2_6442_p[] __initconst = {
 314         "fin_pll",
 315         "none",
 316         "none",
 317         "sclk_usbphy0",
 318         "none",
 319         "none",
 320         "mout_mpll",
 321         "mout_epll",
 322         "mout_vpll",
 323 };
 324
 325 static const char *mout_audio0_6442_p[] __initconst = {
 326         "fin_pll",
 327         "pcmcdclk0",
 328         "none",
 329         "sclk_usbphy0",
 330         "none",
 331         "none",
 332         "mout_mpll",
 333         "mout_epll",
 334         "mout_vpll",
 335 };
 336
 337 static const char *mout_audio1_6442_p[] __initconst = {
 338         "i2scdclk1",
 339         "pcmcdclk1",
 340         "none",
 341         "sclk_usbphy0",
 342         "none",
 343         "none",
 344         "mout_mpll",
 345         "mout_epll",
 346         "mout_vpll",
 347         "fin_pll",
 348 };
 349
 350 static const char *mout_clksel_p[] __initconst = {
 351         "fout_apll_clkout",
 352         "fout_mpll_clkout",
 353         "fout_epll",
 354         "fout_vpll",
 355         "sclk_usbphy0",
 356         "sclk_usbphy1",
 357         "sclk_hdmiphy",
 358         "rtc",
 359         "rtc_tick",
 360         "dout_hclkm",
 361         "dout_pclkm",
 362         "dout_hclkd",
 363         "dout_pclkd",
 364         "dout_hclkp",
 365         "dout_pclkp",
 366         "dout_apll_clkout",
 367         "dout_hpm",
 368         "xxti",
 369         "xusbxti",
 370         "div_dclk"
 371 };
 372
 373 static const char *mout_clksel_6442_p[] __initconst = {
 374         "fout_apll_clkout",
 375         "fout_mpll_clkout",
 376         "fout_epll",
 377         "fout_vpll",
 378         "sclk_usbphy0",
 379         "none",
 380         "none",
 381         "rtc",
 382         "rtc_tick",
 383         "none",
 384         "none",
 385         "dout_hclkd",
 386         "dout_pclkd",
 387         "dout_hclkp",
 388         "dout_pclkp",
 389         "dout_apll_clkout",
 390         "none",
 391         "fin_pll",
 392         "none",
 393         "div_dclk"
 394 };
 395
 396 static const char *mout_clkout_p[] __initconst = {
 397         "dout_clkout",
 398         "none",
 399         "xxti",
 400         "xusbxti"
 401 };
 402
 403 /* Common fixed factor clocks. */
 404 static struct samsung_fixed_factor_clock ffactor_clks[] __initdata = {
 405         FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0),
 406         FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0),
 407         FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0),
 408 };
 409
 410 /* PLL input mux (fin_pll), which needs to be registered before PLLs. */
 411 static struct samsung_mux_clock early_mux_clks[] __initdata = {
 412         MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1,
 413                                         CLK_MUX_READ_ONLY, 0),
 414 };
 415
 416 /* Common clock muxes. */
 417 static struct samsung_mux_clock mux_clks[] __initdata = {
 418         MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
 419         MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
 420         MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
 421         MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1),
 422         MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
 423         MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
 424         MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
 425
 426         MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
 427 };
 428
 429 /* S5PV210-specific clock muxes. */
 430 static struct samsung_mux_clock s5pv210_mux_clks[] __initdata = {
 431         MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
 432
 433         MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
 434         MUX(MOUT_CSIS, "mout_csis", mout_group2_p, CLK_SRC1, 24, 4),
 435         MUX(MOUT_FIMD, "mout_fimd", mout_group2_p, CLK_SRC1, 20, 4),
 436         MUX(MOUT_CAM1, "mout_cam1", mout_group2_p, CLK_SRC1, 16, 4),
 437         MUX(MOUT_CAM0, "mout_cam0", mout_group2_p, CLK_SRC1, 12, 4),
 438         MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1),
 439         MUX(MOUT_MIXER, "mout_mixer", mout_mixer_p, CLK_SRC1, 4, 1),
 440         MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1),
 441
 442         MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2),
 443         MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2),
 444         MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2),
 445
 446         MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_p, CLK_SRC3, 20, 4),
 447         MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_p, CLK_SRC3, 16, 4),
 448         MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_p, CLK_SRC3, 12, 4),
 449
 450         MUX(MOUT_UART3, "mout_uart3", mout_group2_p, CLK_SRC4, 28, 4),
 451         MUX(MOUT_UART2, "mout_uart2", mout_group2_p, CLK_SRC4, 24, 4),
 452         MUX(MOUT_UART1, "mout_uart1", mout_group2_p, CLK_SRC4, 20, 4),
 453         MUX(MOUT_UART0, "mout_uart0", mout_group2_p, CLK_SRC4, 16, 4),
 454         MUX(MOUT_MMC3, "mout_mmc3", mout_group2_p, CLK_SRC4, 12, 4),
 455         MUX(MOUT_MMC2, "mout_mmc2", mout_group2_p, CLK_SRC4, 8, 4),
 456         MUX(MOUT_MMC1, "mout_mmc1", mout_group2_p, CLK_SRC4, 4, 4),
 457         MUX(MOUT_MMC0, "mout_mmc0", mout_group2_p, CLK_SRC4, 0, 4),
 458
 459         MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4),
 460         MUX(MOUT_SPI1, "mout_spi1", mout_group2_p, CLK_SRC5, 4, 4),
 461         MUX(MOUT_SPI0, "mout_spi0", mout_group2_p, CLK_SRC5, 0, 4),
 462
 463         MUX(MOUT_DMC0, "mout_dmc0", mout_group1_p, CLK_SRC6, 24, 2),
 464         MUX(MOUT_PWI, "mout_pwi", mout_group2_p, CLK_SRC6, 20, 4),
 465         MUX(MOUT_HPM, "mout_hpm", mout_group3_p, CLK_SRC6, 16, 1),
 466         MUX(MOUT_SPDIF, "mout_spdif", mout_spdif_p, CLK_SRC6, 12, 2),
 467         MUX(MOUT_AUDIO2, "mout_audio2", mout_audio2_p, CLK_SRC6, 8, 4),
 468         MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_p, CLK_SRC6, 4, 4),
 469         MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_p, CLK_SRC6, 0, 4),
 470
 471         MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_p, CLK_OUT, 12, 5),
 472 };
 473
 474 /* S5P6442-specific clock muxes. */
 475 static struct samsung_mux_clock s5p6442_mux_clks[] __initdata = {
 476         MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1),
 477
 478         MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4),
 479         MUX(MOUT_CAM1, "mout_cam1", mout_group2_6442_p, CLK_SRC1, 16, 4),
 480         MUX(MOUT_CAM0, "mout_cam0", mout_group2_6442_p, CLK_SRC1, 12, 4),
 481         MUX(MOUT_MIXER, "mout_mixer", mout_mixer_6442_p, CLK_SRC1, 4, 1),
 482
 483         MUX(MOUT_D0SYNC, "mout_d0sync", mout_d0sync_6442_p, CLK_SRC2, 28, 1),
 484         MUX(MOUT_D1SYNC, "mout_d1sync", mout_d1sync_6442_p, CLK_SRC2, 24, 1),
 485
 486         MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_6442_p, CLK_SRC3, 20, 4),
 487         MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_6442_p, CLK_SRC3, 16, 4),
 488         MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_6442_p, CLK_SRC3, 12, 4),
 489
 490         MUX(MOUT_UART2, "mout_uart2", mout_group2_6442_p, CLK_SRC4, 24, 4),
 491         MUX(MOUT_UART1, "mout_uart1", mout_group2_6442_p, CLK_SRC4, 20, 4),
 492         MUX(MOUT_UART0, "mout_uart0", mout_group2_6442_p, CLK_SRC4, 16, 4),
 493         MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4),
 494         MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4),
 495         MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4),
 496
 497         MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4),
 498         MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4),
 499
 500         MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4),
 501         MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4),
 502
 503         MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5),
 504 };
 505
 506 /* S5PV210-specific fixed rate clocks generated inside the SoC. */
 507 static struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initdata = {
 508         FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
 509         FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
 510         FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
 511         FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
 512 };
 513
 514 /* S5P6442-specific fixed rate clocks generated inside the SoC. */
 515 static struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initdata = {
 516         FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 30000000),
 517 };
 518
 519 /* Common clock dividers. */
 520 static struct samsung_div_clock div_clks[] __initdata = {
 521         DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3),
 522         DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3),
 523         DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3),
 524         DIV(DOUT_APLL, "dout_apll", "mout_msys", CLK_DIV0, 0, 3),
 525
 526         DIV(DOUT_FIMD, "dout_fimd", "mout_fimd", CLK_DIV1, 20, 4),
 527         DIV(DOUT_CAM1, "dout_cam1", "mout_cam1", CLK_DIV1, 16, 4),
 528         DIV(DOUT_CAM0, "dout_cam0", "mout_cam0", CLK_DIV1, 12, 4),
 529
 530         DIV(DOUT_FIMC2, "dout_fimc2", "mout_fimc2", CLK_DIV3, 20, 4),
 531         DIV(DOUT_FIMC1, "dout_fimc1", "mout_fimc1", CLK_DIV3, 16, 4),
 532         DIV(DOUT_FIMC0, "dout_fimc0", "mout_fimc0", CLK_DIV3, 12, 4),
 533
 534         DIV(DOUT_UART2, "dout_uart2", "mout_uart2", CLK_DIV4, 24, 4),
 535         DIV(DOUT_UART1, "dout_uart1", "mout_uart1", CLK_DIV4, 20, 4),
 536         DIV(DOUT_UART0, "dout_uart0", "mout_uart0", CLK_DIV4, 16, 4),
 537         DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV4, 8, 4),
 538         DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV4, 4, 4),
 539         DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV4, 0, 4),
 540
 541         DIV(DOUT_PWM, "dout_pwm", "mout_pwm", CLK_DIV5, 12, 4),
 542         DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV5, 0, 4),
 543
 544         DIV(DOUT_FLASH, "dout_flash", "mout_flash", CLK_DIV6, 12, 3),
 545         DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV6, 4, 4),
 546         DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV6, 0, 4),
 547
 548         DIV(DOUT_CLKOUT, "dout_clkout", "mout_clksel", CLK_OUT, 20, 4),
 549 };
 550
 551 /* S5PV210-specific clock dividers. */
 552 static struct samsung_div_clock s5pv210_div_clks[] __initdata = {
 553         DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4),
 554         DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4),
 555         DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3),
 556         DIV(DOUT_HCLKM, "dout_hclkm", "dout_apll", CLK_DIV0, 8, 3),
 557
 558         DIV(DOUT_CSIS, "dout_csis", "mout_csis", CLK_DIV1, 28, 4),
 559         DIV(DOUT_TBLK, "dout_tblk", "mout_vpll", CLK_DIV1, 0, 4),
 560
 561         DIV(DOUT_G2D, "dout_g2d", "mout_g2d", CLK_DIV2, 8, 4),
 562         DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV2, 4, 4),
 563         DIV(DOUT_G3D, "dout_g3d", "mout_g3d", CLK_DIV2, 0, 4),
 564
 565         DIV(DOUT_UART3, "dout_uart3", "mout_uart3", CLK_DIV4, 28, 4),
 566         DIV(DOUT_MMC3, "dout_mmc3", "mout_mmc3", CLK_DIV4, 12, 4),
 567
 568         DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV5, 4, 4),
 569
 570         DIV(DOUT_DMC0, "dout_dmc0", "mout_dmc0", CLK_DIV6, 28, 4),
 571         DIV(DOUT_PWI, "dout_pwi", "mout_pwi", CLK_DIV6, 24, 4),
 572         DIV(DOUT_HPM, "dout_hpm", "dout_copy", CLK_DIV6, 20, 3),
 573         DIV(DOUT_COPY, "dout_copy", "mout_hpm", CLK_DIV6, 16, 3),
 574         DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV6, 8, 4),
 575
 576         DIV(DOUT_DPM, "dout_dpm", "dout_pclkp", CLK_DIV7, 8, 7),
 577         DIV(DOUT_DVSEM, "dout_dvsem", "dout_pclkp", CLK_DIV7, 0, 7),
 578 };
 579
 580 /* S5P6442-specific clock dividers. */
 581 static struct samsung_div_clock s5p6442_div_clks[] __initdata = {
 582         DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4),
 583         DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4),
 584
 585         DIV(DOUT_MIXER, "dout_mixer", "mout_vpll", CLK_DIV1, 0, 4),
 586 };
 587
 588 /* Common clock gates. */
 589 static struct samsung_gate_clock gate_clks[] __initdata = {
 590         GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0),
 591         GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0),
 592         GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0),
 593         GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0),
 594         GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
 595         GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0),
 596
 597         GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0),
 598         GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0),
 599         GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0),
 600         GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0),
 601         GATE(CLK_MIXER, "mixer", "dout_hclkd", CLK_GATE_IP1, 9, 0, 0),
 602         GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0),
 603         GATE(CLK_FIMD, "fimd", "dout_hclkd", CLK_GATE_IP1, 0, 0, 0),
 604
 605         GATE(CLK_HSMMC2, "hsmmc2", "dout_hclkp", CLK_GATE_IP2, 18, 0, 0),
 606         GATE(CLK_HSMMC1, "hsmmc1", "dout_hclkp", CLK_GATE_IP2, 17, 0, 0),
 607         GATE(CLK_HSMMC0, "hsmmc0", "dout_hclkp", CLK_GATE_IP2, 16, 0, 0),
 608         GATE(CLK_MODEMIF, "modemif", "dout_hclkp", CLK_GATE_IP2, 9, 0, 0),
 609         GATE(CLK_SECSS, "secss", "dout_hclkp", CLK_GATE_IP2, 0, 0, 0),
 610
 611         GATE(CLK_PCM1, "pcm1", "dout_pclkp", CLK_GATE_IP3, 29, 0, 0),
 612         GATE(CLK_PCM0, "pcm0", "dout_pclkp", CLK_GATE_IP3, 28, 0, 0),
 613         GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0),
 614         GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
 615         GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0),
 616         GATE(CLK_KEYIF, "keyif", "dout_pclkp", CLK_GATE_IP3, 21, 0, 0),
 617         GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
 618         GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
 619         GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
 620         GATE(CLK_SYSTIMER, "systimer", "dout_pclkp", CLK_GATE_IP3, 16, 0, 0),
 621         GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0),
 622         GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0),
 623         GATE(CLK_I2C2, "i2c2", "dout_pclkp", CLK_GATE_IP3, 9, 0, 0),
 624         GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0),
 625         GATE(CLK_I2S1, "i2s1", "dout_pclkp", CLK_GATE_IP3, 5, 0, 0),
 626         GATE(CLK_I2S0, "i2s0", "dout_pclkp", CLK_GATE_IP3, 4, 0, 0),
 627
 628         GATE(CLK_SECKEY, "seckey", "dout_pclkp", CLK_GATE_IP4, 3, 0, 0),
 629         GATE(CLK_CHIPID, "chipid", "dout_pclkp", CLK_GATE_IP4, 0, 0, 0),
 630
 631         GATE(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", CLK_SRC_MASK0, 25,
 632                         CLK_SET_RATE_PARENT, 0),
 633         GATE(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", CLK_SRC_MASK0, 24,
 634                         CLK_SET_RATE_PARENT, 0),
 635         GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
 636                         CLK_SET_RATE_PARENT, 0),
 637         GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16,
 638                         CLK_SET_RATE_PARENT, 0),
 639         GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,
 640                         CLK_SET_RATE_PARENT, 0),
 641         GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
 642                         CLK_SET_RATE_PARENT, 0),
 643         GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
 644                         CLK_SET_RATE_PARENT, 0),
 645         GATE(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", CLK_SRC_MASK0, 10,
 646                         CLK_SET_RATE_PARENT, 0),
 647         GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9,
 648                         CLK_SET_RATE_PARENT, 0),
 649         GATE(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", CLK_SRC_MASK0, 8,
 650                         CLK_SET_RATE_PARENT, 0),
 651         GATE(SCLK_FIMD, "sclk_fimd", "dout_fimd", CLK_SRC_MASK0, 5,
 652                         CLK_SET_RATE_PARENT, 0),
 653         GATE(SCLK_CAM1, "sclk_cam1", "dout_cam1", CLK_SRC_MASK0, 4,
 654                         CLK_SET_RATE_PARENT, 0),
 655         GATE(SCLK_CAM0, "sclk_cam0", "dout_cam0", CLK_SRC_MASK0, 3,
 656                         CLK_SET_RATE_PARENT, 0),
 657         GATE(SCLK_MIXER, "sclk_mixer", "mout_mixer", CLK_SRC_MASK0, 1,
 658                         CLK_SET_RATE_PARENT, 0),
 659
 660         GATE(SCLK_FIMC2, "sclk_fimc2", "dout_fimc2", CLK_SRC_MASK1, 4,
 661                         CLK_SET_RATE_PARENT, 0),
 662         GATE(SCLK_FIMC1, "sclk_fimc1", "dout_fimc1", CLK_SRC_MASK1, 3,
 663                         CLK_SET_RATE_PARENT, 0),
 664         GATE(SCLK_FIMC0, "sclk_fimc0", "dout_fimc0", CLK_SRC_MASK1, 2,
 665                         CLK_SET_RATE_PARENT, 0),
 666 };
 667
 668 /* S5PV210-specific clock gates. */
 669 static struct samsung_gate_clock s5pv210_gate_clks[] __initdata = {
 670         GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0),
 671         GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0),
 672         GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
 673         GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
 674         GATE(CLK_IMEM, "imem", "dout_hclkm", CLK_GATE_IP0, 5, 0, 0),
 675         GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
 676
 677         GATE(CLK_NFCON, "nfcon", "dout_hclkp", CLK_GATE_IP1, 28, 0, 0),
 678         GATE(CLK_CFCON, "cfcon", "dout_hclkp", CLK_GATE_IP1, 25, 0, 0),
 679         GATE(CLK_USB_HOST, "usb_host", "dout_hclkp", CLK_GATE_IP1, 17, 0, 0),
 680         GATE(CLK_HDMI, "hdmi", "dout_hclkd", CLK_GATE_IP1, 11, 0, 0),
 681         GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0),
 682
 683         GATE(CLK_TZIC3, "tzic3", "dout_hclkm", CLK_GATE_IP2, 31, 0, 0),
 684         GATE(CLK_TZIC2, "tzic2", "dout_hclkm", CLK_GATE_IP2, 30, 0, 0),
 685         GATE(CLK_TZIC1, "tzic1", "dout_hclkm", CLK_GATE_IP2, 29, 0, 0),
 686         GATE(CLK_TZIC0, "tzic0", "dout_hclkm", CLK_GATE_IP2, 28, 0, 0),
 687         GATE(CLK_TSI, "tsi", "dout_hclkd", CLK_GATE_IP2, 20, 0, 0),
 688         GATE(CLK_HSMMC3, "hsmmc3", "dout_hclkp", CLK_GATE_IP2, 19, 0, 0),
 689         GATE(CLK_JTAG, "jtag", "dout_hclkp", CLK_GATE_IP2, 11, 0, 0),
 690         GATE(CLK_CORESIGHT, "coresight", "dout_pclkp", CLK_GATE_IP2, 8, 0, 0),
 691         GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0),
 692
 693         GATE(CLK_PCM2, "pcm2", "dout_pclkp", CLK_GATE_IP3, 30, 0, 0),
 694         GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0),
 695         GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0),
 696         GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd",
 697                         CLK_GATE_IP3, 11, 0, 0),
 698         GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0),
 699         GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0),
 700         GATE(CLK_AC97, "ac97", "dout_pclkp", CLK_GATE_IP3, 1, 0, 0),
 701         GATE(CLK_SPDIF, "spdif", "dout_pclkp", CLK_GATE_IP3, 0, 0, 0),
 702
 703         GATE(CLK_TZPC3, "tzpc.3", "dout_pclkd", CLK_GATE_IP4, 8, 0, 0),
 704         GATE(CLK_TZPC2, "tzpc.2", "dout_pclkd", CLK_GATE_IP4, 7, 0, 0),
 705         GATE(CLK_TZPC1, "tzpc.1", "dout_pclkp", CLK_GATE_IP4, 6, 0, 0),
 706         GATE(CLK_TZPC0, "tzpc.0", "dout_pclkm", CLK_GATE_IP4, 5, 0, 0),
 707         GATE(CLK_IEM_APC, "iem_apc", "dout_pclkp", CLK_GATE_IP4, 2, 0, 0),
 708         GATE(CLK_IEM_IEC, "iem_iec", "dout_pclkp", CLK_GATE_IP4, 1, 0, 0),
 709
 710         GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP5, 29, 0, 0),
 711
 712         GATE(SCLK_SPDIF, "sclk_spdif", "mout_spdif", CLK_SRC_MASK0, 27,
 713                         CLK_SET_RATE_PARENT, 0),
 714         GATE(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", CLK_SRC_MASK0, 26,
 715                         CLK_SET_RATE_PARENT, 0),
 716         GATE(SCLK_SPI1, "sclk_spi1", "dout_spi1", CLK_SRC_MASK0, 17,
 717                         CLK_SET_RATE_PARENT, 0),
 718         GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
 719                         CLK_SET_RATE_PARENT, 0),
 720         GATE(SCLK_MMC3, "sclk_mmc3", "dout_mmc3", CLK_SRC_MASK0, 11,
 721                         CLK_SET_RATE_PARENT, 0),
 722         GATE(SCLK_CSIS, "sclk_csis", "dout_csis", CLK_SRC_MASK0, 6,
 723                         CLK_SET_RATE_PARENT, 0),
 724         GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2,
 725                         CLK_SET_RATE_PARENT, 0),
 726         GATE(SCLK_HDMI, "sclk_hdmi", "mout_hdmi", CLK_SRC_MASK0, 0,
 727                         CLK_SET_RATE_PARENT, 0),
 728 };
 729
 730 /* S5P6442-specific clock gates. */
 731 static struct samsung_gate_clock s5p6442_gate_clks[] __initdata = {
 732         GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0),
 733         GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0),
 734         GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
 735         GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
 736         GATE(CLK_IMEM, "imem", "dout_hclkd", CLK_GATE_IP0, 5, 0, 0),
 737
 738         GATE(CLK_ETB, "etb", "dout_hclkd", CLK_GATE_IP1, 31, 0, 0),
 739         GATE(CLK_ETM, "etm", "dout_hclkd", CLK_GATE_IP1, 30, 0, 0),
 740
 741         GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0),
 742
 743         GATE(SCLK_DAC, "sclk_dac", "mout_vpll", CLK_SRC_MASK0, 2,
 744                         CLK_SET_RATE_PARENT, 0),
 745 };
 746
 747 /*
 748  * Clock aliases for legacy clkdev look-up.
 749  * NOTE: Needed only to support legacy board files.
 750  */
 751 static struct samsung_clock_alias s5pv210_aliases[] = {
 752         ALIAS(DOUT_APLL, NULL, "armclk"),
 753         ALIAS(DOUT_HCLKM, NULL, "hclk_msys"),
 754         ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"),
 755 };
 756
 757 /* S5PV210-specific PLLs. */
 758 static struct samsung_pll_clock s5pv210_pll_clks[] __initdata = {
 759         [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
 760                                                 APLL_LOCK, APLL_CON0, NULL),
 761         [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
 762                                                 MPLL_LOCK, MPLL_CON, NULL),
 763         [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
 764                                                 EPLL_LOCK, EPLL_CON0, NULL),
 765         [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
 766                                                 VPLL_LOCK, VPLL_CON, NULL),
 767 };
 768
 769 /* S5P6442-specific PLLs. */
 770 static struct samsung_pll_clock s5p6442_pll_clks[] __initdata = {
 771         [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
 772                                                 APLL_LOCK, APLL_CON0, NULL),
 773         [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
 774                                                 MPLL_LOCK, MPLL_CON, NULL),
 775         [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
 776                                                 EPLL_LOCK, EPLL_CON0, NULL),
 777         [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
 778                                                 VPLL_LOCK, VPLL_CON, NULL),
 779 };
 780
 781 static void __init __s5pv210_clk_init(struct device_node *np,
 782                                       unsigned long xxti_f,
 783                                       unsigned long xusbxti_f,
 784                                       bool is_s5p6442)
 785 {
 786         struct samsung_clk_provider *ctx;
 787
 788         ctx = samsung_clk_init(np, reg_base, NR_CLKS);
 789         if (!ctx)
 790                 panic("%s: unable to allocate context.\n", __func__);
 791
 792         samsung_clk_register_mux(ctx, early_mux_clks,
 793                                         ARRAY_SIZE(early_mux_clks));
 794
 795         if (is_s5p6442) {
 796                 samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks,
 797                         ARRAY_SIZE(s5p6442_frate_clks));
 798                 samsung_clk_register_pll(ctx, s5p6442_pll_clks,
 799                         ARRAY_SIZE(s5p6442_pll_clks), reg_base);
 800                 samsung_clk_register_mux(ctx, s5p6442_mux_clks,
 801                                 ARRAY_SIZE(s5p6442_mux_clks));
 802                 samsung_clk_register_div(ctx, s5p6442_div_clks,
 803                                 ARRAY_SIZE(s5p6442_div_clks));
 804                 samsung_clk_register_gate(ctx, s5p6442_gate_clks,
 805                                 ARRAY_SIZE(s5p6442_gate_clks));
 806         } else {
 807                 samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks,
 808                         ARRAY_SIZE(s5pv210_frate_clks));
 809                 samsung_clk_register_pll(ctx, s5pv210_pll_clks,
 810                         ARRAY_SIZE(s5pv210_pll_clks), reg_base);
 811                 samsung_clk_register_mux(ctx, s5pv210_mux_clks,
 812                                 ARRAY_SIZE(s5pv210_mux_clks));
 813                 samsung_clk_register_div(ctx, s5pv210_div_clks,
 814                                 ARRAY_SIZE(s5pv210_div_clks));
 815                 samsung_clk_register_gate(ctx, s5pv210_gate_clks,
 816                                 ARRAY_SIZE(s5pv210_gate_clks));
 817         }
 818
 819         samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
 820         samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
 821         samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
 822
 823         samsung_clk_register_fixed_factor(ctx, ffactor_clks,
 824                                                 ARRAY_SIZE(ffactor_clks));
 825
 826         samsung_clk_register_alias(ctx, s5pv210_aliases,
 827                                                 ARRAY_SIZE(s5pv210_aliases));
 828
 829         s5pv210_clk_sleep_init();
 830
 831         pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
 832                 "\tmout_epll = %ld, mout_vpll = %ld\n",
 833                 is_s5p6442 ? "S5P6442" : "S5PV210",
 834                 _get_rate("mout_apll"), _get_rate("mout_mpll"),
 835                 _get_rate("mout_epll"), _get_rate("mout_vpll"));
 836 }
 837
 838 static void __init s5pv210_clk_dt_init(struct device_node *np)
 839 {
 840         reg_base = of_iomap(np, 0);
 841         if (!reg_base)
 842                 panic("%s: failed to map registers\n", __func__);
 843
 844         __s5pv210_clk_init(np, 0, 0, false);
 845 }
 846 CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init);
 847
 848 static void __init s5p6442_clk_dt_init(struct device_node *np)
 849 {
 850         reg_base = of_iomap(np, 0);
 851         if (!reg_base)
 852                 panic("%s: failed to map registers\n", __func__);
 853
 854         __s5pv210_clk_init(np, 0, 0, true);
 855 }
 856 CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init);