drivers/clk/shmobile/clk-rcar-gen2.c

   1 /*
   2  * rcar_gen2 Core CPG Clocks
   3  *
   4  * Copyright (C) 2013  Ideas On Board SPRL
   5  *
   6  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  */
  12
  13 #include <linux/clk-provider.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk/shmobile.h>
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/math64.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/spinlock.h>
  22
  23 struct rcar_gen2_cpg {
  24         struct clk_onecell_data data;
  25         spinlock_t lock;
  26         void __iomem *reg;
  27 };
  28
  29 #define CPG_FRQCRB                      0x00000004
  30 #define CPG_FRQCRB_KICK                 BIT(31)
  31 #define CPG_SDCKCR                      0x00000074
  32 #define CPG_PLL0CR                      0x000000d8
  33 #define CPG_FRQCRC                      0x000000e0
  34 #define CPG_FRQCRC_ZFC_MASK             (0x1f << 8)
  35 #define CPG_FRQCRC_ZFC_SHIFT            8
  36
  37 /* -----------------------------------------------------------------------------
  38  * Z Clock
  39  *
  40  * Traits of this clock:
  41  * prepare - clk_prepare only ensures that parents are prepared
  42  * enable - clk_enable only ensures that parents are enabled
  43  * rate - rate is adjustable.  clk->rate = parent->rate * mult / 32
  44  * parent - fixed parent.  No clk_set_parent support
  45  */
  46
  47 struct cpg_z_clk {
  48         struct clk_hw hw;
  49         void __iomem *reg;
  50         void __iomem *kick_reg;
  51 };
  52
  53 #define to_z_clk(_hw)   container_of(_hw, struct cpg_z_clk, hw)
  54
  55 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
  56                                            unsigned long parent_rate)
  57 {
  58         struct cpg_z_clk *zclk = to_z_clk(hw);
  59         unsigned int mult;
  60         unsigned int val;
  61
  62         val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
  63             >> CPG_FRQCRC_ZFC_SHIFT;
  64         mult = 32 - val;
  65
  66         return div_u64((u64)parent_rate * mult, 32);
  67 }
  68
  69 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  70                                  unsigned long *parent_rate)
  71 {
  72         unsigned long prate  = *parent_rate;
  73         unsigned int mult;
  74
  75         if (!prate)
  76                 prate = 1;
  77
  78         mult = div_u64((u64)rate * 32, prate);
  79         mult = clamp(mult, 1U, 32U);
  80
  81         return *parent_rate / 32 * mult;
  82 }
  83
  84 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  85                               unsigned long parent_rate)
  86 {
  87         struct cpg_z_clk *zclk = to_z_clk(hw);
  88         unsigned int mult;
  89         u32 val, kick;
  90         unsigned int i;
  91
  92         mult = div_u64((u64)rate * 32, parent_rate);
  93         mult = clamp(mult, 1U, 32U);
  94
  95         if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
  96                 return -EBUSY;
  97
  98         val = clk_readl(zclk->reg);
  99         val &= ~CPG_FRQCRC_ZFC_MASK;
 100         val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
 101         clk_writel(val, zclk->reg);
 102
 103         /*
 104          * Set KICK bit in FRQCRB to update hardware setting and wait for
 105          * clock change completion.
 106          */
 107         kick = clk_readl(zclk->kick_reg);
 108         kick |= CPG_FRQCRB_KICK;
 109         clk_writel(kick, zclk->kick_reg);
 110
 111         /*
 112          * Note: There is no HW information about the worst case latency.
 113          *
 114          * Using experimental measurements, it seems that no more than
 115          * ~10 iterations are needed, independently of the CPU rate.
 116          * Since this value might be dependant of external xtal rate, pll1
 117          * rate or even the other emulation clocks rate, use 1000 as a
 118          * "super" safe value.
 119          */
 120         for (i = 1000; i; i--) {
 121                 if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
 122                         return 0;
 123
 124                 cpu_relax();
 125         }
 126
 127         return -ETIMEDOUT;
 128 }
 129
 130 static const struct clk_ops cpg_z_clk_ops = {
 131         .recalc_rate = cpg_z_clk_recalc_rate,
 132         .round_rate = cpg_z_clk_round_rate,
 133         .set_rate = cpg_z_clk_set_rate,
 134 };
 135
 136 static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
 137 {
 138         static const char *parent_name = "pll0";
 139         struct clk_init_data init;
 140         struct cpg_z_clk *zclk;
 141         struct clk *clk;
 142
 143         zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
 144         if (!zclk)
 145                 return ERR_PTR(-ENOMEM);
 146
 147         init.name = "z";
 148         init.ops = &cpg_z_clk_ops;
 149         init.flags = 0;
 150         init.parent_names = &parent_name;
 151         init.num_parents = 1;
 152
 153         zclk->reg = cpg->reg + CPG_FRQCRC;
 154         zclk->kick_reg = cpg->reg + CPG_FRQCRB;
 155         zclk->hw.init = &init;
 156
 157         clk = clk_register(NULL, &zclk->hw);
 158         if (IS_ERR(clk))
 159                 kfree(zclk);
 160
 161         return clk;
 162 }
 163
 164 /* -----------------------------------------------------------------------------
 165  * CPG Clock Data
 166  */
 167
 168 /*
 169  *   MD         EXTAL           PLL0    PLL1    PLL3
 170  * 14 13 19     (MHz)           *1      *1
 171  *---------------------------------------------------
 172  * 0  0  0      15 x 1          x172/2  x208/2  x106
 173  * 0  0  1      15 x 1          x172/2  x208/2  x88
 174  * 0  1  0      20 x 1          x130/2  x156/2  x80
 175  * 0  1  1      20 x 1          x130/2  x156/2  x66
 176  * 1  0  0      26 / 2          x200/2  x240/2  x122
 177  * 1  0  1      26 / 2          x200/2  x240/2  x102
 178  * 1  1  0      30 / 2          x172/2  x208/2  x106
 179  * 1  1  1      30 / 2          x172/2  x208/2  x88
 180  *
 181  * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
 182  */
 183 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 12) | \
 184                                          (((md) & BIT(13)) >> 12) | \
 185                                          (((md) & BIT(19)) >> 19))
 186 struct cpg_pll_config {
 187         unsigned int extal_div;
 188         unsigned int pll1_mult;
 189         unsigned int pll3_mult;
 190 };
 191
 192 static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
 193         { 1, 208, 106 }, { 1, 208,  88 }, { 1, 156,  80 }, { 1, 156,  66 },
 194         { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208,  88 },
 195 };
 196
 197 /* SDHI divisors */
 198 static const struct clk_div_table cpg_sdh_div_table[] = {
 199         {  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
 200         {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
 201         {  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
 202 };
 203
 204 static const struct clk_div_table cpg_sd01_div_table[] = {
 205         {  4,  8 },
 206         {  5, 12 }, {  6, 16 }, {  7, 18 }, {  8, 24 },
 207         { 10, 36 }, { 11, 48 }, { 12, 10 }, {  0,  0 },
 208 };
 209
 210 /* -----------------------------------------------------------------------------
 211  * Initialization
 212  */
 213
 214 static u32 cpg_mode __initdata;
 215
 216 static struct clk * __init
 217 rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
 218                              const struct cpg_pll_config *config,
 219                              const char *name)
 220 {
 221         const struct clk_div_table *table = NULL;
 222         const char *parent_name;
 223         unsigned int shift;
 224         unsigned int mult = 1;
 225         unsigned int div = 1;
 226
 227         if (!strcmp(name, "main")) {
 228                 parent_name = of_clk_get_parent_name(np, 0);
 229                 div = config->extal_div;
 230         } else if (!strcmp(name, "pll0")) {
 231                 /* PLL0 is a configurable multiplier clock. Register it as a
 232                  * fixed factor clock for now as there's no generic multiplier
 233                  * clock implementation and we currently have no need to change
 234                  * the multiplier value.
 235                  */
 236                 u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
 237                 parent_name = "main";
 238                 mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
 239         } else if (!strcmp(name, "pll1")) {
 240                 parent_name = "main";
 241                 mult = config->pll1_mult / 2;
 242         } else if (!strcmp(name, "pll3")) {
 243                 parent_name = "main";
 244                 mult = config->pll3_mult;
 245         } else if (!strcmp(name, "lb")) {
 246                 parent_name = "pll1";
 247                 div = cpg_mode & BIT(18) ? 36 : 24;
 248         } else if (!strcmp(name, "qspi")) {
 249                 parent_name = "pll1_div2";
 250                 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
 251                     ? 8 : 10;
 252         } else if (!strcmp(name, "sdh")) {
 253                 parent_name = "pll1";
 254                 table = cpg_sdh_div_table;
 255                 shift = 8;
 256         } else if (!strcmp(name, "sd0")) {
 257                 parent_name = "pll1";
 258                 table = cpg_sd01_div_table;
 259                 shift = 4;
 260         } else if (!strcmp(name, "sd1")) {
 261                 parent_name = "pll1";
 262                 table = cpg_sd01_div_table;
 263                 shift = 0;
 264         } else if (!strcmp(name, "z")) {
 265                 return cpg_z_clk_register(cpg);
 266         } else {
 267                 return ERR_PTR(-EINVAL);
 268         }
 269
 270         if (!table)
 271                 return clk_register_fixed_factor(NULL, name, parent_name, 0,
 272                                                  mult, div);
 273         else
 274                 return clk_register_divider_table(NULL, name, parent_name, 0,
 275                                                  cpg->reg + CPG_SDCKCR, shift,
 276                                                  4, 0, table, &cpg->lock);
 277 }
 278
 279 static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
 280 {
 281         const struct cpg_pll_config *config;
 282         struct rcar_gen2_cpg *cpg;
 283         struct clk **clks;
 284         unsigned int i;
 285         int num_clks;
 286
 287         num_clks = of_property_count_strings(np, "clock-output-names");
 288         if (num_clks < 0) {
 289                 pr_err("%s: failed to count clocks\n", __func__);
 290                 return;
 291         }
 292
 293         cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
 294         clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
 295         if (cpg == NULL || clks == NULL) {
 296                 /* We're leaking memory on purpose, there's no point in cleaning
 297                  * up as the system won't boot anyway.
 298                  */
 299                 pr_err("%s: failed to allocate cpg\n", __func__);
 300                 return;
 301         }
 302
 303         spin_lock_init(&cpg->lock);
 304
 305         cpg->data.clks = clks;
 306         cpg->data.clk_num = num_clks;
 307
 308         cpg->reg = of_iomap(np, 0);
 309         if (WARN_ON(cpg->reg == NULL))
 310                 return;
 311
 312         config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 313
 314         for (i = 0; i < num_clks; ++i) {
 315                 const char *name;
 316                 struct clk *clk;
 317
 318                 of_property_read_string_index(np, "clock-output-names", i,
 319                                               &name);
 320
 321                 clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
 322                 if (IS_ERR(clk))
 323                         pr_err("%s: failed to register %s %s clock (%ld)\n",
 324                                __func__, np->name, name, PTR_ERR(clk));
 325                 else
 326                         cpg->data.clks[i] = clk;
 327         }
 328
 329         of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
 330 }
 331 CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
 332                rcar_gen2_cpg_clocks_init);
 333
 334 void __init rcar_gen2_clocks_init(u32 mode)
 335 {
 336         cpg_mode = mode;
 337
 338         of_clk_init(NULL);
 339 }