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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / clk / spear / spear1340_clock.c
blob5a5c6648308dbc6f8009e6d5702dce3d95572532
1 /*
2 * arch/arm/mach-spear13xx/spear1340_clock.c
3 *
4 * SPEAr1340 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/of_platform.h>
19 #include <linux/spinlock_types.h>
20 #include "clk.h"
21
22 /* Clock Configuration Registers */
23 #define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
24 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
25 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
26 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
27 #define SPEAR1340_SCLK_SRC_SEL_MASK 3
28
29 /* PLL related registers and bit values */
30 #define SPEAR1340_PLL_CFG (misc_base + 0x210)
31 /* PLL_CFG bit values */
32 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
33 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
34 #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
35 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
36 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
37 #define SPEAR1340_PLL_CLK_MASK 2
38 #define SPEAR1340_PLL3_CLK_SHIFT 24
39 #define SPEAR1340_PLL2_CLK_SHIFT 22
40 #define SPEAR1340_PLL1_CLK_SHIFT 20
41
42 #define SPEAR1340_PLL1_CTR (misc_base + 0x214)
43 #define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
44 #define SPEAR1340_PLL2_CTR (misc_base + 0x220)
45 #define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
46 #define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
47 #define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
48 #define SPEAR1340_PLL4_CTR (misc_base + 0x238)
49 #define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
50 #define SPEAR1340_PERIP_CLK_CFG (misc_base + 0x244)
51 /* PERIP_CLK_CFG bit values */
52 #define SPEAR1340_SPDIF_CLK_MASK 1
53 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
54 #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
55 #define SPEAR1340_GPT3_CLK_SHIFT 13
56 #define SPEAR1340_GPT2_CLK_SHIFT 12
57 #define SPEAR1340_GPT_CLK_MASK 1
58 #define SPEAR1340_GPT1_CLK_SHIFT 9
59 #define SPEAR1340_GPT0_CLK_SHIFT 8
60 #define SPEAR1340_UART_CLK_MASK 2
61 #define SPEAR1340_UART1_CLK_SHIFT 6
62 #define SPEAR1340_UART0_CLK_SHIFT 4
63 #define SPEAR1340_CLCD_CLK_MASK 2
64 #define SPEAR1340_CLCD_CLK_SHIFT 2
65 #define SPEAR1340_C3_CLK_MASK 1
66 #define SPEAR1340_C3_CLK_SHIFT 1
67
68 #define SPEAR1340_GMAC_CLK_CFG (misc_base + 0x248)
69 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
70 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
71 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
73
74 #define SPEAR1340_I2S_CLK_CFG (misc_base + 0x24C)
75 /* I2S_CLK_CFG register mask */
76 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
77 #define SPEAR1340_I2S_SCLK_X_SHIFT 27
78 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
79 #define SPEAR1340_I2S_SCLK_Y_SHIFT 22
80 #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
81 #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
82 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
83 #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
84 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
85 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
86 #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
87 #define SPEAR1340_I2S_REF_SEL_MASK 1
88 #define SPEAR1340_I2S_REF_SHIFT 2
89 #define SPEAR1340_I2S_SRC_CLK_MASK 2
90 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
91
92 #define SPEAR1340_C3_CLK_SYNT (misc_base + 0x250)
93 #define SPEAR1340_UART0_CLK_SYNT (misc_base + 0x254)
94 #define SPEAR1340_UART1_CLK_SYNT (misc_base + 0x258)
95 #define SPEAR1340_GMAC_CLK_SYNT (misc_base + 0x25C)
96 #define SPEAR1340_SDHCI_CLK_SYNT (misc_base + 0x260)
97 #define SPEAR1340_CFXD_CLK_SYNT (misc_base + 0x264)
98 #define SPEAR1340_ADC_CLK_SYNT (misc_base + 0x270)
99 #define SPEAR1340_AMBA_CLK_SYNT (misc_base + 0x274)
100 #define SPEAR1340_CLCD_CLK_SYNT (misc_base + 0x27C)
101 #define SPEAR1340_SYS_CLK_SYNT (misc_base + 0x284)
102 #define SPEAR1340_GEN_CLK_SYNT0 (misc_base + 0x28C)
103 #define SPEAR1340_GEN_CLK_SYNT1 (misc_base + 0x294)
104 #define SPEAR1340_GEN_CLK_SYNT2 (misc_base + 0x29C)
105 #define SPEAR1340_GEN_CLK_SYNT3 (misc_base + 0x304)
106 #define SPEAR1340_PERIP1_CLK_ENB (misc_base + 0x30C)
107 #define SPEAR1340_RTC_CLK_ENB 31
108 #define SPEAR1340_ADC_CLK_ENB 30
109 #define SPEAR1340_C3_CLK_ENB 29
110 #define SPEAR1340_CLCD_CLK_ENB 27
111 #define SPEAR1340_DMA_CLK_ENB 25
112 #define SPEAR1340_GPIO1_CLK_ENB 24
113 #define SPEAR1340_GPIO0_CLK_ENB 23
114 #define SPEAR1340_GPT1_CLK_ENB 22
115 #define SPEAR1340_GPT0_CLK_ENB 21
116 #define SPEAR1340_I2S_PLAY_CLK_ENB 20
117 #define SPEAR1340_I2S_REC_CLK_ENB 19
118 #define SPEAR1340_I2C0_CLK_ENB 18
119 #define SPEAR1340_SSP_CLK_ENB 17
120 #define SPEAR1340_UART0_CLK_ENB 15
121 #define SPEAR1340_PCIE_SATA_CLK_ENB 12
122 #define SPEAR1340_UOC_CLK_ENB 11
123 #define SPEAR1340_UHC1_CLK_ENB 10
124 #define SPEAR1340_UHC0_CLK_ENB 9
125 #define SPEAR1340_GMAC_CLK_ENB 8
126 #define SPEAR1340_CFXD_CLK_ENB 7
127 #define SPEAR1340_SDHCI_CLK_ENB 6
128 #define SPEAR1340_SMI_CLK_ENB 5
129 #define SPEAR1340_FSMC_CLK_ENB 4
130 #define SPEAR1340_SYSRAM0_CLK_ENB 3
131 #define SPEAR1340_SYSRAM1_CLK_ENB 2
132 #define SPEAR1340_SYSROM_CLK_ENB 1
133 #define SPEAR1340_BUS_CLK_ENB 0
134
135 #define SPEAR1340_PERIP2_CLK_ENB (misc_base + 0x310)
136 #define SPEAR1340_THSENS_CLK_ENB 8
137 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
138 #define SPEAR1340_ACP_CLK_ENB 6
139 #define SPEAR1340_GPT3_CLK_ENB 5
140 #define SPEAR1340_GPT2_CLK_ENB 4
141 #define SPEAR1340_KBD_CLK_ENB 3
142 #define SPEAR1340_CPU_DBG_CLK_ENB 2
143 #define SPEAR1340_DDR_CORE_CLK_ENB 1
144 #define SPEAR1340_DDR_CTRL_CLK_ENB 0
145
146 #define SPEAR1340_PERIP3_CLK_ENB (misc_base + 0x314)
147 #define SPEAR1340_PLGPIO_CLK_ENB 18
148 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
149 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
150 #define SPEAR1340_SPDIF_OUT_CLK_ENB 13
151 #define SPEAR1340_SPDIF_IN_CLK_ENB 12
152 #define SPEAR1340_VIDEO_IN_CLK_ENB 11
153 #define SPEAR1340_CAM0_CLK_ENB 10
154 #define SPEAR1340_CAM1_CLK_ENB 9
155 #define SPEAR1340_CAM2_CLK_ENB 8
156 #define SPEAR1340_CAM3_CLK_ENB 7
157 #define SPEAR1340_MALI_CLK_ENB 6
158 #define SPEAR1340_CEC0_CLK_ENB 5
159 #define SPEAR1340_CEC1_CLK_ENB 4
160 #define SPEAR1340_PWM_CLK_ENB 3
161 #define SPEAR1340_I2C1_CLK_ENB 2
162 #define SPEAR1340_UART1_CLK_ENB 1
163
164 static DEFINE_SPINLOCK(_lock);
165
166 /* pll rate configuration table, in ascending order of rates */
167 static struct pll_rate_tbl pll_rtbl[] = {
168 /* PCLK 24MHz */
169 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
170 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
171 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
172 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
173 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
174 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
176 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 };
178
179 /* vco-pll4 rate configuration table, in ascending order of rates */
180 static struct pll_rate_tbl pll4_rtbl[] = {
181 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
182 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
183 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
184 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
185 };
186
187 /*
188 * All below entries generate 166 MHz for
189 * different values of vco1div2
190 */
191 static struct frac_rate_tbl amba_synth_rtbl[] = {
192 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
193 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
194 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
195 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
196 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
197 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
198 };
199
200 /*
201 * Synthesizer Clock derived from vcodiv2. This clock is one of the
202 * possible clocks to feed cpu directly.
203 * We can program this synthesizer to make cpu run on different clock
204 * frequencies.
205 * Following table provides configuration values to let cpu run on 200,
206 * 250, 332, 400 or 500 MHz considering different possibilites of input
207 * (vco1div2) clock.
208 *
209 * --------------------------------------------------------------------
210 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
211 * --------------------------------------------------------------------
212 * 400 200 100 0x04000
213 * 400 250 125 0x03333
214 * 400 332 166 0x0268D
215 * 400 400 200 0x02000
216 * --------------------------------------------------------------------
217 * 500 200 100 0x05000
218 * 500 250 125 0x04000
219 * 500 332 166 0x03031
220 * 500 400 200 0x02800
221 * 500 500 250 0x02000
222 * --------------------------------------------------------------------
223 * 600 200 100 0x06000
224 * 600 250 125 0x04CCE
225 * 600 332 166 0x039D5
226 * 600 400 200 0x03000
227 * 600 500 250 0x02666
228 * --------------------------------------------------------------------
229 * 664 200 100 0x06a38
230 * 664 250 125 0x054FD
231 * 664 332 166 0x04000
232 * 664 400 200 0x0351E
233 * 664 500 250 0x02A7E
234 * --------------------------------------------------------------------
235 * 800 200 100 0x08000
236 * 800 250 125 0x06666
237 * 800 332 166 0x04D18
238 * 800 400 200 0x04000
239 * 800 500 250 0x03333
240 * --------------------------------------------------------------------
241 * sys rate configuration table is in descending order of divisor.
242 */
243 static struct frac_rate_tbl sys_synth_rtbl[] = {
244 {.div = 0x08000},
245 {.div = 0x06a38},
246 {.div = 0x06666},
247 {.div = 0x06000},
248 {.div = 0x054FD},
249 {.div = 0x05000},
250 {.div = 0x04D18},
251 {.div = 0x04CCE},
252 {.div = 0x04000},
253 {.div = 0x039D5},
254 {.div = 0x0351E},
255 {.div = 0x03333},
256 {.div = 0x03031},
257 {.div = 0x03000},
258 {.div = 0x02A7E},
259 {.div = 0x02800},
260 {.div = 0x0268D},
261 {.div = 0x02666},
262 {.div = 0x02000},
263 };
264
265 /* aux rate configuration table, in ascending order of rates */
266 static struct aux_rate_tbl aux_rtbl[] = {
267 /* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */
268 {.xscale = 5, .yscale = 122, .eq = 0},
269 /* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */
270 {.xscale = 10, .yscale = 204, .eq = 0},
271 /* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */
272 {.xscale = 4, .yscale = 25, .eq = 0},
273 /* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */
274 {.xscale = 4, .yscale = 21, .eq = 0},
275 /* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */
276 {.xscale = 5, .yscale = 18, .eq = 0},
277 /* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */
278 {.xscale = 2, .yscale = 6, .eq = 0},
279 /* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */
280 {.xscale = 5, .yscale = 12, .eq = 0},
281 /* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */
282 {.xscale = 2, .yscale = 4, .eq = 0},
283 /* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */
284 {.xscale = 5, .yscale = 18, .eq = 1},
285 /* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */
286 {.xscale = 1, .yscale = 3, .eq = 1},
287 /* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */
288 {.xscale = 5, .yscale = 12, .eq = 1},
289 /* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */
290 {.xscale = 1, .yscale = 2, .eq = 1},
291 };
292
293 /* gmac rate configuration table, in ascending order of rates */
294 static struct aux_rate_tbl gmac_rtbl[] = {
295 /* For gmac phy input clk */
296 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
297 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
298 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
299 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
300 };
301
302 /* clcd rate configuration table, in ascending order of rates */
303 static struct frac_rate_tbl clcd_rtbl[] = {
304 {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
305 {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
306 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
307 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
308 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
309 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
310 {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
311 {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
312 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
313 {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
314 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
315 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
316 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
317 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
318 {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
319 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
320 {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
321 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
322 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
323 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
324 };
325
326 /* i2s prescaler1 masks */
327 static struct aux_clk_masks i2s_prs1_masks = {
328 .eq_sel_mask = AUX_EQ_SEL_MASK,
329 .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
330 .eq1_mask = AUX_EQ1_SEL,
331 .eq2_mask = AUX_EQ2_SEL,
332 .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
333 .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
334 .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
335 .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
336 };
337
338 /* i2s sclk (bit clock) syynthesizers masks */
339 static struct aux_clk_masks i2s_sclk_masks = {
340 .eq_sel_mask = AUX_EQ_SEL_MASK,
341 .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
342 .eq1_mask = AUX_EQ1_SEL,
343 .eq2_mask = AUX_EQ2_SEL,
344 .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
345 .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
346 .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
347 .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
348 .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
349 };
350
351 /* i2s prs1 aux rate configuration table, in ascending order of rates */
352 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
353 /* For parent clk = 49.152 MHz */
354 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
355 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
356 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
357 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
358
359 /*
360 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
361 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
362 */
363 {.xscale = 1, .yscale = 3, .eq = 0},
364
365 /* For parent clk = 49.152 MHz */
366 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
367 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
368 };
369
370 /* i2s sclk aux rate configuration table, in ascending order of rates */
371 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
372 /* For sclk = ref_clk * x/2/y */
373 {.xscale = 1, .yscale = 4, .eq = 0},
374 {.xscale = 1, .yscale = 2, .eq = 0},
375 };
376
377 /* adc rate configuration table, in ascending order of rates */
378 /* possible adc range is 2.5 MHz to 20 MHz. */
379 static struct aux_rate_tbl adc_rtbl[] = {
380 /* For ahb = 166.67 MHz */
381 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
382 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
383 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
384 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
385 };
386
387 /* General synth rate configuration table, in ascending order of rates */
388 static struct frac_rate_tbl gen_rtbl[] = {
389 {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
390 {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
391 {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
392 {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
393 {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
394 {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
395 {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
396 {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
397 {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
398 {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
399 {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
400 {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
401 {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
402 {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
403 {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
404 {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
405 {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
406 {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
407 {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
408 {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
409 {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
410 {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
411 {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
412 {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
413 {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
414 };
415
416 /* clock parents */
417 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
418 static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
419 "pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", };
420 static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
421 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
422 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
423 "uart0_syn_gclk", };
424 static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
425 "uart1_syn_gclk", };
426 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
427 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
428 "osc_25m_clk", };
429 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
430 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
431 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
432 static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
433 "i2s_src_pad_clk", };
434 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
435 static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", };
436 static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
437
438 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
439 "pll3_clk", };
440 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
441 "pll2_clk", };
442
443 void __init spear1340_clk_init(void __iomem *misc_base)
444 {
445 struct clk *clk, *clk1;
446
447 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
448 32000);
449 clk_register_clkdev(clk, "osc_32k_clk", NULL);
450
451 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
452 24000000);
453 clk_register_clkdev(clk, "osc_24m_clk", NULL);
454
455 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
456 25000000);
457 clk_register_clkdev(clk, "osc_25m_clk", NULL);
458
459 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT,
460 125000000);
461 clk_register_clkdev(clk, "gmii_pad_clk", NULL);
462
463 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
464 CLK_IS_ROOT, 12288000);
465 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
466
467 /* clock derived from 32 KHz osc clk */
468 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
469 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
470 &_lock);
471 clk_register_clkdev(clk, NULL, "e0580000.rtc");
472
473 /* clock derived from 24 or 25 MHz osc clk */
474 /* vco-pll */
475 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
476 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
477 SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT,
478 SPEAR1340_PLL_CLK_MASK, 0, &_lock);
479 clk_register_clkdev(clk, "vco1_mclk", NULL);
480 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
481 SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
482 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
483 clk_register_clkdev(clk, "vco1_clk", NULL);
484 clk_register_clkdev(clk1, "pll1_clk", NULL);
485
486 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
487 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
488 SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT,
489 SPEAR1340_PLL_CLK_MASK, 0, &_lock);
490 clk_register_clkdev(clk, "vco2_mclk", NULL);
491 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
492 SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
493 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
494 clk_register_clkdev(clk, "vco2_clk", NULL);
495 clk_register_clkdev(clk1, "pll2_clk", NULL);
496
497 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
498 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
499 SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT,
500 SPEAR1340_PLL_CLK_MASK, 0, &_lock);
501 clk_register_clkdev(clk, "vco3_mclk", NULL);
502 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
503 SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
504 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
505 clk_register_clkdev(clk, "vco3_clk", NULL);
506 clk_register_clkdev(clk1, "pll3_clk", NULL);
507
508 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
509 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
510 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
511 clk_register_clkdev(clk, "vco4_clk", NULL);
512 clk_register_clkdev(clk1, "pll4_clk", NULL);
513
514 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
515 48000000);
516 clk_register_clkdev(clk, "pll5_clk", NULL);
517
518 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
519 25000000);
520 clk_register_clkdev(clk, "pll6_clk", NULL);
521
522 /* vco div n clocks */
523 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
524 2);
525 clk_register_clkdev(clk, "vco1div2_clk", NULL);
526
527 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
528 4);
529 clk_register_clkdev(clk, "vco1div4_clk", NULL);
530
531 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
532 2);
533 clk_register_clkdev(clk, "vco2div2_clk", NULL);
534
535 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
536 2);
537 clk_register_clkdev(clk, "vco3div2_clk", NULL);
538
539 /* peripherals */
540 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
541 128);
542 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
543 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
544 &_lock);
545 clk_register_clkdev(clk, NULL, "e07008c4.thermal");
546
547 /* clock derived from pll4 clk */
548 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
549 1);
550 clk_register_clkdev(clk, "ddr_clk", NULL);
551
552 /* clock derived from pll1 clk */
553 clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0,
554 SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
555 ARRAY_SIZE(sys_synth_rtbl), &_lock);
556 clk_register_clkdev(clk, "sys_syn_clk", NULL);
557
558 clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0,
559 SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
560 ARRAY_SIZE(amba_synth_rtbl), &_lock);
561 clk_register_clkdev(clk, "amba_syn_clk", NULL);
562
563 clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
564 ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT,
565 SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT,
566 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
567 clk_register_clkdev(clk, "sys_mclk", NULL);
568
569 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
570 2);
571 clk_register_clkdev(clk, "cpu_clk", NULL);
572
573 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
574 3);
575 clk_register_clkdev(clk, "cpu_div3_clk", NULL);
576
577 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
578 2);
579 clk_register_clkdev(clk, NULL, "ec800620.wdt");
580
581 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
582 2);
583 clk_register_clkdev(clk, NULL, "smp_twd");
584
585 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
586 ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT,
587 SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT,
588 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
589 clk_register_clkdev(clk, "ahb_clk", NULL);
590
591 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
592 2);
593 clk_register_clkdev(clk, "apb_clk", NULL);
594
595 /* gpt clocks */
596 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
597 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
598 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT,
599 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
600 clk_register_clkdev(clk, "gpt0_mclk", NULL);
601 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
602 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
603 &_lock);
604 clk_register_clkdev(clk, NULL, "gpt0");
605
606 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
607 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
608 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT,
609 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
610 clk_register_clkdev(clk, "gpt1_mclk", NULL);
611 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
612 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
613 &_lock);
614 clk_register_clkdev(clk, NULL, "gpt1");
615
616 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
617 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
618 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT,
619 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
620 clk_register_clkdev(clk, "gpt2_mclk", NULL);
621 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
622 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
623 &_lock);
624 clk_register_clkdev(clk, NULL, "gpt2");
625
626 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
627 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
628 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT,
629 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
630 clk_register_clkdev(clk, "gpt3_mclk", NULL);
631 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
632 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
633 &_lock);
634 clk_register_clkdev(clk, NULL, "gpt3");
635
636 /* others */
637 clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk",
638 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
639 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
640 clk_register_clkdev(clk, "uart0_syn_clk", NULL);
641 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
642
643 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
644 ARRAY_SIZE(uart0_parents),
645 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
646 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
647 SPEAR1340_UART_CLK_MASK, 0, &_lock);
648 clk_register_clkdev(clk, "uart0_mclk", NULL);
649
650 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
651 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
652 SPEAR1340_UART0_CLK_ENB, 0, &_lock);
653 clk_register_clkdev(clk, NULL, "e0000000.serial");
654
655 clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk",
656 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
657 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
658 clk_register_clkdev(clk, "uart1_syn_clk", NULL);
659 clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
660
661 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
662 ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT,
663 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT,
664 SPEAR1340_UART_CLK_MASK, 0, &_lock);
665 clk_register_clkdev(clk, "uart1_mclk", NULL);
666
667 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
668 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
669 &_lock);
670 clk_register_clkdev(clk, NULL, "b4100000.serial");
671
672 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
673 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
674 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
675 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
676 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
677
678 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
679 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
680 SPEAR1340_SDHCI_CLK_ENB, 0, &_lock);
681 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
682
683 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
684 0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl,
685 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
686 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
687 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
688
689 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
690 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
691 SPEAR1340_CFXD_CLK_ENB, 0, &_lock);
692 clk_register_clkdev(clk, NULL, "b2800000.cf");
693 clk_register_clkdev(clk, NULL, "arasan_xd");
694
695 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0,
696 SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl,
697 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
698 clk_register_clkdev(clk, "c3_syn_clk", NULL);
699 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
700
701 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
702 ARRAY_SIZE(c3_parents),
703 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
704 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
705 SPEAR1340_C3_CLK_MASK, 0, &_lock);
706 clk_register_clkdev(clk, "c3_mclk", NULL);
707
708 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT,
709 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
710 &_lock);
711 clk_register_clkdev(clk, NULL, "e1800000.c3");
712
713 /* gmac */
714 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
715 ARRAY_SIZE(gmac_phy_input_parents),
716 CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG,
717 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
718 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
719 clk_register_clkdev(clk, "phy_input_mclk", NULL);
720
721 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
722 0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl,
723 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
724 clk_register_clkdev(clk, "phy_syn_clk", NULL);
725 clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
726
727 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
728 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
729 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
730 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
731 clk_register_clkdev(clk, "stmmacphy.0", NULL);
732
733 /* clcd */
734 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
735 ARRAY_SIZE(clcd_synth_parents),
736 CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT,
737 SPEAR1340_CLCD_SYNT_CLK_SHIFT,
738 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
739 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
740
741 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
742 SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
743 ARRAY_SIZE(clcd_rtbl), &_lock);
744 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
745
746 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
747 ARRAY_SIZE(clcd_pixel_parents),
748 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
749 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
750 SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
751 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
752
753 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
754 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
755 &_lock);
756 clk_register_clkdev(clk, NULL, "e1000000.clcd");
757
758 /* i2s */
759 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
760 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
761 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT,
762 SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock);
763 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
764
765 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
766 CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG,
767 &i2s_prs1_masks, i2s_prs1_rtbl,
768 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
769 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
770
771 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
772 ARRAY_SIZE(i2s_ref_parents),
773 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
774 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
775 SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
776 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
777
778 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
779 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
780 0, &_lock);
781 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
782
783 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk",
784 0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks,
785 i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock,
786 &clk1);
787 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
788 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
789
790 /* clock derived from ahb clk */
791 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
792 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
793 &_lock);
794 clk_register_clkdev(clk, NULL, "e0280000.i2c");
795
796 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
797 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
798 &_lock);
799 clk_register_clkdev(clk, NULL, "b4000000.i2c");
800
801 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
802 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
803 &_lock);
804 clk_register_clkdev(clk, NULL, "ea800000.dma");
805 clk_register_clkdev(clk, NULL, "eb000000.dma");
806
807 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
808 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
809 &_lock);
810 clk_register_clkdev(clk, NULL, "e2000000.eth");
811
812 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
813 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
814 &_lock);
815 clk_register_clkdev(clk, NULL, "b0000000.flash");
816
817 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
818 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
819 &_lock);
820 clk_register_clkdev(clk, NULL, "ea000000.flash");
821
822 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
823 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
824 &_lock);
825 clk_register_clkdev(clk, NULL, "e4000000.ohci");
826 clk_register_clkdev(clk, NULL, "e4800000.ehci");
827
828 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
829 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
830 &_lock);
831 clk_register_clkdev(clk, NULL, "e5000000.ohci");
832 clk_register_clkdev(clk, NULL, "e5800000.ehci");
833
834 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
835 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
836 &_lock);
837 clk_register_clkdev(clk, NULL, "e3800000.otg");
838
839 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
840 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
841 0, &_lock);
842 clk_register_clkdev(clk, NULL, "b1000000.pcie");
843 clk_register_clkdev(clk, NULL, "b1000000.ahci");
844
845 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
846 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
847 &_lock);
848 clk_register_clkdev(clk, "sysram0_clk", NULL);
849
850 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
851 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
852 &_lock);
853 clk_register_clkdev(clk, "sysram1_clk", NULL);
854
855 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
856 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
857 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
858 clk_register_clkdev(clk, "adc_syn_clk", NULL);
859 clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
860
861 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
862 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
863 SPEAR1340_ADC_CLK_ENB, 0, &_lock);
864 clk_register_clkdev(clk, NULL, "e0080000.adc");
865
866 /* clock derived from apb clk */
867 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
868 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
869 &_lock);
870 clk_register_clkdev(clk, NULL, "e0100000.spi");
871
872 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
873 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
874 &_lock);
875 clk_register_clkdev(clk, NULL, "e0600000.gpio");
876
877 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
878 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
879 &_lock);
880 clk_register_clkdev(clk, NULL, "e0680000.gpio");
881
882 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
883 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
884 &_lock);
885 clk_register_clkdev(clk, NULL, "b2400000.i2s-play");
886
887 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
888 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
889 &_lock);
890 clk_register_clkdev(clk, NULL, "b2000000.i2s-rec");
891
892 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
893 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
894 &_lock);
895 clk_register_clkdev(clk, NULL, "e0300000.kbd");
896
897 /* RAS clks */
898 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
899 ARRAY_SIZE(gen_synth0_1_parents),
900 CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
901 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
902 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
903 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
904
905 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
906 ARRAY_SIZE(gen_synth2_3_parents),
907 CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
908 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
909 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
910 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
911
912 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0,
913 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
914 &_lock);
915 clk_register_clkdev(clk, "gen_syn0_clk", NULL);
916
917 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0,
918 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
919 &_lock);
920 clk_register_clkdev(clk, "gen_syn1_clk", NULL);
921
922 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0,
923 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
924 &_lock);
925 clk_register_clkdev(clk, "gen_syn2_clk", NULL);
926
927 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0,
928 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
929 &_lock);
930 clk_register_clkdev(clk, "gen_syn3_clk", NULL);
931
932 clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk",
933 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
934 SPEAR1340_MALI_CLK_ENB, 0, &_lock);
935 clk_register_clkdev(clk, NULL, "mali");
936
937 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
938 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
939 &_lock);
940 clk_register_clkdev(clk, NULL, "spear_cec.0");
941
942 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
943 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
944 &_lock);
945 clk_register_clkdev(clk, NULL, "spear_cec.1");
946
947 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
948 ARRAY_SIZE(spdif_out_parents),
949 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
950 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
951 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
952 clk_register_clkdev(clk, "spdif_out_mclk", NULL);
953
954 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk",
955 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
956 SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock);
957 clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
958
959 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
960 ARRAY_SIZE(spdif_in_parents),
961 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
962 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
963 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
964 clk_register_clkdev(clk, "spdif_in_mclk", NULL);
965
966 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk",
967 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
968 SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
969 clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
970
971 clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
972 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
973 &_lock);
974 clk_register_clkdev(clk, NULL, "acp_clk");
975
976 clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
977 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
978 &_lock);
979 clk_register_clkdev(clk, NULL, "e2800000.gpio");
980
981 clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
982 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
983 0, &_lock);
984 clk_register_clkdev(clk, NULL, "video_dec");
985
986 clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
987 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
988 0, &_lock);
989 clk_register_clkdev(clk, NULL, "video_enc");
990
991 clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
992 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
993 &_lock);
994 clk_register_clkdev(clk, NULL, "spear_vip");
995
996 clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
997 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
998 &_lock);
999 clk_register_clkdev(clk, NULL, "d0200000.cam0");
1000
1001 clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
1002 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
1003 &_lock);
1004 clk_register_clkdev(clk, NULL, "d0300000.cam1");
1005
1006 clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
1007 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
1008 &_lock);
1009 clk_register_clkdev(clk, NULL, "d0400000.cam2");
1010
1011 clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
1012 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
1013 &_lock);
1014 clk_register_clkdev(clk, NULL, "d0500000.cam3");
1015
1016 clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0,
1017 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
1018 &_lock);
1019 clk_register_clkdev(clk, NULL, "e0180000.pwm");
1020 }
Linux with added FPC-III support