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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / clk / st / clkgen-pll.c
blob29769d79e3065d8bfd32ed64c2fcc38e5c0d54cb
1 /*
2 * Copyright (C) 2014 STMicroelectronics (R&D) Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 /*
12 * Authors:
13 * Stephen Gallimore <stephen.gallimore@st.com>,
14 * Pankaj Dev <pankaj.dev@st.com>.
15 */
16
17 #include <linux/slab.h>
18 #include <linux/of_address.h>
19 #include <linux/clk-provider.h>
20
21 #include "clkgen.h"
22
23 static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
24
25 /*
26 * Common PLL configuration register bits for PLL800 and PLL1600 C65
27 */
28 #define C65_MDIV_PLL800_MASK (0xff)
29 #define C65_MDIV_PLL1600_MASK (0x7)
30 #define C65_NDIV_MASK (0xff)
31 #define C65_PDIV_MASK (0x7)
32
33 /*
34 * PLL configuration register bits for PLL3200 C32
35 */
36 #define C32_NDIV_MASK (0xff)
37 #define C32_IDF_MASK (0x7)
38 #define C32_ODF_MASK (0x3f)
39 #define C32_LDF_MASK (0x7f)
40
41 #define C32_MAX_ODFS (4)
42
43 struct clkgen_pll_data {
44 struct clkgen_field pdn_status;
45 struct clkgen_field locked_status;
46 struct clkgen_field mdiv;
47 struct clkgen_field ndiv;
48 struct clkgen_field pdiv;
49 struct clkgen_field idf;
50 struct clkgen_field ldf;
51 unsigned int num_odfs;
52 struct clkgen_field odf[C32_MAX_ODFS];
53 struct clkgen_field odf_gate[C32_MAX_ODFS];
54 const struct clk_ops *ops;
55 };
56
57 static const struct clk_ops st_pll1600c65_ops;
58 static const struct clk_ops st_pll800c65_ops;
59 static const struct clk_ops stm_pll3200c32_ops;
60 static const struct clk_ops st_pll1200c32_ops;
61
62 static const struct clkgen_pll_data st_pll1600c65_ax = {
63 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
64 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
65 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
66 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
67 .ops = &st_pll1600c65_ops
68 };
69
70 static const struct clkgen_pll_data st_pll800c65_ax = {
71 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
72 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
73 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
74 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
75 .pdiv = CLKGEN_FIELD(0x0, C65_PDIV_MASK, 16),
76 .ops = &st_pll800c65_ops
77 };
78
79 static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
80 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 31),
81 .locked_status = CLKGEN_FIELD(0x4, 0x1, 31),
82 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
83 .idf = CLKGEN_FIELD(0x4, C32_IDF_MASK, 0x0),
84 .num_odfs = 4,
85 .odf = { CLKGEN_FIELD(0x54, C32_ODF_MASK, 4),
86 CLKGEN_FIELD(0x54, C32_ODF_MASK, 10),
87 CLKGEN_FIELD(0x54, C32_ODF_MASK, 16),
88 CLKGEN_FIELD(0x54, C32_ODF_MASK, 22) },
89 .odf_gate = { CLKGEN_FIELD(0x54, 0x1, 0),
90 CLKGEN_FIELD(0x54, 0x1, 1),
91 CLKGEN_FIELD(0x54, 0x1, 2),
92 CLKGEN_FIELD(0x54, 0x1, 3) },
93 .ops = &stm_pll3200c32_ops,
94 };
95
96 static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
97 .pdn_status = CLKGEN_FIELD(0xC, 0x1, 31),
98 .locked_status = CLKGEN_FIELD(0x10, 0x1, 31),
99 .ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
100 .idf = CLKGEN_FIELD(0x10, C32_IDF_MASK, 0x0),
101 .num_odfs = 4,
102 .odf = { CLKGEN_FIELD(0x58, C32_ODF_MASK, 4),
103 CLKGEN_FIELD(0x58, C32_ODF_MASK, 10),
104 CLKGEN_FIELD(0x58, C32_ODF_MASK, 16),
105 CLKGEN_FIELD(0x58, C32_ODF_MASK, 22) },
106 .odf_gate = { CLKGEN_FIELD(0x58, 0x1, 0),
107 CLKGEN_FIELD(0x58, 0x1, 1),
108 CLKGEN_FIELD(0x58, 0x1, 2),
109 CLKGEN_FIELD(0x58, 0x1, 3) },
110 .ops = &stm_pll3200c32_ops,
111 };
112
113 /* 415 specific */
114 static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
115 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
116 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
117 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
118 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 22),
119 .num_odfs = 1,
120 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 3) },
121 .odf_gate = { CLKGEN_FIELD(0x0, 0x1, 28) },
122 .ops = &stm_pll3200c32_ops,
123 };
124
125 static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
126 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
127 .locked_status = CLKGEN_FIELD(0x100, 0x1, 0),
128 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
129 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
130 .num_odfs = 2,
131 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8),
132 CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) },
133 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28),
134 CLKGEN_FIELD(0x4, 0x1, 29) },
135 .ops = &stm_pll3200c32_ops,
136 };
137
138 static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
139 .pdn_status = CLKGEN_FIELD(0x144, 0x1, 3),
140 .locked_status = CLKGEN_FIELD(0x168, 0x1, 0),
141 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
142 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
143 .num_odfs = 0,
144 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) },
145 .ops = &st_pll1200c32_ops,
146 };
147
148 /* 416 specific */
149 static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
150 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
151 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
152 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
153 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
154 .num_odfs = 1,
155 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8) },
156 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28) },
157 .ops = &stm_pll3200c32_ops,
158 };
159
160 static const struct clkgen_pll_data st_pll3200c32_ddr_416 = {
161 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
162 .locked_status = CLKGEN_FIELD(0x10C, 0x1, 0),
163 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
164 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
165 .num_odfs = 2,
166 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8),
167 CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) },
168 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28),
169 CLKGEN_FIELD(0x4, 0x1, 29) },
170 .ops = &stm_pll3200c32_ops,
171 };
172
173 static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
174 .pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3),
175 .locked_status = CLKGEN_FIELD(0x90C, 0x1, 0),
176 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
177 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
178 .num_odfs = 0,
179 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) },
180 .ops = &st_pll1200c32_ops,
181 };
182
183 static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
184 /* 407 A0 */
185 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
186 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
187 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
188 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
189 .num_odfs = 1,
190 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
191 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
192 .ops = &stm_pll3200c32_ops,
193 };
194
195 static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
196 /* 407 C0 PLL0 */
197 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
198 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
199 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
200 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
201 .num_odfs = 1,
202 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
203 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
204 .ops = &stm_pll3200c32_ops,
205 };
206
207 static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
208 /* 407 C0 PLL1 */
209 .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
210 .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
211 .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
212 .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
213 .num_odfs = 1,
214 .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
215 .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
216 .ops = &stm_pll3200c32_ops,
217 };
218
219 static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
220 /* 407 A9 */
221 .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
222 .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
223 .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
224 .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
225 .num_odfs = 1,
226 .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
227 .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
228 .ops = &stm_pll3200c32_ops,
229 };
230
231 /**
232 * DOC: Clock Generated by PLL, rate set and enabled by bootloader
233 *
234 * Traits of this clock:
235 * prepare - clk_(un)prepare only ensures parent is (un)prepared
236 * enable - clk_enable/disable only ensures parent is enabled
237 * rate - rate is fixed. No clk_set_rate support
238 * parent - fixed parent. No clk_set_parent support
239 */
240
241 /**
242 * PLL clock that is integrated in the ClockGenA instances on the STiH415
243 * and STiH416.
244 *
245 * @hw: handle between common and hardware-specific interfaces.
246 * @type: PLL instance type.
247 * @regs_base: base of the PLL configuration register(s).
248 *
249 */
250 struct clkgen_pll {
251 struct clk_hw hw;
252 struct clkgen_pll_data *data;
253 void __iomem *regs_base;
254 };
255
256 #define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
257
258 static int clkgen_pll_is_locked(struct clk_hw *hw)
259 {
260 struct clkgen_pll *pll = to_clkgen_pll(hw);
261 u32 locked = CLKGEN_READ(pll, locked_status);
262
263 return !!locked;
264 }
265
266 static int clkgen_pll_is_enabled(struct clk_hw *hw)
267 {
268 struct clkgen_pll *pll = to_clkgen_pll(hw);
269 u32 poweroff = CLKGEN_READ(pll, pdn_status);
270 return !poweroff;
271 }
272
273 unsigned long recalc_stm_pll800c65(struct clk_hw *hw,
274 unsigned long parent_rate)
275 {
276 struct clkgen_pll *pll = to_clkgen_pll(hw);
277 unsigned long mdiv, ndiv, pdiv;
278 unsigned long rate;
279 uint64_t res;
280
281 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
282 return 0;
283
284 pdiv = CLKGEN_READ(pll, pdiv);
285 mdiv = CLKGEN_READ(pll, mdiv);
286 ndiv = CLKGEN_READ(pll, ndiv);
287
288 if (!mdiv)
289 mdiv++; /* mdiv=0 or 1 => MDIV=1 */
290
291 res = (uint64_t)2 * (uint64_t)parent_rate * (uint64_t)ndiv;
292 rate = (unsigned long)div64_u64(res, mdiv * (1 << pdiv));
293
294 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
295
296 return rate;
297
298 }
299
300 unsigned long recalc_stm_pll1600c65(struct clk_hw *hw,
301 unsigned long parent_rate)
302 {
303 struct clkgen_pll *pll = to_clkgen_pll(hw);
304 unsigned long mdiv, ndiv;
305 unsigned long rate;
306
307 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
308 return 0;
309
310 mdiv = CLKGEN_READ(pll, mdiv);
311 ndiv = CLKGEN_READ(pll, ndiv);
312
313 if (!mdiv)
314 mdiv = 1;
315
316 /* Note: input is divided by 1000 to avoid overflow */
317 rate = ((2 * (parent_rate / 1000) * ndiv) / mdiv) * 1000;
318
319 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
320
321 return rate;
322 }
323
324 unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
325 unsigned long parent_rate)
326 {
327 struct clkgen_pll *pll = to_clkgen_pll(hw);
328 unsigned long ndiv, idf;
329 unsigned long rate = 0;
330
331 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
332 return 0;
333
334 ndiv = CLKGEN_READ(pll, ndiv);
335 idf = CLKGEN_READ(pll, idf);
336
337 if (idf)
338 /* Note: input is divided to avoid overflow */
339 rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
340
341 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
342
343 return rate;
344 }
345
346 unsigned long recalc_stm_pll1200c32(struct clk_hw *hw,
347 unsigned long parent_rate)
348 {
349 struct clkgen_pll *pll = to_clkgen_pll(hw);
350 unsigned long odf, ldf, idf;
351 unsigned long rate;
352
353 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
354 return 0;
355
356 odf = CLKGEN_READ(pll, odf[0]);
357 ldf = CLKGEN_READ(pll, ldf);
358 idf = CLKGEN_READ(pll, idf);
359
360 if (!idf) /* idf==0 means 1 */
361 idf = 1;
362 if (!odf) /* odf==0 means 1 */
363 odf = 1;
364
365 /* Note: input is divided by 1000 to avoid overflow */
366 rate = (((parent_rate / 1000) * ldf) / (odf * idf)) * 1000;
367
368 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
369
370 return rate;
371 }
372
373 static const struct clk_ops st_pll1600c65_ops = {
374 .is_enabled = clkgen_pll_is_enabled,
375 .recalc_rate = recalc_stm_pll1600c65,
376 };
377
378 static const struct clk_ops st_pll800c65_ops = {
379 .is_enabled = clkgen_pll_is_enabled,
380 .recalc_rate = recalc_stm_pll800c65,
381 };
382
383 static const struct clk_ops stm_pll3200c32_ops = {
384 .is_enabled = clkgen_pll_is_enabled,
385 .recalc_rate = recalc_stm_pll3200c32,
386 };
387
388 static const struct clk_ops st_pll1200c32_ops = {
389 .is_enabled = clkgen_pll_is_enabled,
390 .recalc_rate = recalc_stm_pll1200c32,
391 };
392
393 static struct clk * __init clkgen_pll_register(const char *parent_name,
394 struct clkgen_pll_data *pll_data,
395 void __iomem *reg,
396 const char *clk_name)
397 {
398 struct clkgen_pll *pll;
399 struct clk *clk;
400 struct clk_init_data init;
401
402 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
403 if (!pll)
404 return ERR_PTR(-ENOMEM);
405
406 init.name = clk_name;
407 init.ops = pll_data->ops;
408
409 init.flags = CLK_IS_BASIC;
410 init.parent_names = &parent_name;
411 init.num_parents = 1;
412
413 pll->data = pll_data;
414 pll->regs_base = reg;
415 pll->hw.init = &init;
416
417 clk = clk_register(NULL, &pll->hw);
418 if (IS_ERR(clk)) {
419 kfree(pll);
420 return clk;
421 }
422
423 pr_debug("%s: parent %s rate %lu\n",
424 __clk_get_name(clk),
425 __clk_get_name(clk_get_parent(clk)),
426 clk_get_rate(clk));
427
428 return clk;
429 }
430
431 static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name,
432 const char *clk_name)
433 {
434 struct clk *clk;
435
436 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2);
437 if (IS_ERR(clk))
438 return clk;
439
440 pr_debug("%s: parent %s rate %lu\n",
441 __clk_get_name(clk),
442 __clk_get_name(clk_get_parent(clk)),
443 clk_get_rate(clk));
444 return clk;
445 }
446
447 static void __iomem * __init clkgen_get_register_base(
448 struct device_node *np)
449 {
450 struct device_node *pnode;
451 void __iomem *reg = NULL;
452
453 pnode = of_get_parent(np);
454 if (!pnode)
455 return NULL;
456
457 reg = of_iomap(pnode, 0);
458
459 of_node_put(pnode);
460 return reg;
461 }
462
463 #define CLKGENAx_PLL0_OFFSET 0x0
464 #define CLKGENAx_PLL1_OFFSET 0x4
465
466 static void __init clkgena_c65_pll_setup(struct device_node *np)
467 {
468 const int num_pll_outputs = 3;
469 struct clk_onecell_data *clk_data;
470 const char *parent_name;
471 void __iomem *reg;
472 const char *clk_name;
473
474 parent_name = of_clk_get_parent_name(np, 0);
475 if (!parent_name)
476 return;
477
478 reg = clkgen_get_register_base(np);
479 if (!reg)
480 return;
481
482 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
483 if (!clk_data)
484 return;
485
486 clk_data->clk_num = num_pll_outputs;
487 clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
488 GFP_KERNEL);
489
490 if (!clk_data->clks)
491 goto err;
492
493 if (of_property_read_string_index(np, "clock-output-names",
494 0, &clk_name))
495 goto err;
496
497 /*
498 * PLL0 HS (high speed) output
499 */
500 clk_data->clks[0] = clkgen_pll_register(parent_name,
501 (struct clkgen_pll_data *) &st_pll1600c65_ax,
502 reg + CLKGENAx_PLL0_OFFSET, clk_name);
503
504 if (IS_ERR(clk_data->clks[0]))
505 goto err;
506
507 if (of_property_read_string_index(np, "clock-output-names",
508 1, &clk_name))
509 goto err;
510
511 /*
512 * PLL0 LS (low speed) output, which is a fixed divide by 2 of the
513 * high speed output.
514 */
515 clk_data->clks[1] = clkgen_c65_lsdiv_register(__clk_get_name
516 (clk_data->clks[0]),
517 clk_name);
518
519 if (IS_ERR(clk_data->clks[1]))
520 goto err;
521
522 if (of_property_read_string_index(np, "clock-output-names",
523 2, &clk_name))
524 goto err;
525
526 /*
527 * PLL1 output
528 */
529 clk_data->clks[2] = clkgen_pll_register(parent_name,
530 (struct clkgen_pll_data *) &st_pll800c65_ax,
531 reg + CLKGENAx_PLL1_OFFSET, clk_name);
532
533 if (IS_ERR(clk_data->clks[2]))
534 goto err;
535
536 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
537 return;
538
539 err:
540 kfree(clk_data->clks);
541 kfree(clk_data);
542 }
543 CLK_OF_DECLARE(clkgena_c65_plls,
544 "st,clkgena-plls-c65", clkgena_c65_pll_setup);
545
546 static struct clk * __init clkgen_odf_register(const char *parent_name,
547 void * __iomem reg,
548 struct clkgen_pll_data *pll_data,
549 int odf,
550 spinlock_t *odf_lock,
551 const char *odf_name)
552 {
553 struct clk *clk;
554 unsigned long flags;
555 struct clk_gate *gate;
556 struct clk_divider *div;
557
558 flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
559
560 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
561 if (!gate)
562 return ERR_PTR(-ENOMEM);
563
564 gate->flags = CLK_GATE_SET_TO_DISABLE;
565 gate->reg = reg + pll_data->odf_gate[odf].offset;
566 gate->bit_idx = pll_data->odf_gate[odf].shift;
567 gate->lock = odf_lock;
568
569 div = kzalloc(sizeof(*div), GFP_KERNEL);
570 if (!div) {
571 kfree(gate);
572 return ERR_PTR(-ENOMEM);
573 }
574
575 div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
576 div->reg = reg + pll_data->odf[odf].offset;
577 div->shift = pll_data->odf[odf].shift;
578 div->width = fls(pll_data->odf[odf].mask);
579 div->lock = odf_lock;
580
581 clk = clk_register_composite(NULL, odf_name, &parent_name, 1,
582 NULL, NULL,
583 &div->hw, &clk_divider_ops,
584 &gate->hw, &clk_gate_ops,
585 flags);
586 if (IS_ERR(clk))
587 return clk;
588
589 pr_debug("%s: parent %s rate %lu\n",
590 __clk_get_name(clk),
591 __clk_get_name(clk_get_parent(clk)),
592 clk_get_rate(clk));
593 return clk;
594 }
595
596 static struct of_device_id c32_pll_of_match[] = {
597 {
598 .compatible = "st,plls-c32-a1x-0",
599 .data = &st_pll3200c32_a1x_0,
600 },
601 {
602 .compatible = "st,plls-c32-a1x-1",
603 .data = &st_pll3200c32_a1x_1,
604 },
605 {
606 .compatible = "st,stih415-plls-c32-a9",
607 .data = &st_pll3200c32_a9_415,
608 },
609 {
610 .compatible = "st,stih415-plls-c32-ddr",
611 .data = &st_pll3200c32_ddr_415,
612 },
613 {
614 .compatible = "st,stih416-plls-c32-a9",
615 .data = &st_pll3200c32_a9_416,
616 },
617 {
618 .compatible = "st,stih416-plls-c32-ddr",
619 .data = &st_pll3200c32_ddr_416,
620 },
621 {
622 .compatible = "st,stih407-plls-c32-a0",
623 .data = &st_pll3200c32_407_a0,
624 },
625 {
626 .compatible = "st,stih407-plls-c32-c0_0",
627 .data = &st_pll3200c32_407_c0_0,
628 },
629 {
630 .compatible = "st,stih407-plls-c32-c0_1",
631 .data = &st_pll3200c32_407_c0_1,
632 },
633 {
634 .compatible = "st,stih407-plls-c32-a9",
635 .data = &st_pll3200c32_407_a9,
636 },
637 {}
638 };
639
640 static void __init clkgen_c32_pll_setup(struct device_node *np)
641 {
642 const struct of_device_id *match;
643 struct clk *clk;
644 const char *parent_name, *pll_name;
645 void __iomem *pll_base;
646 int num_odfs, odf;
647 struct clk_onecell_data *clk_data;
648 struct clkgen_pll_data *data;
649
650 match = of_match_node(c32_pll_of_match, np);
651 if (!match) {
652 pr_err("%s: No matching data\n", __func__);
653 return;
654 }
655
656 data = (struct clkgen_pll_data *) match->data;
657
658 parent_name = of_clk_get_parent_name(np, 0);
659 if (!parent_name)
660 return;
661
662 pll_base = clkgen_get_register_base(np);
663 if (!pll_base)
664 return;
665
666 clk = clkgen_pll_register(parent_name, data, pll_base, np->name);
667 if (IS_ERR(clk))
668 return;
669
670 pll_name = __clk_get_name(clk);
671
672 num_odfs = data->num_odfs;
673
674 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
675 if (!clk_data)
676 return;
677
678 clk_data->clk_num = num_odfs;
679 clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
680 GFP_KERNEL);
681
682 if (!clk_data->clks)
683 goto err;
684
685 for (odf = 0; odf < num_odfs; odf++) {
686 struct clk *clk;
687 const char *clk_name;
688
689 if (of_property_read_string_index(np, "clock-output-names",
690 odf, &clk_name))
691 return;
692
693 clk = clkgen_odf_register(pll_name, pll_base, data,
694 odf, &clkgena_c32_odf_lock, clk_name);
695 if (IS_ERR(clk))
696 goto err;
697
698 clk_data->clks[odf] = clk;
699 }
700
701 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
702 return;
703
704 err:
705 kfree(pll_name);
706 kfree(clk_data->clks);
707 kfree(clk_data);
708 }
709 CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup);
710
711 static struct of_device_id c32_gpu_pll_of_match[] = {
712 {
713 .compatible = "st,stih415-gpu-pll-c32",
714 .data = &st_pll1200c32_gpu_415,
715 },
716 {
717 .compatible = "st,stih416-gpu-pll-c32",
718 .data = &st_pll1200c32_gpu_416,
719 },
720 {}
721 };
722
723 static void __init clkgengpu_c32_pll_setup(struct device_node *np)
724 {
725 const struct of_device_id *match;
726 struct clk *clk;
727 const char *parent_name;
728 void __iomem *reg;
729 const char *clk_name;
730 struct clkgen_pll_data *data;
731
732 match = of_match_node(c32_gpu_pll_of_match, np);
733 if (!match) {
734 pr_err("%s: No matching data\n", __func__);
735 return;
736 }
737
738 data = (struct clkgen_pll_data *)match->data;
739
740 parent_name = of_clk_get_parent_name(np, 0);
741 if (!parent_name)
742 return;
743
744 reg = clkgen_get_register_base(np);
745 if (!reg)
746 return;
747
748 if (of_property_read_string_index(np, "clock-output-names",
749 0, &clk_name))
750 return;
751
752 /*
753 * PLL 1200MHz output
754 */
755 clk = clkgen_pll_register(parent_name, data, reg, clk_name);
756
757 if (!IS_ERR(clk))
758 of_clk_add_provider(np, of_clk_src_simple_get, clk);
759
760 return;
761 }
762 CLK_OF_DECLARE(clkgengpu_c32_pll,
763 "st,clkgengpu-pll-c32", clkgengpu_c32_pll_setup);
Linux with added FPC-III support