2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
21 #include <linux/of_address.h>
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/clk/tegra.h>
29 #define AUDIO_SYNC_CLK_I2S0 0x4a0
30 #define AUDIO_SYNC_CLK_I2S1 0x4a4
31 #define AUDIO_SYNC_CLK_I2S2 0x4a8
32 #define AUDIO_SYNC_CLK_I2S3 0x4ac
33 #define AUDIO_SYNC_CLK_I2S4 0x4b0
34 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
36 #define AUDIO_SYNC_DOUBLER 0x49c
40 struct tegra_sync_source_initdata
{
43 unsigned long max_rate
;
51 .max_rate = 24000000,\
52 .clk_id = tegra_clk_ ## _name,\
55 struct tegra_audio_clk_initdata
{
63 #define AUDIO(_name, _offset) \
66 .mux_name = #_name"_mux",\
68 .gate_clk_id = tegra_clk_ ## _name,\
69 .mux_clk_id = tegra_clk_ ## _name ## _mux,\
72 struct tegra_audio2x_clk_initdata
{
82 #define AUDIO2X(_name, _num, _offset) \
85 .gate_name = #_name"_2x",\
86 .name_2x = #_name"_doubler",\
87 .div_name = #_name"_div",\
88 .clk_id = tegra_clk_ ## _name ## _2x,\
90 .div_offset = _offset,\
93 static DEFINE_SPINLOCK(clk_doubler_lock
);
95 static const char *mux_audio_sync_clk
[] = { "spdif_in_sync", "i2s0_sync",
96 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
99 static struct tegra_sync_source_initdata sync_source_clks
[] __initdata
= {
109 static struct tegra_audio_clk_initdata audio_clks
[] = {
110 AUDIO(audio0
, AUDIO_SYNC_CLK_I2S0
),
111 AUDIO(audio1
, AUDIO_SYNC_CLK_I2S1
),
112 AUDIO(audio2
, AUDIO_SYNC_CLK_I2S2
),
113 AUDIO(audio3
, AUDIO_SYNC_CLK_I2S3
),
114 AUDIO(audio4
, AUDIO_SYNC_CLK_I2S4
),
115 AUDIO(spdif
, AUDIO_SYNC_CLK_SPDIF
),
118 static struct tegra_audio2x_clk_initdata audio2x_clks
[] = {
119 AUDIO2X(audio0
, 113, 24),
120 AUDIO2X(audio1
, 114, 25),
121 AUDIO2X(audio2
, 115, 26),
122 AUDIO2X(audio3
, 116, 27),
123 AUDIO2X(audio4
, 117, 28),
124 AUDIO2X(spdif
, 118, 29),
127 void __init
tegra_audio_clk_init(void __iomem
*clk_base
,
128 void __iomem
*pmc_base
, struct tegra_clk
*tegra_clks
,
129 struct tegra_clk_pll_params
*pll_a_params
)
136 dt_clk
= tegra_lookup_dt_id(tegra_clk_pll_a
, tegra_clks
);
138 clk
= tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base
,
139 pmc_base
, 0, pll_a_params
, NULL
);
144 dt_clk
= tegra_lookup_dt_id(tegra_clk_pll_a_out0
, tegra_clks
);
146 clk
= tegra_clk_register_divider("pll_a_out0_div", "pll_a",
147 clk_base
+ PLLA_OUT
, 0, TEGRA_DIVIDER_ROUND_UP
,
149 clk
= tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
150 clk_base
+ PLLA_OUT
, 1, 0, CLK_IGNORE_UNUSED
|
151 CLK_SET_RATE_PARENT
, 0, NULL
);
155 for (i
= 0; i
< ARRAY_SIZE(sync_source_clks
); i
++) {
156 struct tegra_sync_source_initdata
*data
;
158 data
= &sync_source_clks
[i
];
160 dt_clk
= tegra_lookup_dt_id(data
->clk_id
, tegra_clks
);
164 clk
= tegra_clk_register_sync_source(data
->name
,
165 data
->rate
, data
->max_rate
);
169 for (i
= 0; i
< ARRAY_SIZE(audio_clks
); i
++) {
170 struct tegra_audio_clk_initdata
*data
;
172 data
= &audio_clks
[i
];
173 dt_clk
= tegra_lookup_dt_id(data
->mux_clk_id
, tegra_clks
);
177 clk
= clk_register_mux(NULL
, data
->mux_name
, mux_audio_sync_clk
,
178 ARRAY_SIZE(mux_audio_sync_clk
),
179 CLK_SET_RATE_NO_REPARENT
,
180 clk_base
+ data
->offset
, 0, 3, 0,
184 dt_clk
= tegra_lookup_dt_id(data
->gate_clk_id
, tegra_clks
);
188 clk
= clk_register_gate(NULL
, data
->gate_name
, data
->mux_name
,
189 0, clk_base
+ data
->offset
, 4,
190 CLK_GATE_SET_TO_DISABLE
, NULL
);
194 for (i
= 0; i
< ARRAY_SIZE(audio2x_clks
); i
++) {
195 struct tegra_audio2x_clk_initdata
*data
;
197 data
= &audio2x_clks
[i
];
198 dt_clk
= tegra_lookup_dt_id(data
->clk_id
, tegra_clks
);
202 clk
= clk_register_fixed_factor(NULL
, data
->name_2x
,
203 data
->parent
, CLK_SET_RATE_PARENT
, 2, 1);
204 clk
= tegra_clk_register_divider(data
->div_name
,
205 data
->name_2x
, clk_base
+ AUDIO_SYNC_DOUBLER
,
206 0, 0, data
->div_offset
, 1, 0,
208 clk
= tegra_clk_register_periph_gate(data
->gate_name
,
209 data
->div_name
, TEGRA_PERIPH_NO_RESET
,
210 clk_base
, CLK_SET_RATE_PARENT
, data
->clk_num
,
211 periph_clk_enb_refcnt
);