2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/clkdev.h>
22 #include <linux/of_address.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/clk/tegra.h>
30 #define CLK_SOURCE_I2S0 0x1d8
31 #define CLK_SOURCE_I2S1 0x100
32 #define CLK_SOURCE_I2S2 0x104
33 #define CLK_SOURCE_NDFLASH 0x160
34 #define CLK_SOURCE_I2S3 0x3bc
35 #define CLK_SOURCE_I2S4 0x3c0
36 #define CLK_SOURCE_SPDIF_OUT 0x108
37 #define CLK_SOURCE_SPDIF_IN 0x10c
38 #define CLK_SOURCE_PWM 0x110
39 #define CLK_SOURCE_ADX 0x638
40 #define CLK_SOURCE_ADX1 0x670
41 #define CLK_SOURCE_AMX 0x63c
42 #define CLK_SOURCE_AMX1 0x674
43 #define CLK_SOURCE_HDA 0x428
44 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
45 #define CLK_SOURCE_SBC1 0x134
46 #define CLK_SOURCE_SBC2 0x118
47 #define CLK_SOURCE_SBC3 0x11c
48 #define CLK_SOURCE_SBC4 0x1b4
49 #define CLK_SOURCE_SBC5 0x3c8
50 #define CLK_SOURCE_SBC6 0x3cc
51 #define CLK_SOURCE_SATA_OOB 0x420
52 #define CLK_SOURCE_SATA 0x424
53 #define CLK_SOURCE_NDSPEED 0x3f8
54 #define CLK_SOURCE_VFIR 0x168
55 #define CLK_SOURCE_SDMMC1 0x150
56 #define CLK_SOURCE_SDMMC2 0x154
57 #define CLK_SOURCE_SDMMC3 0x1bc
58 #define CLK_SOURCE_SDMMC4 0x164
59 #define CLK_SOURCE_CVE 0x140
60 #define CLK_SOURCE_TVO 0x188
61 #define CLK_SOURCE_TVDAC 0x194
62 #define CLK_SOURCE_VDE 0x1c8
63 #define CLK_SOURCE_CSITE 0x1d4
64 #define CLK_SOURCE_LA 0x1f8
65 #define CLK_SOURCE_TRACE 0x634
66 #define CLK_SOURCE_OWR 0x1cc
67 #define CLK_SOURCE_NOR 0x1d0
68 #define CLK_SOURCE_MIPI 0x174
69 #define CLK_SOURCE_I2C1 0x124
70 #define CLK_SOURCE_I2C2 0x198
71 #define CLK_SOURCE_I2C3 0x1b8
72 #define CLK_SOURCE_I2C4 0x3c4
73 #define CLK_SOURCE_I2C5 0x128
74 #define CLK_SOURCE_I2C6 0x65c
75 #define CLK_SOURCE_UARTA 0x178
76 #define CLK_SOURCE_UARTB 0x17c
77 #define CLK_SOURCE_UARTC 0x1a0
78 #define CLK_SOURCE_UARTD 0x1c0
79 #define CLK_SOURCE_UARTE 0x1c4
80 #define CLK_SOURCE_3D 0x158
81 #define CLK_SOURCE_2D 0x15c
82 #define CLK_SOURCE_MPE 0x170
83 #define CLK_SOURCE_UARTE 0x1c4
84 #define CLK_SOURCE_VI_SENSOR 0x1a8
85 #define CLK_SOURCE_VI 0x148
86 #define CLK_SOURCE_EPP 0x16c
87 #define CLK_SOURCE_MSENC 0x1f0
88 #define CLK_SOURCE_TSEC 0x1f4
89 #define CLK_SOURCE_HOST1X 0x180
90 #define CLK_SOURCE_HDMI 0x18c
91 #define CLK_SOURCE_DISP1 0x138
92 #define CLK_SOURCE_DISP2 0x13c
93 #define CLK_SOURCE_CILAB 0x614
94 #define CLK_SOURCE_CILCD 0x618
95 #define CLK_SOURCE_CILE 0x61c
96 #define CLK_SOURCE_DSIALP 0x620
97 #define CLK_SOURCE_DSIBLP 0x624
98 #define CLK_SOURCE_TSENSOR 0x3b8
99 #define CLK_SOURCE_D_AUDIO 0x3d0
100 #define CLK_SOURCE_DAM0 0x3d8
101 #define CLK_SOURCE_DAM1 0x3dc
102 #define CLK_SOURCE_DAM2 0x3e0
103 #define CLK_SOURCE_ACTMON 0x3e8
104 #define CLK_SOURCE_EXTERN1 0x3ec
105 #define CLK_SOURCE_EXTERN2 0x3f0
106 #define CLK_SOURCE_EXTERN3 0x3f4
107 #define CLK_SOURCE_I2CSLOW 0x3fc
108 #define CLK_SOURCE_SE 0x42c
109 #define CLK_SOURCE_MSELECT 0x3b4
110 #define CLK_SOURCE_DFLL_REF 0x62c
111 #define CLK_SOURCE_DFLL_SOC 0x630
112 #define CLK_SOURCE_SOC_THERM 0x644
113 #define CLK_SOURCE_XUSB_HOST_SRC 0x600
114 #define CLK_SOURCE_XUSB_FALCON_SRC 0x604
115 #define CLK_SOURCE_XUSB_FS_SRC 0x608
116 #define CLK_SOURCE_XUSB_SS_SRC 0x610
117 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
118 #define CLK_SOURCE_ISP 0x144
119 #define CLK_SOURCE_SOR0 0x414
120 #define CLK_SOURCE_DPAUX 0x418
121 #define CLK_SOURCE_SATA_OOB 0x420
122 #define CLK_SOURCE_SATA 0x424
123 #define CLK_SOURCE_ENTROPY 0x628
124 #define CLK_SOURCE_VI_SENSOR2 0x658
125 #define CLK_SOURCE_HDMI_AUDIO 0x668
126 #define CLK_SOURCE_VIC03 0x678
127 #define CLK_SOURCE_CLK72MHZ 0x66c
129 #define MASK(x) (BIT(x) - 1)
131 #define MUX(_name, _parents, _offset, \
132 _clk_num, _gate_flags, _clk_id) \
133 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
134 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
135 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
138 #define MUX_FLAGS(_name, _parents, _offset,\
139 _clk_num, _gate_flags, _clk_id, flags)\
140 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
141 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
142 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
145 #define MUX8(_name, _parents, _offset, \
146 _clk_num, _gate_flags, _clk_id) \
147 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
148 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
149 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
152 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \
153 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
154 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
155 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
156 _parents##_idx, 0, _lock)
158 #define INT(_name, _parents, _offset, \
159 _clk_num, _gate_flags, _clk_id) \
160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
161 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
162 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
163 _clk_id, _parents##_idx, 0, NULL)
165 #define INT_FLAGS(_name, _parents, _offset,\
166 _clk_num, _gate_flags, _clk_id, flags)\
167 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
168 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
169 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
170 _clk_id, _parents##_idx, flags, NULL)
172 #define INT8(_name, _parents, _offset,\
173 _clk_num, _gate_flags, _clk_id) \
174 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
175 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
176 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
177 _clk_id, _parents##_idx, 0, NULL)
179 #define UART(_name, _parents, _offset,\
181 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
182 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
183 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
184 _parents##_idx, 0, NULL)
186 #define I2C(_name, _parents, _offset,\
188 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
189 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
190 _clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
192 #define XUSB(_name, _parents, _offset, \
193 _clk_num, _gate_flags, _clk_id) \
194 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
195 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
196 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
197 _clk_id, _parents##_idx, 0, NULL)
199 #define AUDIO(_name, _offset, _clk_num,\
200 _gate_flags, _clk_id) \
201 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
202 _offset, 16, 0xE01F, 0, 0, 8, 1, \
203 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
204 _clk_id, mux_d_audio_clk_idx, 0, NULL)
206 #define NODIV(_name, _parents, _offset, \
207 _mux_shift, _mux_mask, _clk_num, \
208 _gate_flags, _clk_id, _lock) \
209 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
210 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
211 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
212 _clk_id, _parents##_idx, 0, _lock)
214 #define GATE(_name, _parent_name, \
215 _clk_num, _gate_flags, _clk_id, _flags) \
219 .p.parent_name = _parent_name, \
220 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
221 _clk_num, _gate_flags, 0, NULL), \
225 #define PLLP_BASE 0xa0
226 #define PLLP_MISC 0xac
227 #define PLLP_OUTA 0xa4
228 #define PLLP_OUTB 0xa8
229 #define PLLP_OUTC 0x67c
231 #define PLL_BASE_LOCK BIT(27)
232 #define PLL_MISC_LOCK_ENABLE 18
234 static DEFINE_SPINLOCK(PLLP_OUTA_lock
);
235 static DEFINE_SPINLOCK(PLLP_OUTB_lock
);
236 static DEFINE_SPINLOCK(PLLP_OUTC_lock
);
237 static DEFINE_SPINLOCK(sor0_lock
);
239 #define MUX_I2S_SPDIF(_id) \
240 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
243 MUX_I2S_SPDIF(audio0
)
244 MUX_I2S_SPDIF(audio1
)
245 MUX_I2S_SPDIF(audio2
)
246 MUX_I2S_SPDIF(audio3
)
247 MUX_I2S_SPDIF(audio4
)
250 #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
251 #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
252 #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
253 #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
254 #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
255 #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
257 static const char *mux_pllp_pllc_pllm_clkm
[] = {
258 "pll_p", "pll_c", "pll_m", "clk_m"
260 #define mux_pllp_pllc_pllm_clkm_idx NULL
262 static const char *mux_pllp_pllc_pllm
[] = { "pll_p", "pll_c", "pll_m" };
263 #define mux_pllp_pllc_pllm_idx NULL
265 static const char *mux_pllp_pllc_clk32_clkm
[] = {
266 "pll_p", "pll_c", "clk_32k", "clk_m"
268 #define mux_pllp_pllc_clk32_clkm_idx NULL
270 static const char *mux_plla_pllc_pllp_clkm
[] = {
271 "pll_a_out0", "pll_c", "pll_p", "clk_m"
273 #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
275 static const char *mux_pllp_pllc2_c_c3_pllm_clkm
[] = {
276 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
278 static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx
[] = {
279 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
282 static const char *mux_pllp_clkm
[] = {
285 static u32 mux_pllp_clkm_idx
[] = {
289 static const char *mux_pllm_pllc2_c_c3_pllp_plla
[] = {
290 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
292 #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
294 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm
[] = {
295 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
296 "pll_d2_out0", "clk_m"
298 #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
300 static const char *mux_pllm_pllc_pllp_plla
[] = {
301 "pll_m", "pll_c", "pll_p", "pll_a_out0"
303 #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
305 static const char *mux_pllp_pllc_clkm
[] = {
306 "pll_p", "pll_c", "pll_m"
308 static u32 mux_pllp_pllc_clkm_idx
[] = {
309 [0] = 0, [1] = 1, [2] = 3,
312 static const char *mux_pllp_pllc_clkm_clk32
[] = {
313 "pll_p", "pll_c", "clk_m", "clk_32k"
315 #define mux_pllp_pllc_clkm_clk32_idx NULL
317 static const char *mux_plla_clk32_pllp_clkm_plle
[] = {
318 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
320 #define mux_plla_clk32_pllp_clkm_plle_idx NULL
322 static const char *mux_clkm_pllp_pllc_pllre
[] = {
323 "clk_m", "pll_p", "pll_c", "pll_re_out"
325 static u32 mux_clkm_pllp_pllc_pllre_idx
[] = {
326 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
329 static const char *mux_clkm_48M_pllp_480M
[] = {
330 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
332 static u32 mux_clkm_48M_pllp_480M_idx
[] = {
333 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
336 static const char *mux_clkm_pllre_clk32_480M_pllc_ref
[] = {
337 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
339 static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx
[] = {
340 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
343 static const char *mux_ss_60M
[] = {
344 "xusb_ss_div2", "pll_u_60M"
346 #define mux_ss_60M_idx NULL
348 static const char *mux_d_audio_clk
[] = {
349 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
350 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
352 static u32 mux_d_audio_clk_idx
[] = {
353 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
354 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
357 static const char *mux_pllp_plld_pllc_clkm
[] = {
358 "pll_p", "pll_d_out0", "pll_c", "clk_m"
360 #define mux_pllp_plld_pllc_clkm_idx NULL
361 static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4
[] = {
362 "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4",
364 static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx
[] = {
365 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7,
368 static const char *mux_pllp_clkm1
[] = {
371 #define mux_pllp_clkm1_idx NULL
373 static const char *mux_pllp3_pllc_clkm
[] = {
374 "pll_p_out3", "pll_c", "pll_c2", "clk_m",
376 #define mux_pllp3_pllc_clkm_idx NULL
378 static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm
[] = {
379 "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
381 #define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
383 static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4
[] = {
384 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
386 static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx
[] = {
387 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
390 static const char *mux_clkm_plldp_sor0lvds
[] = {
391 "clk_m", "pll_dp", "sor0_lvds",
393 #define mux_clkm_plldp_sor0lvds_idx NULL
395 static struct tegra_periph_init_data periph_clks
[] = {
396 AUDIO("d_audio", CLK_SOURCE_D_AUDIO
, 106, TEGRA_PERIPH_ON_APB
, tegra_clk_d_audio
),
397 AUDIO("dam0", CLK_SOURCE_DAM0
, 108, TEGRA_PERIPH_ON_APB
, tegra_clk_dam0
),
398 AUDIO("dam1", CLK_SOURCE_DAM1
, 109, TEGRA_PERIPH_ON_APB
, tegra_clk_dam1
),
399 AUDIO("dam2", CLK_SOURCE_DAM2
, 110, TEGRA_PERIPH_ON_APB
, tegra_clk_dam2
),
400 I2C("i2c1", mux_pllp_clkm
, CLK_SOURCE_I2C1
, 12, tegra_clk_i2c1
),
401 I2C("i2c2", mux_pllp_clkm
, CLK_SOURCE_I2C2
, 54, tegra_clk_i2c2
),
402 I2C("i2c3", mux_pllp_clkm
, CLK_SOURCE_I2C3
, 67, tegra_clk_i2c3
),
403 I2C("i2c4", mux_pllp_clkm
, CLK_SOURCE_I2C4
, 103, tegra_clk_i2c4
),
404 I2C("i2c5", mux_pllp_clkm
, CLK_SOURCE_I2C5
, 47, tegra_clk_i2c5
),
405 INT("vde", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_VDE
, 61, 0, tegra_clk_vde
),
406 INT("vi", mux_pllm_pllc_pllp_plla
, CLK_SOURCE_VI
, 20, 0, tegra_clk_vi
),
407 INT("epp", mux_pllm_pllc_pllp_plla
, CLK_SOURCE_EPP
, 19, 0, tegra_clk_epp
),
408 INT("host1x", mux_pllm_pllc_pllp_plla
, CLK_SOURCE_HOST1X
, 28, 0, tegra_clk_host1x
),
409 INT("mpe", mux_pllm_pllc_pllp_plla
, CLK_SOURCE_MPE
, 60, 0, tegra_clk_mpe
),
410 INT("2d", mux_pllm_pllc_pllp_plla
, CLK_SOURCE_2D
, 21, 0, tegra_clk_gr2d
),
411 INT("3d", mux_pllm_pllc_pllp_plla
, CLK_SOURCE_3D
, 24, 0, tegra_clk_gr3d
),
412 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_VDE
, 61, 0, tegra_clk_vde_8
),
413 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla
, CLK_SOURCE_VI
, 20, 0, tegra_clk_vi_8
),
414 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4
, CLK_SOURCE_VI
, 20, 0, tegra_clk_vi_9
),
415 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla
, CLK_SOURCE_EPP
, 19, 0, tegra_clk_epp_8
),
416 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla
, CLK_SOURCE_MSENC
, 91, TEGRA_PERIPH_WAR_1005168
, tegra_clk_msenc
),
417 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_TSEC
, 83, 0, tegra_clk_tsec
),
418 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla
, CLK_SOURCE_HOST1X
, 28, 0, tegra_clk_host1x_8
),
419 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SE
, 127, TEGRA_PERIPH_ON_APB
, tegra_clk_se
),
420 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla
, CLK_SOURCE_2D
, 21, 0, tegra_clk_gr2d_8
),
421 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla
, CLK_SOURCE_3D
, 24, 0, tegra_clk_gr3d_8
),
422 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm
, CLK_SOURCE_VIC03
, 178, 0, tegra_clk_vic03
),
423 INT_FLAGS("mselect", mux_pllp_clkm
, CLK_SOURCE_MSELECT
, 99, 0, tegra_clk_mselect
, CLK_IGNORE_UNUSED
),
424 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm
, CLK_SOURCE_I2S0
, 30, TEGRA_PERIPH_ON_APB
, tegra_clk_i2s0
),
425 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm
, CLK_SOURCE_I2S1
, 11, TEGRA_PERIPH_ON_APB
, tegra_clk_i2s1
),
426 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm
, CLK_SOURCE_I2S2
, 18, TEGRA_PERIPH_ON_APB
, tegra_clk_i2s2
),
427 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm
, CLK_SOURCE_I2S3
, 101, TEGRA_PERIPH_ON_APB
, tegra_clk_i2s3
),
428 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm
, CLK_SOURCE_I2S4
, 102, TEGRA_PERIPH_ON_APB
, tegra_clk_i2s4
),
429 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm
, CLK_SOURCE_SPDIF_OUT
, 10, TEGRA_PERIPH_ON_APB
, tegra_clk_spdif_out
),
430 MUX("spdif_in", mux_pllp_pllc_pllm
, CLK_SOURCE_SPDIF_IN
, 10, TEGRA_PERIPH_ON_APB
, tegra_clk_spdif_in
),
431 MUX("pwm", mux_pllp_pllc_clk32_clkm
, CLK_SOURCE_PWM
, 17, TEGRA_PERIPH_ON_APB
, tegra_clk_pwm
),
432 MUX("adx", mux_plla_pllc_pllp_clkm
, CLK_SOURCE_ADX
, 154, TEGRA_PERIPH_ON_APB
, tegra_clk_adx
),
433 MUX("amx", mux_plla_pllc_pllp_clkm
, CLK_SOURCE_AMX
, 153, TEGRA_PERIPH_ON_APB
, tegra_clk_amx
),
434 MUX("hda", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_HDA
, 125, TEGRA_PERIPH_ON_APB
, tegra_clk_hda
),
435 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_HDA2CODEC_2X
, 111, TEGRA_PERIPH_ON_APB
, tegra_clk_hda2codec_2x
),
436 MUX("vfir", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_VFIR
, 7, TEGRA_PERIPH_ON_APB
, tegra_clk_vfir
),
437 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SDMMC1
, 14, 0, tegra_clk_sdmmc1
),
438 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SDMMC2
, 9, 0, tegra_clk_sdmmc2
),
439 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SDMMC3
, 69, 0, tegra_clk_sdmmc3
),
440 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SDMMC4
, 15, 0, tegra_clk_sdmmc4
),
441 MUX("la", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_LA
, 76, TEGRA_PERIPH_ON_APB
, tegra_clk_la
),
442 MUX("trace", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_TRACE
, 77, TEGRA_PERIPH_ON_APB
, tegra_clk_trace
),
443 MUX("owr", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_OWR
, 71, TEGRA_PERIPH_ON_APB
, tegra_clk_owr
),
444 MUX("nor", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_NOR
, 42, 0, tegra_clk_nor
),
445 MUX("mipi", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_MIPI
, 50, TEGRA_PERIPH_ON_APB
, tegra_clk_mipi
),
446 MUX("vi_sensor", mux_pllm_pllc_pllp_plla
, CLK_SOURCE_VI_SENSOR
, 20, TEGRA_PERIPH_NO_RESET
, tegra_clk_vi_sensor
),
447 MUX("cilab", mux_pllp_pllc_clkm
, CLK_SOURCE_CILAB
, 144, 0, tegra_clk_cilab
),
448 MUX("cilcd", mux_pllp_pllc_clkm
, CLK_SOURCE_CILCD
, 145, 0, tegra_clk_cilcd
),
449 MUX("cile", mux_pllp_pllc_clkm
, CLK_SOURCE_CILE
, 146, 0, tegra_clk_cile
),
450 MUX("dsialp", mux_pllp_pllc_clkm
, CLK_SOURCE_DSIALP
, 147, 0, tegra_clk_dsialp
),
451 MUX("dsiblp", mux_pllp_pllc_clkm
, CLK_SOURCE_DSIBLP
, 148, 0, tegra_clk_dsiblp
),
452 MUX("tsensor", mux_pllp_pllc_clkm_clk32
, CLK_SOURCE_TSENSOR
, 100, TEGRA_PERIPH_ON_APB
, tegra_clk_tsensor
),
453 MUX("actmon", mux_pllp_pllc_clk32_clkm
, CLK_SOURCE_ACTMON
, 119, 0, tegra_clk_actmon
),
454 MUX("dfll_ref", mux_pllp_clkm
, CLK_SOURCE_DFLL_REF
, 155, TEGRA_PERIPH_ON_APB
, tegra_clk_dfll_ref
),
455 MUX("dfll_soc", mux_pllp_clkm
, CLK_SOURCE_DFLL_SOC
, 155, TEGRA_PERIPH_ON_APB
, tegra_clk_dfll_soc
),
456 MUX("i2cslow", mux_pllp_pllc_clk32_clkm
, CLK_SOURCE_I2CSLOW
, 81, TEGRA_PERIPH_ON_APB
, tegra_clk_i2cslow
),
457 MUX("sbc1", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SBC1
, 41, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc1
),
458 MUX("sbc2", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SBC2
, 44, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc2
),
459 MUX("sbc3", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SBC3
, 46, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc3
),
460 MUX("sbc4", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SBC4
, 68, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc4
),
461 MUX("sbc5", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SBC5
, 104, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc5
),
462 MUX("sbc6", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SBC6
, 105, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc6
),
463 MUX("cve", mux_pllp_plld_pllc_clkm
, CLK_SOURCE_CVE
, 49, 0, tegra_clk_cve
),
464 MUX("tvo", mux_pllp_plld_pllc_clkm
, CLK_SOURCE_TVO
, 49, 0, tegra_clk_tvo
),
465 MUX("tvdac", mux_pllp_plld_pllc_clkm
, CLK_SOURCE_TVDAC
, 53, 0, tegra_clk_tvdac
),
466 MUX("ndflash", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_NDFLASH
, 13, TEGRA_PERIPH_ON_APB
, tegra_clk_ndflash
),
467 MUX("ndspeed", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_NDSPEED
, 80, TEGRA_PERIPH_ON_APB
, tegra_clk_ndspeed
),
468 MUX("sata_oob", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SATA_OOB
, 123, TEGRA_PERIPH_ON_APB
, tegra_clk_sata_oob
),
469 MUX("sata", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_SATA
, 124, TEGRA_PERIPH_ON_APB
, tegra_clk_sata
),
470 MUX("adx1", mux_plla_pllc_pllp_clkm
, CLK_SOURCE_ADX1
, 180, TEGRA_PERIPH_ON_APB
, tegra_clk_adx1
),
471 MUX("amx1", mux_plla_pllc_pllp_clkm
, CLK_SOURCE_AMX1
, 185, TEGRA_PERIPH_ON_APB
, tegra_clk_amx1
),
472 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla
, CLK_SOURCE_VI_SENSOR2
, 165, TEGRA_PERIPH_NO_RESET
, tegra_clk_vi_sensor2
),
473 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SDMMC1
, 14, 0, tegra_clk_sdmmc1_8
),
474 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SDMMC2
, 9, 0, tegra_clk_sdmmc2_8
),
475 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SDMMC3
, 69, 0, tegra_clk_sdmmc3_8
),
476 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SDMMC4
, 15, 0, tegra_clk_sdmmc4_8
),
477 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SBC1
, 41, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc1_8
),
478 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SBC2
, 44, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc2_8
),
479 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SBC3
, 46, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc3_8
),
480 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SBC4
, 68, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc4_8
),
481 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SBC5
, 104, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc5_8
),
482 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_SBC6
, 105, TEGRA_PERIPH_ON_APB
, tegra_clk_sbc6_8
),
483 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_NDFLASH
, 13, TEGRA_PERIPH_ON_APB
, tegra_clk_ndflash_8
),
484 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm
, CLK_SOURCE_NDSPEED
, 80, TEGRA_PERIPH_ON_APB
, tegra_clk_ndspeed_8
),
485 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm
, CLK_SOURCE_HDMI
, 51, 0, tegra_clk_hdmi
),
486 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle
, CLK_SOURCE_EXTERN1
, 120, 0, tegra_clk_extern1
),
487 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle
, CLK_SOURCE_EXTERN2
, 121, 0, tegra_clk_extern2
),
488 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle
, CLK_SOURCE_EXTERN3
, 122, 0, tegra_clk_extern3
),
489 MUX8("soc_therm", mux_pllm_pllc_pllp_plla
, CLK_SOURCE_SOC_THERM
, 78, TEGRA_PERIPH_ON_APB
, tegra_clk_soc_therm
),
490 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla
, CLK_SOURCE_VI_SENSOR
, 164, TEGRA_PERIPH_NO_RESET
, tegra_clk_vi_sensor_8
),
491 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4
, CLK_SOURCE_ISP
, 23, TEGRA_PERIPH_ON_APB
, tegra_clk_isp_8
),
492 MUX8("entropy", mux_pllp_clkm1
, CLK_SOURCE_ENTROPY
, 149, 0, tegra_clk_entropy
),
493 MUX8("hdmi_audio", mux_pllp3_pllc_clkm
, CLK_SOURCE_HDMI_AUDIO
, 176, TEGRA_PERIPH_NO_RESET
, tegra_clk_hdmi_audio
),
494 MUX8("clk72mhz", mux_pllp3_pllc_clkm
, CLK_SOURCE_CLK72MHZ
, 177, TEGRA_PERIPH_NO_RESET
, tegra_clk_clk72Mhz
),
495 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm
, CLK_SOURCE_SOR0
, tegra_clk_sor0_lvds
, &sor0_lock
),
496 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_CSITE
, 73, TEGRA_PERIPH_ON_APB
, tegra_clk_csite
, CLK_IGNORE_UNUSED
),
497 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm
, CLK_SOURCE_DISP1
, 29, 7, 27, 0, tegra_clk_disp1
, NULL
),
498 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm
, CLK_SOURCE_DISP2
, 29, 7, 26, 0, tegra_clk_disp2
, NULL
),
499 NODIV("sor0", mux_clkm_plldp_sor0lvds
, CLK_SOURCE_SOR0
, 14, 3, 182, 0, tegra_clk_sor0
, &sor0_lock
),
500 UART("uarta", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_UARTA
, 6, tegra_clk_uarta
),
501 UART("uartb", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_UARTB
, 7, tegra_clk_uartb
),
502 UART("uartc", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_UARTC
, 55, tegra_clk_uartc
),
503 UART("uartd", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_UARTD
, 65, tegra_clk_uartd
),
504 UART("uarte", mux_pllp_pllc_pllm_clkm
, CLK_SOURCE_UARTE
, 66, tegra_clk_uarte
),
505 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre
, CLK_SOURCE_XUSB_HOST_SRC
, 143, TEGRA_PERIPH_ON_APB
| TEGRA_PERIPH_NO_RESET
, tegra_clk_xusb_host_src
),
506 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre
, CLK_SOURCE_XUSB_FALCON_SRC
, 143, TEGRA_PERIPH_NO_RESET
, tegra_clk_xusb_falcon_src
),
507 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M
, CLK_SOURCE_XUSB_FS_SRC
, 143, TEGRA_PERIPH_NO_RESET
, tegra_clk_xusb_fs_src
),
508 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref
, CLK_SOURCE_XUSB_SS_SRC
, 143, TEGRA_PERIPH_NO_RESET
, tegra_clk_xusb_ss_src
),
509 NODIV("xusb_hs_src", mux_ss_60M
, CLK_SOURCE_XUSB_SS_SRC
, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET
, tegra_clk_xusb_hs_src
, NULL
),
510 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre
, CLK_SOURCE_XUSB_DEV_SRC
, 95, TEGRA_PERIPH_ON_APB
| TEGRA_PERIPH_NO_RESET
, tegra_clk_xusb_dev_src
),
513 static struct tegra_periph_init_data gate_clks
[] = {
514 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB
| TEGRA_PERIPH_NO_RESET
, tegra_clk_rtc
, 0),
515 GATE("timer", "clk_m", 5, 0, tegra_clk_timer
, 0),
516 GATE("isp", "clk_m", 23, 0, tegra_clk_isp
, 0),
517 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp
, 0),
518 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma
, 0),
519 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB
| TEGRA_PERIPH_NO_RESET
, tegra_clk_kbc
, 0),
520 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB
, tegra_clk_fuse
, 0),
521 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB
, tegra_clk_fuse_burn
, 0),
522 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB
, tegra_clk_kfuse
, 0),
523 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB
, tegra_clk_apbif
, 0),
524 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB
, tegra_clk_hda2hdmi
, 0),
525 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea
, 0),
526 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev
, 0),
527 GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal
, 0),
528 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd
, 0),
529 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2
, 0),
530 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3
, 0),
531 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi
, 0),
532 GATE("afi", "clk_m", 72, 0, tegra_clk_afi
, 0),
533 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET
, tegra_clk_csus
, 0),
534 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB
, tegra_clk_dds
, 0),
535 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB
, tegra_clk_dp2
, 0),
536 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB
, tegra_clk_dtv
, 0),
537 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host
, 0),
538 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss
, 0),
539 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev
, 0),
540 GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia
, 0),
541 GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib
, 0),
542 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc
, CLK_IGNORE_UNUSED
),
543 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB
, tegra_clk_sata_cold
, 0),
544 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb
, 0),
545 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk
, 0),
546 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie
, 0),
547 GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux
, 0),
548 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu
, 0),
551 struct pll_out_data
{
562 #define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
564 .div_name = "pll_p_out" #_num "_div",\
565 .pll_out_name = "pll_p_out" #_num,\
567 .div_shift = _div_shift,\
568 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
569 TEGRA_DIVIDER_ROUND_UP,\
570 .rst_shift = _rst_shift,\
571 .clk_id = tegra_clk_ ## _id,\
572 .lock = &_offset ##_lock,\
575 static struct pll_out_data pllp_out_clks
[] = {
576 PLL_OUT(1, PLLP_OUTA
, 8, 0, 0, pll_p_out1
),
577 PLL_OUT(2, PLLP_OUTA
, 24, 0, 16, pll_p_out2
),
578 PLL_OUT(2, PLLP_OUTA
, 24, TEGRA_DIVIDER_INT
, 16, pll_p_out2_int
),
579 PLL_OUT(3, PLLP_OUTB
, 8, 0, 0, pll_p_out3
),
580 PLL_OUT(4, PLLP_OUTB
, 24, 0, 16, pll_p_out4
),
581 PLL_OUT(5, PLLP_OUTC
, 24, 0, 16, pll_p_out5
),
584 static void __init
periph_clk_init(void __iomem
*clk_base
,
585 struct tegra_clk
*tegra_clks
)
591 for (i
= 0; i
< ARRAY_SIZE(periph_clks
); i
++) {
592 struct tegra_clk_periph_regs
*bank
;
593 struct tegra_periph_init_data
*data
;
595 data
= periph_clks
+ i
;
597 dt_clk
= tegra_lookup_dt_id(data
->clk_id
, tegra_clks
);
601 bank
= get_reg_bank(data
->periph
.gate
.clk_num
);
605 data
->periph
.gate
.regs
= bank
;
606 clk
= tegra_clk_register_periph(data
->name
,
607 data
->p
.parent_names
, data
->num_parents
,
608 &data
->periph
, clk_base
, data
->offset
,
614 static void __init
gate_clk_init(void __iomem
*clk_base
,
615 struct tegra_clk
*tegra_clks
)
621 for (i
= 0; i
< ARRAY_SIZE(gate_clks
); i
++) {
622 struct tegra_periph_init_data
*data
;
624 data
= gate_clks
+ i
;
626 dt_clk
= tegra_lookup_dt_id(data
->clk_id
, tegra_clks
);
630 clk
= tegra_clk_register_periph_gate(data
->name
,
631 data
->p
.parent_name
, data
->periph
.gate
.flags
,
632 clk_base
, data
->flags
,
633 data
->periph
.gate
.clk_num
,
634 periph_clk_enb_refcnt
);
639 static void __init
init_pllp(void __iomem
*clk_base
, void __iomem
*pmc_base
,
640 struct tegra_clk
*tegra_clks
,
641 struct tegra_clk_pll_params
*pll_params
)
647 dt_clk
= tegra_lookup_dt_id(tegra_clk_pll_p
, tegra_clks
);
650 clk
= tegra_clk_register_pll("pll_p", "pll_ref", clk_base
,
651 pmc_base
, 0, pll_params
, NULL
);
652 clk_register_clkdev(clk
, "pll_p", NULL
);
656 for (i
= 0; i
< ARRAY_SIZE(pllp_out_clks
); i
++) {
657 struct pll_out_data
*data
;
659 data
= pllp_out_clks
+ i
;
661 dt_clk
= tegra_lookup_dt_id(data
->clk_id
, tegra_clks
);
665 clk
= tegra_clk_register_divider(data
->div_name
, "pll_p",
666 clk_base
+ data
->offset
, 0, data
->div_flags
,
667 data
->div_shift
, 8, 1, data
->lock
);
668 clk
= tegra_clk_register_pll_out(data
->pll_out_name
,
669 data
->div_name
, clk_base
+ data
->offset
,
670 data
->rst_shift
+ 1, data
->rst_shift
,
671 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0,
677 void __init
tegra_periph_clk_init(void __iomem
*clk_base
,
678 void __iomem
*pmc_base
, struct tegra_clk
*tegra_clks
,
679 struct tegra_clk_pll_params
*pll_params
)
681 init_pllp(clk_base
, pmc_base
, tegra_clks
, pll_params
);
682 periph_clk_init(clk_base
, tegra_clks
);
683 gate_clk_init(clk_base
, tegra_clks
);