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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / clk / tegra / clk-tegra20.c
blob41272dcc9e225758da291018dc71bf921f85be8f
1 /*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/clkdev.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/tegra.h>
24 #include <linux/delay.h>
25 #include <dt-bindings/clock/tegra20-car.h>
26
27 #include "clk.h"
28 #include "clk-id.h"
29
30 #define OSC_CTRL 0x50
31 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
32 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
33 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
34 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
35 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
36 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
37
38 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
39 #define OSC_CTRL_PLL_REF_DIV_1 (0<<28)
40 #define OSC_CTRL_PLL_REF_DIV_2 (1<<28)
41 #define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
42
43 #define OSC_FREQ_DET 0x58
44 #define OSC_FREQ_DET_TRIG (1<<31)
45
46 #define OSC_FREQ_DET_STATUS 0x5c
47 #define OSC_FREQ_DET_BUSY (1<<31)
48 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
49
50 #define TEGRA20_CLK_PERIPH_BANKS 3
51
52 #define PLLS_BASE 0xf0
53 #define PLLS_MISC 0xf4
54 #define PLLC_BASE 0x80
55 #define PLLC_MISC 0x8c
56 #define PLLM_BASE 0x90
57 #define PLLM_MISC 0x9c
58 #define PLLP_BASE 0xa0
59 #define PLLP_MISC 0xac
60 #define PLLA_BASE 0xb0
61 #define PLLA_MISC 0xbc
62 #define PLLU_BASE 0xc0
63 #define PLLU_MISC 0xcc
64 #define PLLD_BASE 0xd0
65 #define PLLD_MISC 0xdc
66 #define PLLX_BASE 0xe0
67 #define PLLX_MISC 0xe4
68 #define PLLE_BASE 0xe8
69 #define PLLE_MISC 0xec
70
71 #define PLL_BASE_LOCK BIT(27)
72 #define PLLE_MISC_LOCK BIT(11)
73
74 #define PLL_MISC_LOCK_ENABLE 18
75 #define PLLDU_MISC_LOCK_ENABLE 22
76 #define PLLE_MISC_LOCK_ENABLE 9
77
78 #define PLLC_OUT 0x84
79 #define PLLM_OUT 0x94
80 #define PLLP_OUTA 0xa4
81 #define PLLP_OUTB 0xa8
82 #define PLLA_OUT 0xb4
83
84 #define CCLK_BURST_POLICY 0x20
85 #define SUPER_CCLK_DIVIDER 0x24
86 #define SCLK_BURST_POLICY 0x28
87 #define SUPER_SCLK_DIVIDER 0x2c
88 #define CLK_SYSTEM_RATE 0x30
89
90 #define CCLK_BURST_POLICY_SHIFT 28
91 #define CCLK_RUN_POLICY_SHIFT 4
92 #define CCLK_IDLE_POLICY_SHIFT 0
93 #define CCLK_IDLE_POLICY 1
94 #define CCLK_RUN_POLICY 2
95 #define CCLK_BURST_POLICY_PLLX 8
96
97 #define CLK_SOURCE_I2S1 0x100
98 #define CLK_SOURCE_I2S2 0x104
99 #define CLK_SOURCE_PWM 0x110
100 #define CLK_SOURCE_SPI 0x114
101 #define CLK_SOURCE_XIO 0x120
102 #define CLK_SOURCE_TWC 0x12c
103 #define CLK_SOURCE_IDE 0x144
104 #define CLK_SOURCE_HDMI 0x18c
105 #define CLK_SOURCE_DISP1 0x138
106 #define CLK_SOURCE_DISP2 0x13c
107 #define CLK_SOURCE_CSITE 0x1d4
108 #define CLK_SOURCE_I2C1 0x124
109 #define CLK_SOURCE_I2C2 0x198
110 #define CLK_SOURCE_I2C3 0x1b8
111 #define CLK_SOURCE_DVC 0x128
112 #define CLK_SOURCE_UARTA 0x178
113 #define CLK_SOURCE_UARTB 0x17c
114 #define CLK_SOURCE_UARTC 0x1a0
115 #define CLK_SOURCE_UARTD 0x1c0
116 #define CLK_SOURCE_UARTE 0x1c4
117 #define CLK_SOURCE_EMC 0x19c
118
119 #define AUDIO_SYNC_CLK 0x38
120
121 /* Tegra CPU clock and reset control regs */
122 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
123 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
124 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
125
126 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
127 #define CPU_RESET(cpu) (0x1111ul << (cpu))
128
129 #ifdef CONFIG_PM_SLEEP
130 static struct cpu_clk_suspend_context {
131 u32 pllx_misc;
132 u32 pllx_base;
133
134 u32 cpu_burst;
135 u32 clk_csite_src;
136 u32 cclk_divider;
137 } tegra20_cpu_clk_sctx;
138 #endif
139
140 static void __iomem *clk_base;
141 static void __iomem *pmc_base;
142
143 static DEFINE_SPINLOCK(emc_lock);
144
145 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
146 _clk_num, _gate_flags, _clk_id) \
147 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
148 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
149 _clk_num, \
150 _gate_flags, _clk_id)
151
152 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \
153 _clk_num, _gate_flags, _clk_id) \
154 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
155 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
156 _clk_num, _gate_flags, \
157 _clk_id)
158
159 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
160 _mux_shift, _mux_width, _clk_num, \
161 _gate_flags, _clk_id) \
162 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
163 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
164 _clk_num, _gate_flags, \
165 _clk_id)
166
167 static struct clk **clks;
168
169 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
170 { 12000000, 600000000, 600, 12, 0, 8 },
171 { 13000000, 600000000, 600, 13, 0, 8 },
172 { 19200000, 600000000, 500, 16, 0, 6 },
173 { 26000000, 600000000, 600, 26, 0, 8 },
174 { 0, 0, 0, 0, 0, 0 },
175 };
176
177 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
178 { 12000000, 666000000, 666, 12, 0, 8},
179 { 13000000, 666000000, 666, 13, 0, 8},
180 { 19200000, 666000000, 555, 16, 0, 8},
181 { 26000000, 666000000, 666, 26, 0, 8},
182 { 12000000, 600000000, 600, 12, 0, 8},
183 { 13000000, 600000000, 600, 13, 0, 8},
184 { 19200000, 600000000, 375, 12, 0, 6},
185 { 26000000, 600000000, 600, 26, 0, 8},
186 { 0, 0, 0, 0, 0, 0 },
187 };
188
189 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
190 { 12000000, 216000000, 432, 12, 1, 8},
191 { 13000000, 216000000, 432, 13, 1, 8},
192 { 19200000, 216000000, 90, 4, 1, 1},
193 { 26000000, 216000000, 432, 26, 1, 8},
194 { 12000000, 432000000, 432, 12, 0, 8},
195 { 13000000, 432000000, 432, 13, 0, 8},
196 { 19200000, 432000000, 90, 4, 0, 1},
197 { 26000000, 432000000, 432, 26, 0, 8},
198 { 0, 0, 0, 0, 0, 0 },
199 };
200
201 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
202 { 28800000, 56448000, 49, 25, 0, 1},
203 { 28800000, 73728000, 64, 25, 0, 1},
204 { 28800000, 24000000, 5, 6, 0, 1},
205 { 0, 0, 0, 0, 0, 0 },
206 };
207
208 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
209 { 12000000, 216000000, 216, 12, 0, 4},
210 { 13000000, 216000000, 216, 13, 0, 4},
211 { 19200000, 216000000, 135, 12, 0, 3},
212 { 26000000, 216000000, 216, 26, 0, 4},
213
214 { 12000000, 594000000, 594, 12, 0, 8},
215 { 13000000, 594000000, 594, 13, 0, 8},
216 { 19200000, 594000000, 495, 16, 0, 8},
217 { 26000000, 594000000, 594, 26, 0, 8},
218
219 { 12000000, 1000000000, 1000, 12, 0, 12},
220 { 13000000, 1000000000, 1000, 13, 0, 12},
221 { 19200000, 1000000000, 625, 12, 0, 8},
222 { 26000000, 1000000000, 1000, 26, 0, 12},
223
224 { 0, 0, 0, 0, 0, 0 },
225 };
226
227 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
228 { 12000000, 480000000, 960, 12, 0, 0},
229 { 13000000, 480000000, 960, 13, 0, 0},
230 { 19200000, 480000000, 200, 4, 0, 0},
231 { 26000000, 480000000, 960, 26, 0, 0},
232 { 0, 0, 0, 0, 0, 0 },
233 };
234
235 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
236 /* 1 GHz */
237 { 12000000, 1000000000, 1000, 12, 0, 12},
238 { 13000000, 1000000000, 1000, 13, 0, 12},
239 { 19200000, 1000000000, 625, 12, 0, 8},
240 { 26000000, 1000000000, 1000, 26, 0, 12},
241
242 /* 912 MHz */
243 { 12000000, 912000000, 912, 12, 0, 12},
244 { 13000000, 912000000, 912, 13, 0, 12},
245 { 19200000, 912000000, 760, 16, 0, 8},
246 { 26000000, 912000000, 912, 26, 0, 12},
247
248 /* 816 MHz */
249 { 12000000, 816000000, 816, 12, 0, 12},
250 { 13000000, 816000000, 816, 13, 0, 12},
251 { 19200000, 816000000, 680, 16, 0, 8},
252 { 26000000, 816000000, 816, 26, 0, 12},
253
254 /* 760 MHz */
255 { 12000000, 760000000, 760, 12, 0, 12},
256 { 13000000, 760000000, 760, 13, 0, 12},
257 { 19200000, 760000000, 950, 24, 0, 8},
258 { 26000000, 760000000, 760, 26, 0, 12},
259
260 /* 750 MHz */
261 { 12000000, 750000000, 750, 12, 0, 12},
262 { 13000000, 750000000, 750, 13, 0, 12},
263 { 19200000, 750000000, 625, 16, 0, 8},
264 { 26000000, 750000000, 750, 26, 0, 12},
265
266 /* 608 MHz */
267 { 12000000, 608000000, 608, 12, 0, 12},
268 { 13000000, 608000000, 608, 13, 0, 12},
269 { 19200000, 608000000, 380, 12, 0, 8},
270 { 26000000, 608000000, 608, 26, 0, 12},
271
272 /* 456 MHz */
273 { 12000000, 456000000, 456, 12, 0, 12},
274 { 13000000, 456000000, 456, 13, 0, 12},
275 { 19200000, 456000000, 380, 16, 0, 8},
276 { 26000000, 456000000, 456, 26, 0, 12},
277
278 /* 312 MHz */
279 { 12000000, 312000000, 312, 12, 0, 12},
280 { 13000000, 312000000, 312, 13, 0, 12},
281 { 19200000, 312000000, 260, 16, 0, 8},
282 { 26000000, 312000000, 312, 26, 0, 12},
283
284 { 0, 0, 0, 0, 0, 0 },
285 };
286
287 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
288 { 12000000, 100000000, 200, 24, 0, 0 },
289 { 0, 0, 0, 0, 0, 0 },
290 };
291
292 /* PLL parameters */
293 static struct tegra_clk_pll_params pll_c_params = {
294 .input_min = 2000000,
295 .input_max = 31000000,
296 .cf_min = 1000000,
297 .cf_max = 6000000,
298 .vco_min = 20000000,
299 .vco_max = 1400000000,
300 .base_reg = PLLC_BASE,
301 .misc_reg = PLLC_MISC,
302 .lock_mask = PLL_BASE_LOCK,
303 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
304 .lock_delay = 300,
305 .freq_table = pll_c_freq_table,
306 .flags = TEGRA_PLL_HAS_CPCON,
307 };
308
309 static struct tegra_clk_pll_params pll_m_params = {
310 .input_min = 2000000,
311 .input_max = 31000000,
312 .cf_min = 1000000,
313 .cf_max = 6000000,
314 .vco_min = 20000000,
315 .vco_max = 1200000000,
316 .base_reg = PLLM_BASE,
317 .misc_reg = PLLM_MISC,
318 .lock_mask = PLL_BASE_LOCK,
319 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
320 .lock_delay = 300,
321 .freq_table = pll_m_freq_table,
322 .flags = TEGRA_PLL_HAS_CPCON,
323 };
324
325 static struct tegra_clk_pll_params pll_p_params = {
326 .input_min = 2000000,
327 .input_max = 31000000,
328 .cf_min = 1000000,
329 .cf_max = 6000000,
330 .vco_min = 20000000,
331 .vco_max = 1400000000,
332 .base_reg = PLLP_BASE,
333 .misc_reg = PLLP_MISC,
334 .lock_mask = PLL_BASE_LOCK,
335 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
336 .lock_delay = 300,
337 .freq_table = pll_p_freq_table,
338 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON,
339 .fixed_rate = 216000000,
340 };
341
342 static struct tegra_clk_pll_params pll_a_params = {
343 .input_min = 2000000,
344 .input_max = 31000000,
345 .cf_min = 1000000,
346 .cf_max = 6000000,
347 .vco_min = 20000000,
348 .vco_max = 1400000000,
349 .base_reg = PLLA_BASE,
350 .misc_reg = PLLA_MISC,
351 .lock_mask = PLL_BASE_LOCK,
352 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
353 .lock_delay = 300,
354 .freq_table = pll_a_freq_table,
355 .flags = TEGRA_PLL_HAS_CPCON,
356 };
357
358 static struct tegra_clk_pll_params pll_d_params = {
359 .input_min = 2000000,
360 .input_max = 40000000,
361 .cf_min = 1000000,
362 .cf_max = 6000000,
363 .vco_min = 40000000,
364 .vco_max = 1000000000,
365 .base_reg = PLLD_BASE,
366 .misc_reg = PLLD_MISC,
367 .lock_mask = PLL_BASE_LOCK,
368 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
369 .lock_delay = 1000,
370 .freq_table = pll_d_freq_table,
371 .flags = TEGRA_PLL_HAS_CPCON,
372 };
373
374 static struct pdiv_map pllu_p[] = {
375 { .pdiv = 1, .hw_val = 1 },
376 { .pdiv = 2, .hw_val = 0 },
377 { .pdiv = 0, .hw_val = 0 },
378 };
379
380 static struct tegra_clk_pll_params pll_u_params = {
381 .input_min = 2000000,
382 .input_max = 40000000,
383 .cf_min = 1000000,
384 .cf_max = 6000000,
385 .vco_min = 48000000,
386 .vco_max = 960000000,
387 .base_reg = PLLU_BASE,
388 .misc_reg = PLLU_MISC,
389 .lock_mask = PLL_BASE_LOCK,
390 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
391 .lock_delay = 1000,
392 .pdiv_tohw = pllu_p,
393 .freq_table = pll_u_freq_table,
394 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
395 };
396
397 static struct tegra_clk_pll_params pll_x_params = {
398 .input_min = 2000000,
399 .input_max = 31000000,
400 .cf_min = 1000000,
401 .cf_max = 6000000,
402 .vco_min = 20000000,
403 .vco_max = 1200000000,
404 .base_reg = PLLX_BASE,
405 .misc_reg = PLLX_MISC,
406 .lock_mask = PLL_BASE_LOCK,
407 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
408 .lock_delay = 300,
409 .freq_table = pll_x_freq_table,
410 .flags = TEGRA_PLL_HAS_CPCON,
411 };
412
413 static struct tegra_clk_pll_params pll_e_params = {
414 .input_min = 12000000,
415 .input_max = 12000000,
416 .cf_min = 0,
417 .cf_max = 0,
418 .vco_min = 0,
419 .vco_max = 0,
420 .base_reg = PLLE_BASE,
421 .misc_reg = PLLE_MISC,
422 .lock_mask = PLLE_MISC_LOCK,
423 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
424 .lock_delay = 0,
425 .freq_table = pll_e_freq_table,
426 .flags = TEGRA_PLL_FIXED,
427 .fixed_rate = 100000000,
428 };
429
430 static struct tegra_devclk devclks[] __initdata = {
431 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
432 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
433 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
434 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
435 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
436 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
437 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
438 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
439 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
440 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
441 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
442 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
443 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
444 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
445 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
446 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
447 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
448 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
449 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
450 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
451 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
452 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
453 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
454 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
455 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
456 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
457 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
458 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
459 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
460 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
461 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
462 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
463 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
464 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
465 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
466 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
467 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
468 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
469 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
470 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
471 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
472 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
473 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
474 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
475 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
476 { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
477 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
478 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
479 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
480 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
481 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
482 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
483 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
484 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
485 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
486 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
487 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
488 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
489 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
490 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
491 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
492 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
493 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
494 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
495 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
496 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
497 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
498 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },
499 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
500 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
501 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
502 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
503 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
504 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
505 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
506 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
507 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
508 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
509 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
510 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
511 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
512 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
513 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
514 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
515 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
516 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
517 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
518 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
519 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
520 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
521 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
522 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
523 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
524 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
525 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
526 };
527
528 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
529 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
530 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
531 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
532 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
533 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
534 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
535 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
536 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
537 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
538 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
539 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
540 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
541 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
542 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
543 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
544 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
545 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
546 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
547 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
548 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
549 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
550 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
551 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
552 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
553 [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
554 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
555 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
556 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
557 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
558 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
559 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
560 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
561 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
562 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
563 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
564 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
565 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
566 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
567 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
568 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
569 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
570 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
571 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
572 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
573 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
574 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
575 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
576 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
577 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
578 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
579 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
580 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
581 };
582
583 static unsigned long tegra20_clk_measure_input_freq(void)
584 {
585 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
586 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
587 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
588 unsigned long input_freq;
589
590 switch (auto_clk_control) {
591 case OSC_CTRL_OSC_FREQ_12MHZ:
592 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
593 input_freq = 12000000;
594 break;
595 case OSC_CTRL_OSC_FREQ_13MHZ:
596 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
597 input_freq = 13000000;
598 break;
599 case OSC_CTRL_OSC_FREQ_19_2MHZ:
600 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
601 input_freq = 19200000;
602 break;
603 case OSC_CTRL_OSC_FREQ_26MHZ:
604 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
605 input_freq = 26000000;
606 break;
607 default:
608 pr_err("Unexpected clock autodetect value %d",
609 auto_clk_control);
610 BUG();
611 return 0;
612 }
613
614 return input_freq;
615 }
616
617 static unsigned int tegra20_get_pll_ref_div(void)
618 {
619 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
620 OSC_CTRL_PLL_REF_DIV_MASK;
621
622 switch (pll_ref_div) {
623 case OSC_CTRL_PLL_REF_DIV_1:
624 return 1;
625 case OSC_CTRL_PLL_REF_DIV_2:
626 return 2;
627 case OSC_CTRL_PLL_REF_DIV_4:
628 return 4;
629 default:
630 pr_err("Invalied pll ref divider %d\n", pll_ref_div);
631 BUG();
632 }
633 return 0;
634 }
635
636 static void tegra20_pll_init(void)
637 {
638 struct clk *clk;
639
640 /* PLLC */
641 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
642 &pll_c_params, NULL);
643 clks[TEGRA20_CLK_PLL_C] = clk;
644
645 /* PLLC_OUT1 */
646 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
647 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
648 8, 8, 1, NULL);
649 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
650 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
651 0, NULL);
652 clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
653
654 /* PLLM */
655 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
656 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
657 &pll_m_params, NULL);
658 clks[TEGRA20_CLK_PLL_M] = clk;
659
660 /* PLLM_OUT1 */
661 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
662 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
663 8, 8, 1, NULL);
664 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
665 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
666 CLK_SET_RATE_PARENT, 0, NULL);
667 clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
668
669 /* PLLX */
670 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
671 &pll_x_params, NULL);
672 clks[TEGRA20_CLK_PLL_X] = clk;
673
674 /* PLLU */
675 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
676 &pll_u_params, NULL);
677 clks[TEGRA20_CLK_PLL_U] = clk;
678
679 /* PLLD */
680 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
681 &pll_d_params, NULL);
682 clks[TEGRA20_CLK_PLL_D] = clk;
683
684 /* PLLD_OUT0 */
685 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
686 CLK_SET_RATE_PARENT, 1, 2);
687 clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
688
689 /* PLLA */
690 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
691 &pll_a_params, NULL);
692 clks[TEGRA20_CLK_PLL_A] = clk;
693
694 /* PLLA_OUT0 */
695 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
696 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
697 8, 8, 1, NULL);
698 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
699 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
700 CLK_SET_RATE_PARENT, 0, NULL);
701 clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
702
703 /* PLLE */
704 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
705 0, &pll_e_params, NULL);
706 clks[TEGRA20_CLK_PLL_E] = clk;
707 }
708
709 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
710 "pll_p", "pll_p_out4",
711 "pll_p_out3", "clk_d", "pll_x" };
712 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
713 "pll_p_out3", "pll_p_out2", "clk_d",
714 "clk_32k", "pll_m_out1" };
715
716 static void tegra20_super_clk_init(void)
717 {
718 struct clk *clk;
719
720 /* CCLK */
721 clk = tegra_clk_register_super_mux("cclk", cclk_parents,
722 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
723 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
724 clks[TEGRA20_CLK_CCLK] = clk;
725
726 /* SCLK */
727 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
728 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
729 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
730 clks[TEGRA20_CLK_SCLK] = clk;
731
732 /* twd */
733 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
734 clks[TEGRA20_CLK_TWD] = clk;
735 }
736
737 static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
738 "pll_a_out0", "unused", "unused",
739 "unused"};
740
741 static void __init tegra20_audio_clk_init(void)
742 {
743 struct clk *clk;
744
745 /* audio */
746 clk = clk_register_mux(NULL, "audio_mux", audio_parents,
747 ARRAY_SIZE(audio_parents),
748 CLK_SET_RATE_NO_REPARENT,
749 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
750 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
751 clk_base + AUDIO_SYNC_CLK, 4,
752 CLK_GATE_SET_TO_DISABLE, NULL);
753 clks[TEGRA20_CLK_AUDIO] = clk;
754
755 /* audio_2x */
756 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
757 CLK_SET_RATE_PARENT, 2, 1);
758 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
759 TEGRA_PERIPH_NO_RESET, clk_base,
760 CLK_SET_RATE_PARENT, 89,
761 periph_clk_enb_refcnt);
762 clks[TEGRA20_CLK_AUDIO_2X] = clk;
763
764 }
765
766 static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
767 "clk_m"};
768 static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
769 "clk_m"};
770 static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
771 "clk_32k"};
772 static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
773 static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
774 "clk_m"};
775 static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
776
777 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
778 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
779 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),
780 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
781 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO),
782 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
783 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE),
784 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
785 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
786 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
787 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
788 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI),
789 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),
790 };
791
792 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
793 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
794 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
795 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
796 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
797 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
798 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1),
799 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
800 };
801
802 static void __init tegra20_periph_clk_init(void)
803 {
804 struct tegra_periph_init_data *data;
805 struct clk *clk;
806 int i;
807
808 /* ac97 */
809 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
810 TEGRA_PERIPH_ON_APB,
811 clk_base, 0, 3, periph_clk_enb_refcnt);
812 clks[TEGRA20_CLK_AC97] = clk;
813
814 /* apbdma */
815 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
816 0, 34, periph_clk_enb_refcnt);
817 clks[TEGRA20_CLK_APBDMA] = clk;
818
819 /* emc */
820 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
821 ARRAY_SIZE(mux_pllmcp_clkm),
822 CLK_SET_RATE_NO_REPARENT,
823 clk_base + CLK_SOURCE_EMC,
824 30, 2, 0, &emc_lock);
825 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
826 57, periph_clk_enb_refcnt);
827 clks[TEGRA20_CLK_EMC] = clk;
828
829 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
830 &emc_lock);
831 clks[TEGRA20_CLK_MC] = clk;
832
833 /* dsi */
834 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
835 48, periph_clk_enb_refcnt);
836 clk_register_clkdev(clk, NULL, "dsi");
837 clks[TEGRA20_CLK_DSI] = clk;
838
839 /* pex */
840 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
841 periph_clk_enb_refcnt);
842 clks[TEGRA20_CLK_PEX] = clk;
843
844 /* cdev1 */
845 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
846 26000000);
847 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
848 clk_base, 0, 94, periph_clk_enb_refcnt);
849 clks[TEGRA20_CLK_CDEV1] = clk;
850
851 /* cdev2 */
852 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
853 26000000);
854 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
855 clk_base, 0, 93, periph_clk_enb_refcnt);
856 clks[TEGRA20_CLK_CDEV2] = clk;
857
858 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
859 data = &tegra_periph_clk_list[i];
860 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
861 data->num_parents, &data->periph,
862 clk_base, data->offset, data->flags);
863 clks[data->clk_id] = clk;
864 }
865
866 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
867 data = &tegra_periph_nodiv_clk_list[i];
868 clk = tegra_clk_register_periph_nodiv(data->name,
869 data->p.parent_names,
870 data->num_parents, &data->periph,
871 clk_base, data->offset);
872 clks[data->clk_id] = clk;
873 }
874
875 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
876 }
877
878 static void __init tegra20_osc_clk_init(void)
879 {
880 struct clk *clk;
881 unsigned long input_freq;
882 unsigned int pll_ref_div;
883
884 input_freq = tegra20_clk_measure_input_freq();
885
886 /* clk_m */
887 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |
888 CLK_IGNORE_UNUSED, input_freq);
889 clks[TEGRA20_CLK_CLK_M] = clk;
890
891 /* pll_ref */
892 pll_ref_div = tegra20_get_pll_ref_div();
893 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
894 CLK_SET_RATE_PARENT, 1, pll_ref_div);
895 clks[TEGRA20_CLK_PLL_REF] = clk;
896 }
897
898 /* Tegra20 CPU clock and reset control functions */
899 static void tegra20_wait_cpu_in_reset(u32 cpu)
900 {
901 unsigned int reg;
902
903 do {
904 reg = readl(clk_base +
905 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
906 cpu_relax();
907 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
908
909 return;
910 }
911
912 static void tegra20_put_cpu_in_reset(u32 cpu)
913 {
914 writel(CPU_RESET(cpu),
915 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
916 dmb();
917 }
918
919 static void tegra20_cpu_out_of_reset(u32 cpu)
920 {
921 writel(CPU_RESET(cpu),
922 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
923 wmb();
924 }
925
926 static void tegra20_enable_cpu_clock(u32 cpu)
927 {
928 unsigned int reg;
929
930 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
931 writel(reg & ~CPU_CLOCK(cpu),
932 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
933 barrier();
934 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
935 }
936
937 static void tegra20_disable_cpu_clock(u32 cpu)
938 {
939 unsigned int reg;
940
941 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
942 writel(reg | CPU_CLOCK(cpu),
943 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
944 }
945
946 #ifdef CONFIG_PM_SLEEP
947 static bool tegra20_cpu_rail_off_ready(void)
948 {
949 unsigned int cpu_rst_status;
950
951 cpu_rst_status = readl(clk_base +
952 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
953
954 return !!(cpu_rst_status & 0x2);
955 }
956
957 static void tegra20_cpu_clock_suspend(void)
958 {
959 /* switch coresite to clk_m, save off original source */
960 tegra20_cpu_clk_sctx.clk_csite_src =
961 readl(clk_base + CLK_SOURCE_CSITE);
962 writel(3<<30, clk_base + CLK_SOURCE_CSITE);
963
964 tegra20_cpu_clk_sctx.cpu_burst =
965 readl(clk_base + CCLK_BURST_POLICY);
966 tegra20_cpu_clk_sctx.pllx_base =
967 readl(clk_base + PLLX_BASE);
968 tegra20_cpu_clk_sctx.pllx_misc =
969 readl(clk_base + PLLX_MISC);
970 tegra20_cpu_clk_sctx.cclk_divider =
971 readl(clk_base + SUPER_CCLK_DIVIDER);
972 }
973
974 static void tegra20_cpu_clock_resume(void)
975 {
976 unsigned int reg, policy;
977
978 /* Is CPU complex already running on PLLX? */
979 reg = readl(clk_base + CCLK_BURST_POLICY);
980 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF;
981
982 if (policy == CCLK_IDLE_POLICY)
983 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF;
984 else if (policy == CCLK_RUN_POLICY)
985 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF;
986 else
987 BUG();
988
989 if (reg != CCLK_BURST_POLICY_PLLX) {
990 /* restore PLLX settings if CPU is on different PLL */
991 writel(tegra20_cpu_clk_sctx.pllx_misc,
992 clk_base + PLLX_MISC);
993 writel(tegra20_cpu_clk_sctx.pllx_base,
994 clk_base + PLLX_BASE);
995
996 /* wait for PLL stabilization if PLLX was enabled */
997 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
998 udelay(300);
999 }
1000
1001 /*
1002 * Restore original burst policy setting for calls resulting from CPU
1003 * LP2 in idle or system suspend.
1004 */
1005 writel(tegra20_cpu_clk_sctx.cclk_divider,
1006 clk_base + SUPER_CCLK_DIVIDER);
1007 writel(tegra20_cpu_clk_sctx.cpu_burst,
1008 clk_base + CCLK_BURST_POLICY);
1009
1010 writel(tegra20_cpu_clk_sctx.clk_csite_src,
1011 clk_base + CLK_SOURCE_CSITE);
1012 }
1013 #endif
1014
1015 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1016 .wait_for_reset = tegra20_wait_cpu_in_reset,
1017 .put_in_reset = tegra20_put_cpu_in_reset,
1018 .out_of_reset = tegra20_cpu_out_of_reset,
1019 .enable_clock = tegra20_enable_cpu_clock,
1020 .disable_clock = tegra20_disable_cpu_clock,
1021 #ifdef CONFIG_PM_SLEEP
1022 .rail_off_ready = tegra20_cpu_rail_off_ready,
1023 .suspend = tegra20_cpu_clock_suspend,
1024 .resume = tegra20_cpu_clock_resume,
1025 #endif
1026 };
1027
1028 static struct tegra_clk_init_table init_table[] __initdata = {
1029 {TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1},
1030 {TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1},
1031 {TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1},
1032 {TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1},
1033 {TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1},
1034 {TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1},
1035 {TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1},
1036 {TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1},
1037 {TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1038 {TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1},
1039 {TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1},
1040 {TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1},
1041 {TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1042 {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0},
1043 {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0},
1044 {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0},
1045 {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0},
1046 {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},
1047 {TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1},
1048 {TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1},
1049 {TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1},
1050 {TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1},
1051 {TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1052 {TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1053 {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0},
1054 {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0},
1055 {TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0},
1056 {TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0},
1057 {TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0},
1058 {TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0},
1059 {TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0},
1060 {TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0},
1061 {TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0},
1062 {TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0},
1063 {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0},
1064 {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0},
1065 {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0},
1066 {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */
1067 };
1068
1069 static void __init tegra20_clock_apply_init_table(void)
1070 {
1071 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1072 }
1073
1074 /*
1075 * Some clocks may be used by different drivers depending on the board
1076 * configuration. List those here to register them twice in the clock lookup
1077 * table under two names.
1078 */
1079 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1080 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
1081 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
1082 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
1083 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
1084 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */
1085 };
1086
1087 static const struct of_device_id pmc_match[] __initconst = {
1088 { .compatible = "nvidia,tegra20-pmc" },
1089 {},
1090 };
1091
1092 static void __init tegra20_clock_init(struct device_node *np)
1093 {
1094 struct device_node *node;
1095
1096 clk_base = of_iomap(np, 0);
1097 if (!clk_base) {
1098 pr_err("Can't map CAR registers\n");
1099 BUG();
1100 }
1101
1102 node = of_find_matching_node(NULL, pmc_match);
1103 if (!node) {
1104 pr_err("Failed to find pmc node\n");
1105 BUG();
1106 }
1107
1108 pmc_base = of_iomap(node, 0);
1109 if (!pmc_base) {
1110 pr_err("Can't map pmc registers\n");
1111 BUG();
1112 }
1113
1114 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
1115 TEGRA20_CLK_PERIPH_BANKS);
1116 if (!clks)
1117 return;
1118
1119 tegra20_osc_clk_init();
1120 tegra_fixed_clk_init(tegra20_clks);
1121 tegra20_pll_init();
1122 tegra20_super_clk_init();
1123 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
1124 tegra20_periph_clk_init();
1125 tegra20_audio_clk_init();
1126 tegra_pmc_clk_init(pmc_base, tegra20_clks);
1127
1128 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
1129
1130 tegra_add_of_provider(np);
1131 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1132
1133 tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
1134
1135 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1136 }
1137 CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
Linux with added FPC-III support