drivers/clocksource/tegra20_timer.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@google.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/err.h>
  20 #include <linux/time.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/clockchips.h>
  24 #include <linux/clocksource.h>
  25 #include <linux/clk.h>
  26 #include <linux/io.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/sched_clock.h>
  30 #include <linux/delay.h>
  31
  32 #include <asm/mach/time.h>
  33 #include <asm/smp_twd.h>
  34
  35 #define RTC_SECONDS            0x08
  36 #define RTC_SHADOW_SECONDS     0x0c
  37 #define RTC_MILLISECONDS       0x10
  38
  39 #define TIMERUS_CNTR_1US 0x10
  40 #define TIMERUS_USEC_CFG 0x14
  41 #define TIMERUS_CNTR_FREEZE 0x4c
  42
  43 #define TIMER1_BASE 0x0
  44 #define TIMER2_BASE 0x8
  45 #define TIMER3_BASE 0x50
  46 #define TIMER4_BASE 0x58
  47
  48 #define TIMER_PTV 0x0
  49 #define TIMER_PCR 0x4
  50
  51 static void __iomem *timer_reg_base;
  52 static void __iomem *rtc_base;
  53
  54 static struct timespec persistent_ts;
  55 static u64 persistent_ms, last_persistent_ms;
  56
  57 static struct delay_timer tegra_delay_timer;
  58
  59 #define timer_writel(value, reg) \
  60         __raw_writel(value, timer_reg_base + (reg))
  61 #define timer_readl(reg) \
  62         __raw_readl(timer_reg_base + (reg))
  63
  64 static int tegra_timer_set_next_event(unsigned long cycles,
  65                                          struct clock_event_device *evt)
  66 {
  67         u32 reg;
  68
  69         reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
  70         timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  71
  72         return 0;
  73 }
  74
  75 static void tegra_timer_set_mode(enum clock_event_mode mode,
  76                                     struct clock_event_device *evt)
  77 {
  78         u32 reg;
  79
  80         timer_writel(0, TIMER3_BASE + TIMER_PTV);
  81
  82         switch (mode) {
  83         case CLOCK_EVT_MODE_PERIODIC:
  84                 reg = 0xC0000000 | ((1000000/HZ)-1);
  85                 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  86                 break;
  87         case CLOCK_EVT_MODE_ONESHOT:
  88                 break;
  89         case CLOCK_EVT_MODE_UNUSED:
  90         case CLOCK_EVT_MODE_SHUTDOWN:
  91         case CLOCK_EVT_MODE_RESUME:
  92                 break;
  93         }
  94 }
  95
  96 static struct clock_event_device tegra_clockevent = {
  97         .name           = "timer0",
  98         .rating         = 300,
  99         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 100         .set_next_event = tegra_timer_set_next_event,
 101         .set_mode       = tegra_timer_set_mode,
 102 };
 103
 104 static u64 notrace tegra_read_sched_clock(void)
 105 {
 106         return timer_readl(TIMERUS_CNTR_1US);
 107 }
 108
 109 /*
 110  * tegra_rtc_read - Reads the Tegra RTC registers
 111  * Care must be taken that this funciton is not called while the
 112  * tegra_rtc driver could be executing to avoid race conditions
 113  * on the RTC shadow register
 114  */
 115 static u64 tegra_rtc_read_ms(void)
 116 {
 117         u32 ms = readl(rtc_base + RTC_MILLISECONDS);
 118         u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
 119         return (u64)s * MSEC_PER_SEC + ms;
 120 }
 121
 122 /*
 123  * tegra_read_persistent_clock -  Return time from a persistent clock.
 124  *
 125  * Reads the time from a source which isn't disabled during PM, the
 126  * 32k sync timer.  Convert the cycles elapsed since last read into
 127  * nsecs and adds to a monotonically increasing timespec.
 128  * Care must be taken that this funciton is not called while the
 129  * tegra_rtc driver could be executing to avoid race conditions
 130  * on the RTC shadow register
 131  */
 132 static void tegra_read_persistent_clock(struct timespec *ts)
 133 {
 134         u64 delta;
 135         struct timespec *tsp = &persistent_ts;
 136
 137         last_persistent_ms = persistent_ms;
 138         persistent_ms = tegra_rtc_read_ms();
 139         delta = persistent_ms - last_persistent_ms;
 140
 141         timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
 142         *ts = *tsp;
 143 }
 144
 145 static unsigned long tegra_delay_timer_read_counter_long(void)
 146 {
 147         return readl(timer_reg_base + TIMERUS_CNTR_1US);
 148 }
 149
 150 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
 151 {
 152         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 153         timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
 154         evt->event_handler(evt);
 155         return IRQ_HANDLED;
 156 }
 157
 158 static struct irqaction tegra_timer_irq = {
 159         .name           = "timer0",
 160         .flags          = IRQF_TIMER | IRQF_TRIGGER_HIGH,
 161         .handler        = tegra_timer_interrupt,
 162         .dev_id         = &tegra_clockevent,
 163 };
 164
 165 static void __init tegra20_init_timer(struct device_node *np)
 166 {
 167         struct clk *clk;
 168         unsigned long rate;
 169         int ret;
 170
 171         timer_reg_base = of_iomap(np, 0);
 172         if (!timer_reg_base) {
 173                 pr_err("Can't map timer registers\n");
 174                 BUG();
 175         }
 176
 177         tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
 178         if (tegra_timer_irq.irq <= 0) {
 179                 pr_err("Failed to map timer IRQ\n");
 180                 BUG();
 181         }
 182
 183         clk = of_clk_get(np, 0);
 184         if (IS_ERR(clk)) {
 185                 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
 186                 rate = 12000000;
 187         } else {
 188                 clk_prepare_enable(clk);
 189                 rate = clk_get_rate(clk);
 190         }
 191
 192         switch (rate) {
 193         case 12000000:
 194                 timer_writel(0x000b, TIMERUS_USEC_CFG);
 195                 break;
 196         case 13000000:
 197                 timer_writel(0x000c, TIMERUS_USEC_CFG);
 198                 break;
 199         case 19200000:
 200                 timer_writel(0x045f, TIMERUS_USEC_CFG);
 201                 break;
 202         case 26000000:
 203                 timer_writel(0x0019, TIMERUS_USEC_CFG);
 204                 break;
 205         default:
 206                 WARN(1, "Unknown clock rate");
 207         }
 208
 209         sched_clock_register(tegra_read_sched_clock, 32, 1000000);
 210
 211         if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
 212                 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
 213                 pr_err("Failed to register clocksource\n");
 214                 BUG();
 215         }
 216
 217         tegra_delay_timer.read_current_timer =
 218                         tegra_delay_timer_read_counter_long;
 219         tegra_delay_timer.freq = 1000000;
 220         register_current_timer_delay(&tegra_delay_timer);
 221
 222         ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
 223         if (ret) {
 224                 pr_err("Failed to register timer IRQ: %d\n", ret);
 225                 BUG();
 226         }
 227
 228         tegra_clockevent.cpumask = cpu_all_mask;
 229         tegra_clockevent.irq = tegra_timer_irq.irq;
 230         clockevents_config_and_register(&tegra_clockevent, 1000000,
 231                                         0x1, 0x1fffffff);
 232 }
 233 CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
 234
 235 static void __init tegra20_init_rtc(struct device_node *np)
 236 {
 237         struct clk *clk;
 238
 239         rtc_base = of_iomap(np, 0);
 240         if (!rtc_base) {
 241                 pr_err("Can't map RTC registers");
 242                 BUG();
 243         }
 244
 245         /*
 246          * rtc registers are used by read_persistent_clock, keep the rtc clock
 247          * enabled
 248          */
 249         clk = of_clk_get(np, 0);
 250         if (IS_ERR(clk))
 251                 pr_warn("Unable to get rtc-tegra clock\n");
 252         else
 253                 clk_prepare_enable(clk);
 254
 255         register_persistent_clock(NULL, tegra_read_persistent_clock);
 256 }
 257 CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
 258
 259 #ifdef CONFIG_PM
 260 static u32 usec_config;
 261
 262 void tegra_timer_suspend(void)
 263 {
 264         usec_config = timer_readl(TIMERUS_USEC_CFG);
 265 }
 266
 267 void tegra_timer_resume(void)
 268 {
 269         timer_writel(usec_config, TIMERUS_USEC_CFG);
 270 }
 271 #endif