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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / irqchip / irq-armada-370-xp.c
blob463c235acbdcdc1758329205e3c79e380b5fa7a6
1 /*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/cpu.h>
23 #include <linux/io.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/irqdomain.h>
28 #include <linux/slab.h>
29 #include <linux/syscore_ops.h>
30 #include <linux/msi.h>
31 #include <asm/mach/arch.h>
32 #include <asm/exception.h>
33 #include <asm/smp_plat.h>
34 #include <asm/mach/irq.h>
35
36 #include "irqchip.h"
37
38 /* Interrupt Controller Registers Map */
39 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
40 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
41
42 #define ARMADA_370_XP_INT_CONTROL (0x00)
43 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
44 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
45 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
46 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
47 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
48
49 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
50 #define ARMADA_375_PPI_CAUSE (0x10)
51
52 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
53 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
54 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
55
56 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
57
58 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
59
60 #define IPI_DOORBELL_START (0)
61 #define IPI_DOORBELL_END (8)
62 #define IPI_DOORBELL_MASK 0xFF
63 #define PCI_MSI_DOORBELL_START (16)
64 #define PCI_MSI_DOORBELL_NR (16)
65 #define PCI_MSI_DOORBELL_END (32)
66 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
67
68 static void __iomem *per_cpu_int_base;
69 static void __iomem *main_int_base;
70 static struct irq_domain *armada_370_xp_mpic_domain;
71 static u32 doorbell_mask_reg;
72 #ifdef CONFIG_PCI_MSI
73 static struct irq_domain *armada_370_xp_msi_domain;
74 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
75 static DEFINE_MUTEX(msi_used_lock);
76 static phys_addr_t msi_doorbell_addr;
77 #endif
78
79 /*
80 * In SMP mode:
81 * For shared global interrupts, mask/unmask global enable bit
82 * For CPU interrupts, mask/unmask the calling CPU's bit
83 */
84 static void armada_370_xp_irq_mask(struct irq_data *d)
85 {
86 irq_hw_number_t hwirq = irqd_to_hwirq(d);
87
88 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
89 writel(hwirq, main_int_base +
90 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
91 else
92 writel(hwirq, per_cpu_int_base +
93 ARMADA_370_XP_INT_SET_MASK_OFFS);
94 }
95
96 static void armada_370_xp_irq_unmask(struct irq_data *d)
97 {
98 irq_hw_number_t hwirq = irqd_to_hwirq(d);
99
100 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
101 writel(hwirq, main_int_base +
102 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
103 else
104 writel(hwirq, per_cpu_int_base +
105 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
106 }
107
108 #ifdef CONFIG_PCI_MSI
109
110 static int armada_370_xp_alloc_msi(void)
111 {
112 int hwirq;
113
114 mutex_lock(&msi_used_lock);
115 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
116 if (hwirq >= PCI_MSI_DOORBELL_NR)
117 hwirq = -ENOSPC;
118 else
119 set_bit(hwirq, msi_used);
120 mutex_unlock(&msi_used_lock);
121
122 return hwirq;
123 }
124
125 static void armada_370_xp_free_msi(int hwirq)
126 {
127 mutex_lock(&msi_used_lock);
128 if (!test_bit(hwirq, msi_used))
129 pr_err("trying to free unused MSI#%d\n", hwirq);
130 else
131 clear_bit(hwirq, msi_used);
132 mutex_unlock(&msi_used_lock);
133 }
134
135 static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
136 struct pci_dev *pdev,
137 struct msi_desc *desc)
138 {
139 struct msi_msg msg;
140 int virq, hwirq;
141
142 /* We support MSI, but not MSI-X */
143 if (desc->msi_attrib.is_msix)
144 return -EINVAL;
145
146 hwirq = armada_370_xp_alloc_msi();
147 if (hwirq < 0)
148 return hwirq;
149
150 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
151 if (!virq) {
152 armada_370_xp_free_msi(hwirq);
153 return -EINVAL;
154 }
155
156 irq_set_msi_desc(virq, desc);
157
158 msg.address_lo = msi_doorbell_addr;
159 msg.address_hi = 0;
160 msg.data = 0xf00 | (hwirq + 16);
161
162 pci_write_msi_msg(virq, &msg);
163 return 0;
164 }
165
166 static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
167 unsigned int irq)
168 {
169 struct irq_data *d = irq_get_irq_data(irq);
170 unsigned long hwirq = d->hwirq;
171
172 irq_dispose_mapping(irq);
173 armada_370_xp_free_msi(hwirq);
174 }
175
176 static struct irq_chip armada_370_xp_msi_irq_chip = {
177 .name = "armada_370_xp_msi_irq",
178 .irq_enable = pci_msi_unmask_irq,
179 .irq_disable = pci_msi_mask_irq,
180 .irq_mask = pci_msi_mask_irq,
181 .irq_unmask = pci_msi_unmask_irq,
182 };
183
184 static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
185 irq_hw_number_t hw)
186 {
187 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
188 handle_simple_irq);
189 set_irq_flags(virq, IRQF_VALID);
190
191 return 0;
192 }
193
194 static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
195 .map = armada_370_xp_msi_map,
196 };
197
198 static int armada_370_xp_msi_init(struct device_node *node,
199 phys_addr_t main_int_phys_base)
200 {
201 struct msi_controller *msi_chip;
202 u32 reg;
203 int ret;
204
205 msi_doorbell_addr = main_int_phys_base +
206 ARMADA_370_XP_SW_TRIG_INT_OFFS;
207
208 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
209 if (!msi_chip)
210 return -ENOMEM;
211
212 msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
213 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
214 msi_chip->of_node = node;
215
216 armada_370_xp_msi_domain =
217 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
218 &armada_370_xp_msi_irq_ops,
219 NULL);
220 if (!armada_370_xp_msi_domain) {
221 kfree(msi_chip);
222 return -ENOMEM;
223 }
224
225 ret = of_pci_msi_chip_add(msi_chip);
226 if (ret < 0) {
227 irq_domain_remove(armada_370_xp_msi_domain);
228 kfree(msi_chip);
229 return ret;
230 }
231
232 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
233 | PCI_MSI_DOORBELL_MASK;
234
235 writel(reg, per_cpu_int_base +
236 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
237
238 /* Unmask IPI interrupt */
239 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
240
241 return 0;
242 }
243 #else
244 static inline int armada_370_xp_msi_init(struct device_node *node,
245 phys_addr_t main_int_phys_base)
246 {
247 return 0;
248 }
249 #endif
250
251 #ifdef CONFIG_SMP
252 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
253
254 static int armada_xp_set_affinity(struct irq_data *d,
255 const struct cpumask *mask_val, bool force)
256 {
257 irq_hw_number_t hwirq = irqd_to_hwirq(d);
258 unsigned long reg, mask;
259 int cpu;
260
261 /* Select a single core from the affinity mask which is online */
262 cpu = cpumask_any_and(mask_val, cpu_online_mask);
263 mask = 1UL << cpu_logical_map(cpu);
264
265 raw_spin_lock(&irq_controller_lock);
266 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
267 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
268 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
269 raw_spin_unlock(&irq_controller_lock);
270
271 return IRQ_SET_MASK_OK;
272 }
273 #endif
274
275 static struct irq_chip armada_370_xp_irq_chip = {
276 .name = "armada_370_xp_irq",
277 .irq_mask = armada_370_xp_irq_mask,
278 .irq_mask_ack = armada_370_xp_irq_mask,
279 .irq_unmask = armada_370_xp_irq_unmask,
280 #ifdef CONFIG_SMP
281 .irq_set_affinity = armada_xp_set_affinity,
282 #endif
283 };
284
285 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
286 unsigned int virq, irq_hw_number_t hw)
287 {
288 armada_370_xp_irq_mask(irq_get_irq_data(virq));
289 if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
290 writel(hw, per_cpu_int_base +
291 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
292 else
293 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
294 irq_set_status_flags(virq, IRQ_LEVEL);
295
296 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
297 irq_set_percpu_devid(virq);
298 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
299 handle_percpu_devid_irq);
300
301 } else {
302 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
303 handle_level_irq);
304 }
305 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
306
307 return 0;
308 }
309
310 #ifdef CONFIG_SMP
311 static void armada_mpic_send_doorbell(const struct cpumask *mask,
312 unsigned int irq)
313 {
314 int cpu;
315 unsigned long map = 0;
316
317 /* Convert our logical CPU mask into a physical one. */
318 for_each_cpu(cpu, mask)
319 map |= 1 << cpu_logical_map(cpu);
320
321 /*
322 * Ensure that stores to Normal memory are visible to the
323 * other CPUs before issuing the IPI.
324 */
325 dsb();
326
327 /* submit softirq */
328 writel((map << 8) | irq, main_int_base +
329 ARMADA_370_XP_SW_TRIG_INT_OFFS);
330 }
331
332 static void armada_xp_mpic_smp_cpu_init(void)
333 {
334 u32 control;
335 int nr_irqs, i;
336
337 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
338 nr_irqs = (control >> 2) & 0x3ff;
339
340 for (i = 0; i < nr_irqs; i++)
341 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
342
343 /* Clear pending IPIs */
344 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
345
346 /* Enable first 8 IPIs */
347 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
348 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
349
350 /* Unmask IPI interrupt */
351 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
352 }
353
354 static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
355 unsigned long action, void *hcpu)
356 {
357 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
358 armada_xp_mpic_smp_cpu_init();
359 return NOTIFY_OK;
360 }
361
362 static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
363 .notifier_call = armada_xp_mpic_secondary_init,
364 .priority = 100,
365 };
366
367 #endif /* CONFIG_SMP */
368
369 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
370 .map = armada_370_xp_mpic_irq_map,
371 .xlate = irq_domain_xlate_onecell,
372 };
373
374 #ifdef CONFIG_PCI_MSI
375 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
376 {
377 u32 msimask, msinr;
378
379 msimask = readl_relaxed(per_cpu_int_base +
380 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
381 & PCI_MSI_DOORBELL_MASK;
382
383 writel(~msimask, per_cpu_int_base +
384 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
385
386 for (msinr = PCI_MSI_DOORBELL_START;
387 msinr < PCI_MSI_DOORBELL_END; msinr++) {
388 int irq;
389
390 if (!(msimask & BIT(msinr)))
391 continue;
392
393 if (is_chained) {
394 irq = irq_find_mapping(armada_370_xp_msi_domain,
395 msinr - 16);
396 generic_handle_irq(irq);
397 } else {
398 irq = msinr - 16;
399 handle_domain_irq(armada_370_xp_msi_domain,
400 irq, regs);
401 }
402 }
403 }
404 #else
405 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
406 #endif
407
408 static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
409 struct irq_desc *desc)
410 {
411 struct irq_chip *chip = irq_get_chip(irq);
412 unsigned long irqmap, irqn, irqsrc, cpuid;
413 unsigned int cascade_irq;
414
415 chained_irq_enter(chip, desc);
416
417 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
418 cpuid = cpu_logical_map(smp_processor_id());
419
420 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
421 irqsrc = readl_relaxed(main_int_base +
422 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
423
424 /* Check if the interrupt is not masked on current CPU.
425 * Test IRQ (0-1) and FIQ (8-9) mask bits.
426 */
427 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
428 continue;
429
430 if (irqn == 1) {
431 armada_370_xp_handle_msi_irq(NULL, true);
432 continue;
433 }
434
435 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
436 generic_handle_irq(cascade_irq);
437 }
438
439 chained_irq_exit(chip, desc);
440 }
441
442 static void __exception_irq_entry
443 armada_370_xp_handle_irq(struct pt_regs *regs)
444 {
445 u32 irqstat, irqnr;
446
447 do {
448 irqstat = readl_relaxed(per_cpu_int_base +
449 ARMADA_370_XP_CPU_INTACK_OFFS);
450 irqnr = irqstat & 0x3FF;
451
452 if (irqnr > 1022)
453 break;
454
455 if (irqnr > 1) {
456 handle_domain_irq(armada_370_xp_mpic_domain,
457 irqnr, regs);
458 continue;
459 }
460
461 /* MSI handling */
462 if (irqnr == 1)
463 armada_370_xp_handle_msi_irq(regs, false);
464
465 #ifdef CONFIG_SMP
466 /* IPI Handling */
467 if (irqnr == 0) {
468 u32 ipimask, ipinr;
469
470 ipimask = readl_relaxed(per_cpu_int_base +
471 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
472 & IPI_DOORBELL_MASK;
473
474 writel(~ipimask, per_cpu_int_base +
475 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
476
477 /* Handle all pending doorbells */
478 for (ipinr = IPI_DOORBELL_START;
479 ipinr < IPI_DOORBELL_END; ipinr++) {
480 if (ipimask & (0x1 << ipinr))
481 handle_IPI(ipinr, regs);
482 }
483 continue;
484 }
485 #endif
486
487 } while (1);
488 }
489
490 static int armada_370_xp_mpic_suspend(void)
491 {
492 doorbell_mask_reg = readl(per_cpu_int_base +
493 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
494 return 0;
495 }
496
497 static void armada_370_xp_mpic_resume(void)
498 {
499 int nirqs;
500 irq_hw_number_t irq;
501
502 /* Re-enable interrupts */
503 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
504 for (irq = 0; irq < nirqs; irq++) {
505 struct irq_data *data;
506 int virq;
507
508 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
509 if (virq == 0)
510 continue;
511
512 if (irq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
513 writel(irq, per_cpu_int_base +
514 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
515 else
516 writel(irq, main_int_base +
517 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
518
519 data = irq_get_irq_data(virq);
520 if (!irqd_irq_disabled(data))
521 armada_370_xp_irq_unmask(data);
522 }
523
524 /* Reconfigure doorbells for IPIs and MSIs */
525 writel(doorbell_mask_reg,
526 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
527 if (doorbell_mask_reg & IPI_DOORBELL_MASK)
528 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
529 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
530 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
531 }
532
533 struct syscore_ops armada_370_xp_mpic_syscore_ops = {
534 .suspend = armada_370_xp_mpic_suspend,
535 .resume = armada_370_xp_mpic_resume,
536 };
537
538 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
539 struct device_node *parent)
540 {
541 struct resource main_int_res, per_cpu_int_res;
542 int parent_irq, nr_irqs, i;
543 u32 control;
544
545 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
546 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
547
548 BUG_ON(!request_mem_region(main_int_res.start,
549 resource_size(&main_int_res),
550 node->full_name));
551 BUG_ON(!request_mem_region(per_cpu_int_res.start,
552 resource_size(&per_cpu_int_res),
553 node->full_name));
554
555 main_int_base = ioremap(main_int_res.start,
556 resource_size(&main_int_res));
557 BUG_ON(!main_int_base);
558
559 per_cpu_int_base = ioremap(per_cpu_int_res.start,
560 resource_size(&per_cpu_int_res));
561 BUG_ON(!per_cpu_int_base);
562
563 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
564 nr_irqs = (control >> 2) & 0x3ff;
565
566 for (i = 0; i < nr_irqs; i++)
567 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
568
569 armada_370_xp_mpic_domain =
570 irq_domain_add_linear(node, nr_irqs,
571 &armada_370_xp_mpic_irq_ops, NULL);
572
573 BUG_ON(!armada_370_xp_mpic_domain);
574
575 #ifdef CONFIG_SMP
576 armada_xp_mpic_smp_cpu_init();
577 #endif
578
579 armada_370_xp_msi_init(node, main_int_res.start);
580
581 parent_irq = irq_of_parse_and_map(node, 0);
582 if (parent_irq <= 0) {
583 irq_set_default_host(armada_370_xp_mpic_domain);
584 set_handle_irq(armada_370_xp_handle_irq);
585 #ifdef CONFIG_SMP
586 set_smp_cross_call(armada_mpic_send_doorbell);
587 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
588 #endif
589 } else {
590 irq_set_chained_handler(parent_irq,
591 armada_370_xp_mpic_handle_cascade_irq);
592 }
593
594 register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
595
596 return 0;
597 }
598
599 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
Linux with added FPC-III support