?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / net / can / flexcan.c
blobb1d583ba967482f4039af3c372cf9df46d229248
1 /*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/regulator/consumer.h>
40
41 #define DRV_NAME "flexcan"
42
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
45
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
66 #define FLEXCAN_MCR_IDAM_A (0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (3 << 8)
70
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94
95 /* FLEXCAN control register 2 (CTRL2) bits */
96 #define FLEXCAN_CRL2_ECRWRE BIT(29)
97 #define FLEXCAN_CRL2_WRMFRZ BIT(28)
98 #define FLEXCAN_CRL2_RFFN(x) (((x) & 0x0f) << 24)
99 #define FLEXCAN_CRL2_TASD(x) (((x) & 0x1f) << 19)
100 #define FLEXCAN_CRL2_MRP BIT(18)
101 #define FLEXCAN_CRL2_RRS BIT(17)
102 #define FLEXCAN_CRL2_EACEN BIT(16)
103
104 /* FLEXCAN memory error control register (MECR) bits */
105 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
106 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
107 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
108 #define FLEXCAN_MECR_CEI_MSK BIT(16)
109 #define FLEXCAN_MECR_HAERRIE BIT(15)
110 #define FLEXCAN_MECR_FAERRIE BIT(14)
111 #define FLEXCAN_MECR_EXTERRIE BIT(13)
112 #define FLEXCAN_MECR_RERRDIS BIT(9)
113 #define FLEXCAN_MECR_ECCDIS BIT(8)
114 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
115
116 /* FLEXCAN error and status register (ESR) bits */
117 #define FLEXCAN_ESR_TWRN_INT BIT(17)
118 #define FLEXCAN_ESR_RWRN_INT BIT(16)
119 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
120 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
121 #define FLEXCAN_ESR_ACK_ERR BIT(13)
122 #define FLEXCAN_ESR_CRC_ERR BIT(12)
123 #define FLEXCAN_ESR_FRM_ERR BIT(11)
124 #define FLEXCAN_ESR_STF_ERR BIT(10)
125 #define FLEXCAN_ESR_TX_WRN BIT(9)
126 #define FLEXCAN_ESR_RX_WRN BIT(8)
127 #define FLEXCAN_ESR_IDLE BIT(7)
128 #define FLEXCAN_ESR_TXRX BIT(6)
129 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
130 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
133 #define FLEXCAN_ESR_BOFF_INT BIT(2)
134 #define FLEXCAN_ESR_ERR_INT BIT(1)
135 #define FLEXCAN_ESR_WAK_INT BIT(0)
136 #define FLEXCAN_ESR_ERR_BUS \
137 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
138 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
139 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
140 #define FLEXCAN_ESR_ERR_STATE \
141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
142 #define FLEXCAN_ESR_ERR_ALL \
143 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
144 #define FLEXCAN_ESR_ALL_INT \
145 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
146 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
147
148 /* FLEXCAN interrupt flag register (IFLAG) bits */
149 /* Errata ERR005829 step7: Reserve first valid MB */
150 #define FLEXCAN_TX_BUF_RESERVED 8
151 #define FLEXCAN_TX_BUF_ID 9
152 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
153 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
154 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
155 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
156 #define FLEXCAN_IFLAG_DEFAULT \
157 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
158 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
159
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
162 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
163 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
164 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
165 #define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24)
166 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
167
168 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
169 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
170 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
171 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
172
173 #define FLEXCAN_MB_CNT_SRR BIT(22)
174 #define FLEXCAN_MB_CNT_IDE BIT(21)
175 #define FLEXCAN_MB_CNT_RTR BIT(20)
176 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
177 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
178
179 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
180
181 #define FLEXCAN_TIMEOUT_US (50)
182
183 /*
184 * FLEXCAN hardware feature flags
185 *
186 * Below is some version info we got:
187 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err
188 * Filter? connected? detection
189 * MX25 FlexCAN2 03.00.00.00 no no no
190 * MX28 FlexCAN2 03.00.04.00 yes yes no
191 * MX35 FlexCAN2 03.00.00.00 no no no
192 * MX53 FlexCAN2 03.00.00.00 yes no no
193 * MX6s FlexCAN3 10.00.12.00 yes yes no
194 * VF610 FlexCAN3 ? no yes yes
195 *
196 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
197 */
198 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
199 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
200 #define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */
201
202 /* Structure of the message buffer */
203 struct flexcan_mb {
204 u32 can_ctrl;
205 u32 can_id;
206 u32 data[2];
207 };
208
209 /* Structure of the hardware registers */
210 struct flexcan_regs {
211 u32 mcr; /* 0x00 */
212 u32 ctrl; /* 0x04 */
213 u32 timer; /* 0x08 */
214 u32 _reserved1; /* 0x0c */
215 u32 rxgmask; /* 0x10 */
216 u32 rx14mask; /* 0x14 */
217 u32 rx15mask; /* 0x18 */
218 u32 ecr; /* 0x1c */
219 u32 esr; /* 0x20 */
220 u32 imask2; /* 0x24 */
221 u32 imask1; /* 0x28 */
222 u32 iflag2; /* 0x2c */
223 u32 iflag1; /* 0x30 */
224 u32 crl2; /* 0x34 */
225 u32 esr2; /* 0x38 */
226 u32 imeur; /* 0x3c */
227 u32 lrfr; /* 0x40 */
228 u32 crcr; /* 0x44 */
229 u32 rxfgmask; /* 0x48 */
230 u32 rxfir; /* 0x4c */
231 u32 _reserved3[12]; /* 0x50 */
232 struct flexcan_mb cantxfg[64]; /* 0x80 */
233 u32 _reserved4[408];
234 u32 mecr; /* 0xae0 */
235 u32 erriar; /* 0xae4 */
236 u32 erridpr; /* 0xae8 */
237 u32 errippr; /* 0xaec */
238 u32 rerrar; /* 0xaf0 */
239 u32 rerrdr; /* 0xaf4 */
240 u32 rerrsynr; /* 0xaf8 */
241 u32 errsr; /* 0xafc */
242 };
243
244 struct flexcan_devtype_data {
245 u32 features; /* hardware controller features */
246 };
247
248 struct flexcan_priv {
249 struct can_priv can;
250 struct net_device *dev;
251 struct napi_struct napi;
252
253 void __iomem *base;
254 u32 reg_esr;
255 u32 reg_ctrl_default;
256
257 struct clk *clk_ipg;
258 struct clk *clk_per;
259 struct flexcan_platform_data *pdata;
260 const struct flexcan_devtype_data *devtype_data;
261 struct regulator *reg_xceiver;
262 };
263
264 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
265 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
266 };
267 static struct flexcan_devtype_data fsl_imx28_devtype_data;
268 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
269 .features = FLEXCAN_HAS_V10_FEATURES,
270 };
271 static struct flexcan_devtype_data fsl_vf610_devtype_data = {
272 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
273 };
274
275 static const struct can_bittiming_const flexcan_bittiming_const = {
276 .name = DRV_NAME,
277 .tseg1_min = 4,
278 .tseg1_max = 16,
279 .tseg2_min = 2,
280 .tseg2_max = 8,
281 .sjw_max = 4,
282 .brp_min = 1,
283 .brp_max = 256,
284 .brp_inc = 1,
285 };
286
287 /*
288 * Abstract off the read/write for arm versus ppc. This
289 * assumes that PPC uses big-endian registers and everything
290 * else uses little-endian registers, independent of CPU
291 * endianess.
292 */
293 #if defined(CONFIG_PPC)
294 static inline u32 flexcan_read(void __iomem *addr)
295 {
296 return in_be32(addr);
297 }
298
299 static inline void flexcan_write(u32 val, void __iomem *addr)
300 {
301 out_be32(addr, val);
302 }
303 #else
304 static inline u32 flexcan_read(void __iomem *addr)
305 {
306 return readl(addr);
307 }
308
309 static inline void flexcan_write(u32 val, void __iomem *addr)
310 {
311 writel(val, addr);
312 }
313 #endif
314
315 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
316 {
317 if (!priv->reg_xceiver)
318 return 0;
319
320 return regulator_enable(priv->reg_xceiver);
321 }
322
323 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
324 {
325 if (!priv->reg_xceiver)
326 return 0;
327
328 return regulator_disable(priv->reg_xceiver);
329 }
330
331 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
332 u32 reg_esr)
333 {
334 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
335 (reg_esr & FLEXCAN_ESR_ERR_BUS);
336 }
337
338 static int flexcan_chip_enable(struct flexcan_priv *priv)
339 {
340 struct flexcan_regs __iomem *regs = priv->base;
341 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
342 u32 reg;
343
344 reg = flexcan_read(&regs->mcr);
345 reg &= ~FLEXCAN_MCR_MDIS;
346 flexcan_write(reg, &regs->mcr);
347
348 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
349 udelay(10);
350
351 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
352 return -ETIMEDOUT;
353
354 return 0;
355 }
356
357 static int flexcan_chip_disable(struct flexcan_priv *priv)
358 {
359 struct flexcan_regs __iomem *regs = priv->base;
360 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
361 u32 reg;
362
363 reg = flexcan_read(&regs->mcr);
364 reg |= FLEXCAN_MCR_MDIS;
365 flexcan_write(reg, &regs->mcr);
366
367 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
368 udelay(10);
369
370 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
371 return -ETIMEDOUT;
372
373 return 0;
374 }
375
376 static int flexcan_chip_freeze(struct flexcan_priv *priv)
377 {
378 struct flexcan_regs __iomem *regs = priv->base;
379 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
380 u32 reg;
381
382 reg = flexcan_read(&regs->mcr);
383 reg |= FLEXCAN_MCR_HALT;
384 flexcan_write(reg, &regs->mcr);
385
386 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
387 udelay(100);
388
389 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
390 return -ETIMEDOUT;
391
392 return 0;
393 }
394
395 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
396 {
397 struct flexcan_regs __iomem *regs = priv->base;
398 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
399 u32 reg;
400
401 reg = flexcan_read(&regs->mcr);
402 reg &= ~FLEXCAN_MCR_HALT;
403 flexcan_write(reg, &regs->mcr);
404
405 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
406 udelay(10);
407
408 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
409 return -ETIMEDOUT;
410
411 return 0;
412 }
413
414 static int flexcan_chip_softreset(struct flexcan_priv *priv)
415 {
416 struct flexcan_regs __iomem *regs = priv->base;
417 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
418
419 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
420 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
421 udelay(10);
422
423 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
424 return -ETIMEDOUT;
425
426 return 0;
427 }
428
429
430 static int __flexcan_get_berr_counter(const struct net_device *dev,
431 struct can_berr_counter *bec)
432 {
433 const struct flexcan_priv *priv = netdev_priv(dev);
434 struct flexcan_regs __iomem *regs = priv->base;
435 u32 reg = flexcan_read(&regs->ecr);
436
437 bec->txerr = (reg >> 0) & 0xff;
438 bec->rxerr = (reg >> 8) & 0xff;
439
440 return 0;
441 }
442
443 static int flexcan_get_berr_counter(const struct net_device *dev,
444 struct can_berr_counter *bec)
445 {
446 const struct flexcan_priv *priv = netdev_priv(dev);
447 int err;
448
449 err = clk_prepare_enable(priv->clk_ipg);
450 if (err)
451 return err;
452
453 err = clk_prepare_enable(priv->clk_per);
454 if (err)
455 goto out_disable_ipg;
456
457 err = __flexcan_get_berr_counter(dev, bec);
458
459 clk_disable_unprepare(priv->clk_per);
460 out_disable_ipg:
461 clk_disable_unprepare(priv->clk_ipg);
462
463 return err;
464 }
465
466 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
467 {
468 const struct flexcan_priv *priv = netdev_priv(dev);
469 struct flexcan_regs __iomem *regs = priv->base;
470 struct can_frame *cf = (struct can_frame *)skb->data;
471 u32 can_id;
472 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
473
474 if (can_dropped_invalid_skb(dev, skb))
475 return NETDEV_TX_OK;
476
477 netif_stop_queue(dev);
478
479 if (cf->can_id & CAN_EFF_FLAG) {
480 can_id = cf->can_id & CAN_EFF_MASK;
481 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
482 } else {
483 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
484 }
485
486 if (cf->can_id & CAN_RTR_FLAG)
487 ctrl |= FLEXCAN_MB_CNT_RTR;
488
489 if (cf->can_dlc > 0) {
490 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
491 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
492 }
493 if (cf->can_dlc > 3) {
494 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
495 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
496 }
497
498 can_put_echo_skb(skb, dev, 0);
499
500 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
501 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
502
503 /* Errata ERR005829 step8:
504 * Write twice INACTIVE(0x8) code to first MB.
505 */
506 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
507 &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
508 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
509 &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
510
511 return NETDEV_TX_OK;
512 }
513
514 static void do_bus_err(struct net_device *dev,
515 struct can_frame *cf, u32 reg_esr)
516 {
517 struct flexcan_priv *priv = netdev_priv(dev);
518 int rx_errors = 0, tx_errors = 0;
519
520 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
521
522 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
523 netdev_dbg(dev, "BIT1_ERR irq\n");
524 cf->data[2] |= CAN_ERR_PROT_BIT1;
525 tx_errors = 1;
526 }
527 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
528 netdev_dbg(dev, "BIT0_ERR irq\n");
529 cf->data[2] |= CAN_ERR_PROT_BIT0;
530 tx_errors = 1;
531 }
532 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
533 netdev_dbg(dev, "ACK_ERR irq\n");
534 cf->can_id |= CAN_ERR_ACK;
535 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
536 tx_errors = 1;
537 }
538 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
539 netdev_dbg(dev, "CRC_ERR irq\n");
540 cf->data[2] |= CAN_ERR_PROT_BIT;
541 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
542 rx_errors = 1;
543 }
544 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
545 netdev_dbg(dev, "FRM_ERR irq\n");
546 cf->data[2] |= CAN_ERR_PROT_FORM;
547 rx_errors = 1;
548 }
549 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
550 netdev_dbg(dev, "STF_ERR irq\n");
551 cf->data[2] |= CAN_ERR_PROT_STUFF;
552 rx_errors = 1;
553 }
554
555 priv->can.can_stats.bus_error++;
556 if (rx_errors)
557 dev->stats.rx_errors++;
558 if (tx_errors)
559 dev->stats.tx_errors++;
560 }
561
562 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
563 {
564 struct sk_buff *skb;
565 struct can_frame *cf;
566
567 skb = alloc_can_err_skb(dev, &cf);
568 if (unlikely(!skb))
569 return 0;
570
571 do_bus_err(dev, cf, reg_esr);
572 netif_receive_skb(skb);
573
574 dev->stats.rx_packets++;
575 dev->stats.rx_bytes += cf->can_dlc;
576
577 return 1;
578 }
579
580 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
581 {
582 struct flexcan_priv *priv = netdev_priv(dev);
583 struct sk_buff *skb;
584 struct can_frame *cf;
585 enum can_state new_state = 0, rx_state = 0, tx_state = 0;
586 int flt;
587 struct can_berr_counter bec;
588
589 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
590 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
591 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
592 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
593 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
594 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
595 new_state = max(tx_state, rx_state);
596 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) {
597 __flexcan_get_berr_counter(dev, &bec);
598 new_state = CAN_STATE_ERROR_PASSIVE;
599 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
600 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
601 } else {
602 new_state = CAN_STATE_BUS_OFF;
603 }
604
605 /* state hasn't changed */
606 if (likely(new_state == priv->can.state))
607 return 0;
608
609 skb = alloc_can_err_skb(dev, &cf);
610 if (unlikely(!skb))
611 return 0;
612
613 can_change_state(dev, cf, tx_state, rx_state);
614
615 if (unlikely(new_state == CAN_STATE_BUS_OFF))
616 can_bus_off(dev);
617
618 netif_receive_skb(skb);
619
620 dev->stats.rx_packets++;
621 dev->stats.rx_bytes += cf->can_dlc;
622
623 return 1;
624 }
625
626 static void flexcan_read_fifo(const struct net_device *dev,
627 struct can_frame *cf)
628 {
629 const struct flexcan_priv *priv = netdev_priv(dev);
630 struct flexcan_regs __iomem *regs = priv->base;
631 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
632 u32 reg_ctrl, reg_id;
633
634 reg_ctrl = flexcan_read(&mb->can_ctrl);
635 reg_id = flexcan_read(&mb->can_id);
636 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
637 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
638 else
639 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
640
641 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
642 cf->can_id |= CAN_RTR_FLAG;
643 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
644
645 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
646 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
647
648 /* mark as read */
649 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
650 flexcan_read(&regs->timer);
651 }
652
653 static int flexcan_read_frame(struct net_device *dev)
654 {
655 struct net_device_stats *stats = &dev->stats;
656 struct can_frame *cf;
657 struct sk_buff *skb;
658
659 skb = alloc_can_skb(dev, &cf);
660 if (unlikely(!skb)) {
661 stats->rx_dropped++;
662 return 0;
663 }
664
665 flexcan_read_fifo(dev, cf);
666 netif_receive_skb(skb);
667
668 stats->rx_packets++;
669 stats->rx_bytes += cf->can_dlc;
670
671 can_led_event(dev, CAN_LED_EVENT_RX);
672
673 return 1;
674 }
675
676 static int flexcan_poll(struct napi_struct *napi, int quota)
677 {
678 struct net_device *dev = napi->dev;
679 const struct flexcan_priv *priv = netdev_priv(dev);
680 struct flexcan_regs __iomem *regs = priv->base;
681 u32 reg_iflag1, reg_esr;
682 int work_done = 0;
683
684 /*
685 * The error bits are cleared on read,
686 * use saved value from irq handler.
687 */
688 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
689
690 /* handle state changes */
691 work_done += flexcan_poll_state(dev, reg_esr);
692
693 /* handle RX-FIFO */
694 reg_iflag1 = flexcan_read(&regs->iflag1);
695 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
696 work_done < quota) {
697 work_done += flexcan_read_frame(dev);
698 reg_iflag1 = flexcan_read(&regs->iflag1);
699 }
700
701 /* report bus errors */
702 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
703 work_done += flexcan_poll_bus_err(dev, reg_esr);
704
705 if (work_done < quota) {
706 napi_complete(napi);
707 /* enable IRQs */
708 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
709 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
710 }
711
712 return work_done;
713 }
714
715 static irqreturn_t flexcan_irq(int irq, void *dev_id)
716 {
717 struct net_device *dev = dev_id;
718 struct net_device_stats *stats = &dev->stats;
719 struct flexcan_priv *priv = netdev_priv(dev);
720 struct flexcan_regs __iomem *regs = priv->base;
721 u32 reg_iflag1, reg_esr;
722
723 reg_iflag1 = flexcan_read(&regs->iflag1);
724 reg_esr = flexcan_read(&regs->esr);
725 /* ACK all bus error and state change IRQ sources */
726 if (reg_esr & FLEXCAN_ESR_ALL_INT)
727 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
728
729 /*
730 * schedule NAPI in case of:
731 * - rx IRQ
732 * - state change IRQ
733 * - bus error IRQ and bus error reporting is activated
734 */
735 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
736 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
737 flexcan_has_and_handle_berr(priv, reg_esr)) {
738 /*
739 * The error bits are cleared on read,
740 * save them for later use.
741 */
742 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
743 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
744 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
745 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
746 &regs->ctrl);
747 napi_schedule(&priv->napi);
748 }
749
750 /* FIFO overflow */
751 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
752 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
753 dev->stats.rx_over_errors++;
754 dev->stats.rx_errors++;
755 }
756
757 /* transmission complete interrupt */
758 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
759 stats->tx_bytes += can_get_echo_skb(dev, 0);
760 stats->tx_packets++;
761 can_led_event(dev, CAN_LED_EVENT_TX);
762 /* after sending a RTR frame mailbox is in RX mode */
763 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
764 &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
765 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
766 netif_wake_queue(dev);
767 }
768
769 return IRQ_HANDLED;
770 }
771
772 static void flexcan_set_bittiming(struct net_device *dev)
773 {
774 const struct flexcan_priv *priv = netdev_priv(dev);
775 const struct can_bittiming *bt = &priv->can.bittiming;
776 struct flexcan_regs __iomem *regs = priv->base;
777 u32 reg;
778
779 reg = flexcan_read(&regs->ctrl);
780 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
781 FLEXCAN_CTRL_RJW(0x3) |
782 FLEXCAN_CTRL_PSEG1(0x7) |
783 FLEXCAN_CTRL_PSEG2(0x7) |
784 FLEXCAN_CTRL_PROPSEG(0x7) |
785 FLEXCAN_CTRL_LPB |
786 FLEXCAN_CTRL_SMP |
787 FLEXCAN_CTRL_LOM);
788
789 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
790 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
791 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
792 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
793 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
794
795 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
796 reg |= FLEXCAN_CTRL_LPB;
797 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
798 reg |= FLEXCAN_CTRL_LOM;
799 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
800 reg |= FLEXCAN_CTRL_SMP;
801
802 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
803 flexcan_write(reg, &regs->ctrl);
804
805 /* print chip status */
806 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
807 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
808 }
809
810 /*
811 * flexcan_chip_start
812 *
813 * this functions is entered with clocks enabled
814 *
815 */
816 static int flexcan_chip_start(struct net_device *dev)
817 {
818 struct flexcan_priv *priv = netdev_priv(dev);
819 struct flexcan_regs __iomem *regs = priv->base;
820 u32 reg_mcr, reg_ctrl, reg_crl2, reg_mecr;
821 int err, i;
822
823 /* enable module */
824 err = flexcan_chip_enable(priv);
825 if (err)
826 return err;
827
828 /* soft reset */
829 err = flexcan_chip_softreset(priv);
830 if (err)
831 goto out_chip_disable;
832
833 flexcan_set_bittiming(dev);
834
835 /*
836 * MCR
837 *
838 * enable freeze
839 * enable fifo
840 * halt now
841 * only supervisor access
842 * enable warning int
843 * choose format C
844 * disable local echo
845 *
846 */
847 reg_mcr = flexcan_read(&regs->mcr);
848 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
849 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
850 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
851 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
852 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
853 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
854 flexcan_write(reg_mcr, &regs->mcr);
855
856 /*
857 * CTRL
858 *
859 * disable timer sync feature
860 *
861 * disable auto busoff recovery
862 * transmit lowest buffer first
863 *
864 * enable tx and rx warning interrupt
865 * enable bus off interrupt
866 * (== FLEXCAN_CTRL_ERR_STATE)
867 */
868 reg_ctrl = flexcan_read(&regs->ctrl);
869 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
870 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
871 FLEXCAN_CTRL_ERR_STATE;
872 /*
873 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
874 * on most Flexcan cores, too. Otherwise we don't get
875 * any error warning or passive interrupts.
876 */
877 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
878 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
879 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
880 else
881 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
882
883 /* save for later use */
884 priv->reg_ctrl_default = reg_ctrl;
885 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
886 flexcan_write(reg_ctrl, &regs->ctrl);
887
888 /* clear and invalidate all mailboxes first */
889 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
890 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
891 &regs->cantxfg[i].can_ctrl);
892 }
893
894 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
895 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
896 &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
897
898 /* mark TX mailbox as INACTIVE */
899 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
900 &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
901
902 /* acceptance mask/acceptance code (accept everything) */
903 flexcan_write(0x0, &regs->rxgmask);
904 flexcan_write(0x0, &regs->rx14mask);
905 flexcan_write(0x0, &regs->rx15mask);
906
907 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
908 flexcan_write(0x0, &regs->rxfgmask);
909
910 /*
911 * On Vybrid, disable memory error detection interrupts
912 * and freeze mode.
913 * This also works around errata e5295 which generates
914 * false positive memory errors and put the device in
915 * freeze mode.
916 */
917 if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) {
918 /*
919 * Follow the protocol as described in "Detection
920 * and Correction of Memory Errors" to write to
921 * MECR register
922 */
923 reg_crl2 = flexcan_read(&regs->crl2);
924 reg_crl2 |= FLEXCAN_CRL2_ECRWRE;
925 flexcan_write(reg_crl2, &regs->crl2);
926
927 reg_mecr = flexcan_read(&regs->mecr);
928 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
929 flexcan_write(reg_mecr, &regs->mecr);
930 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
931 FLEXCAN_MECR_FANCEI_MSK);
932 flexcan_write(reg_mecr, &regs->mecr);
933 }
934
935 err = flexcan_transceiver_enable(priv);
936 if (err)
937 goto out_chip_disable;
938
939 /* synchronize with the can bus */
940 err = flexcan_chip_unfreeze(priv);
941 if (err)
942 goto out_transceiver_disable;
943
944 priv->can.state = CAN_STATE_ERROR_ACTIVE;
945
946 /* enable FIFO interrupts */
947 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
948
949 /* print chip status */
950 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
951 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
952
953 return 0;
954
955 out_transceiver_disable:
956 flexcan_transceiver_disable(priv);
957 out_chip_disable:
958 flexcan_chip_disable(priv);
959 return err;
960 }
961
962 /*
963 * flexcan_chip_stop
964 *
965 * this functions is entered with clocks enabled
966 *
967 */
968 static void flexcan_chip_stop(struct net_device *dev)
969 {
970 struct flexcan_priv *priv = netdev_priv(dev);
971 struct flexcan_regs __iomem *regs = priv->base;
972
973 /* freeze + disable module */
974 flexcan_chip_freeze(priv);
975 flexcan_chip_disable(priv);
976
977 /* Disable all interrupts */
978 flexcan_write(0, &regs->imask1);
979 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
980 &regs->ctrl);
981
982 flexcan_transceiver_disable(priv);
983 priv->can.state = CAN_STATE_STOPPED;
984
985 return;
986 }
987
988 static int flexcan_open(struct net_device *dev)
989 {
990 struct flexcan_priv *priv = netdev_priv(dev);
991 int err;
992
993 err = clk_prepare_enable(priv->clk_ipg);
994 if (err)
995 return err;
996
997 err = clk_prepare_enable(priv->clk_per);
998 if (err)
999 goto out_disable_ipg;
1000
1001 err = open_candev(dev);
1002 if (err)
1003 goto out_disable_per;
1004
1005 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1006 if (err)
1007 goto out_close;
1008
1009 /* start chip and queuing */
1010 err = flexcan_chip_start(dev);
1011 if (err)
1012 goto out_free_irq;
1013
1014 can_led_event(dev, CAN_LED_EVENT_OPEN);
1015
1016 napi_enable(&priv->napi);
1017 netif_start_queue(dev);
1018
1019 return 0;
1020
1021 out_free_irq:
1022 free_irq(dev->irq, dev);
1023 out_close:
1024 close_candev(dev);
1025 out_disable_per:
1026 clk_disable_unprepare(priv->clk_per);
1027 out_disable_ipg:
1028 clk_disable_unprepare(priv->clk_ipg);
1029
1030 return err;
1031 }
1032
1033 static int flexcan_close(struct net_device *dev)
1034 {
1035 struct flexcan_priv *priv = netdev_priv(dev);
1036
1037 netif_stop_queue(dev);
1038 napi_disable(&priv->napi);
1039 flexcan_chip_stop(dev);
1040
1041 free_irq(dev->irq, dev);
1042 clk_disable_unprepare(priv->clk_per);
1043 clk_disable_unprepare(priv->clk_ipg);
1044
1045 close_candev(dev);
1046
1047 can_led_event(dev, CAN_LED_EVENT_STOP);
1048
1049 return 0;
1050 }
1051
1052 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1053 {
1054 int err;
1055
1056 switch (mode) {
1057 case CAN_MODE_START:
1058 err = flexcan_chip_start(dev);
1059 if (err)
1060 return err;
1061
1062 netif_wake_queue(dev);
1063 break;
1064
1065 default:
1066 return -EOPNOTSUPP;
1067 }
1068
1069 return 0;
1070 }
1071
1072 static const struct net_device_ops flexcan_netdev_ops = {
1073 .ndo_open = flexcan_open,
1074 .ndo_stop = flexcan_close,
1075 .ndo_start_xmit = flexcan_start_xmit,
1076 .ndo_change_mtu = can_change_mtu,
1077 };
1078
1079 static int register_flexcandev(struct net_device *dev)
1080 {
1081 struct flexcan_priv *priv = netdev_priv(dev);
1082 struct flexcan_regs __iomem *regs = priv->base;
1083 u32 reg, err;
1084
1085 err = clk_prepare_enable(priv->clk_ipg);
1086 if (err)
1087 return err;
1088
1089 err = clk_prepare_enable(priv->clk_per);
1090 if (err)
1091 goto out_disable_ipg;
1092
1093 /* select "bus clock", chip must be disabled */
1094 err = flexcan_chip_disable(priv);
1095 if (err)
1096 goto out_disable_per;
1097 reg = flexcan_read(&regs->ctrl);
1098 reg |= FLEXCAN_CTRL_CLK_SRC;
1099 flexcan_write(reg, &regs->ctrl);
1100
1101 err = flexcan_chip_enable(priv);
1102 if (err)
1103 goto out_chip_disable;
1104
1105 /* set freeze, halt and activate FIFO, restrict register access */
1106 reg = flexcan_read(&regs->mcr);
1107 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1108 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1109 flexcan_write(reg, &regs->mcr);
1110
1111 /*
1112 * Currently we only support newer versions of this core
1113 * featuring a RX FIFO. Older cores found on some Coldfire
1114 * derivates are not yet supported.
1115 */
1116 reg = flexcan_read(&regs->mcr);
1117 if (!(reg & FLEXCAN_MCR_FEN)) {
1118 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1119 err = -ENODEV;
1120 goto out_chip_disable;
1121 }
1122
1123 err = register_candev(dev);
1124
1125 /* disable core and turn off clocks */
1126 out_chip_disable:
1127 flexcan_chip_disable(priv);
1128 out_disable_per:
1129 clk_disable_unprepare(priv->clk_per);
1130 out_disable_ipg:
1131 clk_disable_unprepare(priv->clk_ipg);
1132
1133 return err;
1134 }
1135
1136 static void unregister_flexcandev(struct net_device *dev)
1137 {
1138 unregister_candev(dev);
1139 }
1140
1141 static const struct of_device_id flexcan_of_match[] = {
1142 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1143 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1144 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1145 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1146 { /* sentinel */ },
1147 };
1148 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1149
1150 static const struct platform_device_id flexcan_id_table[] = {
1151 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1152 { /* sentinel */ },
1153 };
1154 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1155
1156 static int flexcan_probe(struct platform_device *pdev)
1157 {
1158 const struct of_device_id *of_id;
1159 const struct flexcan_devtype_data *devtype_data;
1160 struct net_device *dev;
1161 struct flexcan_priv *priv;
1162 struct resource *mem;
1163 struct clk *clk_ipg = NULL, *clk_per = NULL;
1164 void __iomem *base;
1165 int err, irq;
1166 u32 clock_freq = 0;
1167
1168 if (pdev->dev.of_node)
1169 of_property_read_u32(pdev->dev.of_node,
1170 "clock-frequency", &clock_freq);
1171
1172 if (!clock_freq) {
1173 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1174 if (IS_ERR(clk_ipg)) {
1175 dev_err(&pdev->dev, "no ipg clock defined\n");
1176 return PTR_ERR(clk_ipg);
1177 }
1178
1179 clk_per = devm_clk_get(&pdev->dev, "per");
1180 if (IS_ERR(clk_per)) {
1181 dev_err(&pdev->dev, "no per clock defined\n");
1182 return PTR_ERR(clk_per);
1183 }
1184 clock_freq = clk_get_rate(clk_per);
1185 }
1186
1187 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188 irq = platform_get_irq(pdev, 0);
1189 if (irq <= 0)
1190 return -ENODEV;
1191
1192 base = devm_ioremap_resource(&pdev->dev, mem);
1193 if (IS_ERR(base))
1194 return PTR_ERR(base);
1195
1196 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1197 if (of_id) {
1198 devtype_data = of_id->data;
1199 } else if (platform_get_device_id(pdev)->driver_data) {
1200 devtype_data = (struct flexcan_devtype_data *)
1201 platform_get_device_id(pdev)->driver_data;
1202 } else {
1203 return -ENODEV;
1204 }
1205
1206 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1207 if (!dev)
1208 return -ENOMEM;
1209
1210 dev->netdev_ops = &flexcan_netdev_ops;
1211 dev->irq = irq;
1212 dev->flags |= IFF_ECHO;
1213
1214 priv = netdev_priv(dev);
1215 priv->can.clock.freq = clock_freq;
1216 priv->can.bittiming_const = &flexcan_bittiming_const;
1217 priv->can.do_set_mode = flexcan_set_mode;
1218 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1219 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1220 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1221 CAN_CTRLMODE_BERR_REPORTING;
1222 priv->base = base;
1223 priv->dev = dev;
1224 priv->clk_ipg = clk_ipg;
1225 priv->clk_per = clk_per;
1226 priv->pdata = dev_get_platdata(&pdev->dev);
1227 priv->devtype_data = devtype_data;
1228
1229 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1230 if (IS_ERR(priv->reg_xceiver))
1231 priv->reg_xceiver = NULL;
1232
1233 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1234
1235 platform_set_drvdata(pdev, dev);
1236 SET_NETDEV_DEV(dev, &pdev->dev);
1237
1238 err = register_flexcandev(dev);
1239 if (err) {
1240 dev_err(&pdev->dev, "registering netdev failed\n");
1241 goto failed_register;
1242 }
1243
1244 devm_can_led_init(dev);
1245
1246 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1247 priv->base, dev->irq);
1248
1249 return 0;
1250
1251 failed_register:
1252 free_candev(dev);
1253 return err;
1254 }
1255
1256 static int flexcan_remove(struct platform_device *pdev)
1257 {
1258 struct net_device *dev = platform_get_drvdata(pdev);
1259 struct flexcan_priv *priv = netdev_priv(dev);
1260
1261 unregister_flexcandev(dev);
1262 netif_napi_del(&priv->napi);
1263 free_candev(dev);
1264
1265 return 0;
1266 }
1267
1268 static int __maybe_unused flexcan_suspend(struct device *device)
1269 {
1270 struct net_device *dev = dev_get_drvdata(device);
1271 struct flexcan_priv *priv = netdev_priv(dev);
1272 int err;
1273
1274 err = flexcan_chip_disable(priv);
1275 if (err)
1276 return err;
1277
1278 if (netif_running(dev)) {
1279 netif_stop_queue(dev);
1280 netif_device_detach(dev);
1281 }
1282 priv->can.state = CAN_STATE_SLEEPING;
1283
1284 return 0;
1285 }
1286
1287 static int __maybe_unused flexcan_resume(struct device *device)
1288 {
1289 struct net_device *dev = dev_get_drvdata(device);
1290 struct flexcan_priv *priv = netdev_priv(dev);
1291
1292 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1293 if (netif_running(dev)) {
1294 netif_device_attach(dev);
1295 netif_start_queue(dev);
1296 }
1297 return flexcan_chip_enable(priv);
1298 }
1299
1300 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1301
1302 static struct platform_driver flexcan_driver = {
1303 .driver = {
1304 .name = DRV_NAME,
1305 .pm = &flexcan_pm_ops,
1306 .of_match_table = flexcan_of_match,
1307 },
1308 .probe = flexcan_probe,
1309 .remove = flexcan_remove,
1310 .id_table = flexcan_id_table,
1311 };
1312
1313 module_platform_driver(flexcan_driver);
1314
1315 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1316 "Marc Kleine-Budde <kernel@pengutronix.de>");
1317 MODULE_LICENSE("GPL v2");
1318 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux with added FPC-III support