2 * CAN bus driver for the alone generic (as possible as) MSCAN controller.
4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
7 * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/if_arp.h>
28 #include <linux/if_ether.h>
29 #include <linux/list.h>
30 #include <linux/can/dev.h>
31 #include <linux/can/error.h>
36 static const struct can_bittiming_const mscan_bittiming_const
= {
54 static enum can_state state_map
[] = {
55 CAN_STATE_ERROR_ACTIVE
,
56 CAN_STATE_ERROR_WARNING
,
57 CAN_STATE_ERROR_PASSIVE
,
61 static int mscan_set_mode(struct net_device
*dev
, u8 mode
)
63 struct mscan_priv
*priv
= netdev_priv(dev
);
64 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
69 if (mode
!= MSCAN_NORMAL_MODE
) {
70 if (priv
->tx_active
) {
71 /* Abort transfers before going to sleep */#
72 out_8(®s
->cantarq
, priv
->tx_active
);
73 /* Suppress TX done interrupts */
74 out_8(®s
->cantier
, 0);
77 canctl1
= in_8(®s
->canctl1
);
78 if ((mode
& MSCAN_SLPRQ
) && !(canctl1
& MSCAN_SLPAK
)) {
79 setbits8(®s
->canctl0
, MSCAN_SLPRQ
);
80 for (i
= 0; i
< MSCAN_SET_MODE_RETRIES
; i
++) {
81 if (in_8(®s
->canctl1
) & MSCAN_SLPAK
)
86 * The mscan controller will fail to enter sleep mode,
87 * while there are irregular activities on bus, like
88 * somebody keeps retransmitting. This behavior is
89 * undocumented and seems to differ between mscan built
90 * in mpc5200b and mpc5200. We proceed in that case,
91 * since otherwise the slprq will be kept set and the
92 * controller will get stuck. NOTE: INITRQ or CSWAI
93 * will abort all active transmit actions, if still
96 if (i
>= MSCAN_SET_MODE_RETRIES
)
98 "device failed to enter sleep mode. "
99 "We proceed anyhow.\n");
101 priv
->can
.state
= CAN_STATE_SLEEPING
;
104 if ((mode
& MSCAN_INITRQ
) && !(canctl1
& MSCAN_INITAK
)) {
105 setbits8(®s
->canctl0
, MSCAN_INITRQ
);
106 for (i
= 0; i
< MSCAN_SET_MODE_RETRIES
; i
++) {
107 if (in_8(®s
->canctl1
) & MSCAN_INITAK
)
110 if (i
>= MSCAN_SET_MODE_RETRIES
)
114 priv
->can
.state
= CAN_STATE_STOPPED
;
116 if (mode
& MSCAN_CSWAI
)
117 setbits8(®s
->canctl0
, MSCAN_CSWAI
);
120 canctl1
= in_8(®s
->canctl1
);
121 if (canctl1
& (MSCAN_SLPAK
| MSCAN_INITAK
)) {
122 clrbits8(®s
->canctl0
, MSCAN_SLPRQ
| MSCAN_INITRQ
);
123 for (i
= 0; i
< MSCAN_SET_MODE_RETRIES
; i
++) {
124 canctl1
= in_8(®s
->canctl1
);
125 if (!(canctl1
& (MSCAN_INITAK
| MSCAN_SLPAK
)))
128 if (i
>= MSCAN_SET_MODE_RETRIES
)
131 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
137 static int mscan_start(struct net_device
*dev
)
139 struct mscan_priv
*priv
= netdev_priv(dev
);
140 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
144 out_8(®s
->canrier
, 0);
146 INIT_LIST_HEAD(&priv
->tx_head
);
147 priv
->prev_buf_id
= 0;
150 priv
->shadow_canrier
= 0;
153 if (priv
->type
== MSCAN_TYPE_MPC5121
) {
154 /* Clear pending bus-off condition */
155 if (in_8(®s
->canmisc
) & MSCAN_BOHOLD
)
156 out_8(®s
->canmisc
, MSCAN_BOHOLD
);
159 err
= mscan_set_mode(dev
, MSCAN_NORMAL_MODE
);
163 canrflg
= in_8(®s
->canrflg
);
164 priv
->shadow_statflg
= canrflg
& MSCAN_STAT_MSK
;
165 priv
->can
.state
= state_map
[max(MSCAN_STATE_RX(canrflg
),
166 MSCAN_STATE_TX(canrflg
))];
167 out_8(®s
->cantier
, 0);
169 /* Enable receive interrupts. */
170 out_8(®s
->canrier
, MSCAN_RX_INTS_ENABLE
);
175 static int mscan_restart(struct net_device
*dev
)
177 struct mscan_priv
*priv
= netdev_priv(dev
);
179 if (priv
->type
== MSCAN_TYPE_MPC5121
) {
180 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
182 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
183 WARN(!(in_8(®s
->canmisc
) & MSCAN_BOHOLD
),
184 "bus-off state expected\n");
185 out_8(®s
->canmisc
, MSCAN_BOHOLD
);
186 /* Re-enable receive interrupts. */
187 out_8(®s
->canrier
, MSCAN_RX_INTS_ENABLE
);
189 if (priv
->can
.state
<= CAN_STATE_BUS_OFF
)
190 mscan_set_mode(dev
, MSCAN_INIT_MODE
);
191 return mscan_start(dev
);
197 static netdev_tx_t
mscan_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
199 struct can_frame
*frame
= (struct can_frame
*)skb
->data
;
200 struct mscan_priv
*priv
= netdev_priv(dev
);
201 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
205 if (can_dropped_invalid_skb(dev
, skb
))
208 out_8(®s
->cantier
, 0);
210 i
= ~priv
->tx_active
& MSCAN_TXE
;
212 switch (hweight8(i
)) {
214 netif_stop_queue(dev
);
215 netdev_err(dev
, "Tx Ring full when queue awake!\n");
216 return NETDEV_TX_BUSY
;
219 * if buf_id < 3, then current frame will be send out of order,
220 * since buffer with lower id have higher priority (hell..)
222 netif_stop_queue(dev
);
224 if (buf_id
< priv
->prev_buf_id
) {
226 if (priv
->cur_pri
== 0xff) {
227 set_bit(F_TX_WAIT_ALL
, &priv
->flags
);
228 netif_stop_queue(dev
);
231 set_bit(F_TX_PROGRESS
, &priv
->flags
);
234 priv
->prev_buf_id
= buf_id
;
235 out_8(®s
->cantbsel
, i
);
237 rtr
= frame
->can_id
& CAN_RTR_FLAG
;
239 /* RTR is always the lowest bit of interest, then IDs follow */
240 if (frame
->can_id
& CAN_EFF_FLAG
) {
241 can_id
= (frame
->can_id
& CAN_EFF_MASK
)
242 << (MSCAN_EFF_RTR_SHIFT
+ 1);
244 can_id
|= 1 << MSCAN_EFF_RTR_SHIFT
;
245 out_be16(®s
->tx
.idr3_2
, can_id
);
248 /* EFF_FLAGS are between the IDs :( */
249 can_id
= (can_id
& 0x7) | ((can_id
<< 2) & 0xffe0)
252 can_id
= (frame
->can_id
& CAN_SFF_MASK
)
253 << (MSCAN_SFF_RTR_SHIFT
+ 1);
255 can_id
|= 1 << MSCAN_SFF_RTR_SHIFT
;
257 out_be16(®s
->tx
.idr1_0
, can_id
);
260 void __iomem
*data
= ®s
->tx
.dsr1_0
;
261 u16
*payload
= (u16
*)frame
->data
;
263 for (i
= 0; i
< frame
->can_dlc
/ 2; i
++) {
264 out_be16(data
, *payload
++);
265 data
+= 2 + _MSCAN_RESERVED_DSR_SIZE
;
267 /* write remaining byte if necessary */
268 if (frame
->can_dlc
& 1)
269 out_8(data
, frame
->data
[frame
->can_dlc
- 1]);
272 out_8(®s
->tx
.dlr
, frame
->can_dlc
);
273 out_8(®s
->tx
.tbpr
, priv
->cur_pri
);
275 /* Start transmission. */
276 out_8(®s
->cantflg
, 1 << buf_id
);
278 if (!test_bit(F_TX_PROGRESS
, &priv
->flags
))
279 dev
->trans_start
= jiffies
;
281 list_add_tail(&priv
->tx_queue
[buf_id
].list
, &priv
->tx_head
);
283 can_put_echo_skb(skb
, dev
, buf_id
);
285 /* Enable interrupt. */
286 priv
->tx_active
|= 1 << buf_id
;
287 out_8(®s
->cantier
, priv
->tx_active
);
292 static enum can_state
get_new_state(struct net_device
*dev
, u8 canrflg
)
294 struct mscan_priv
*priv
= netdev_priv(dev
);
296 if (unlikely(canrflg
& MSCAN_CSCIF
))
297 return state_map
[max(MSCAN_STATE_RX(canrflg
),
298 MSCAN_STATE_TX(canrflg
))];
300 return priv
->can
.state
;
303 static void mscan_get_rx_frame(struct net_device
*dev
, struct can_frame
*frame
)
305 struct mscan_priv
*priv
= netdev_priv(dev
);
306 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
310 can_id
= in_be16(®s
->rx
.idr1_0
);
311 if (can_id
& (1 << 3)) {
312 frame
->can_id
= CAN_EFF_FLAG
;
313 can_id
= ((can_id
<< 16) | in_be16(®s
->rx
.idr3_2
));
314 can_id
= ((can_id
& 0xffe00000) |
315 ((can_id
& 0x7ffff) << 2)) >> 2;
321 frame
->can_id
|= can_id
>> 1;
323 frame
->can_id
|= CAN_RTR_FLAG
;
325 frame
->can_dlc
= get_can_dlc(in_8(®s
->rx
.dlr
) & 0xf);
327 if (!(frame
->can_id
& CAN_RTR_FLAG
)) {
328 void __iomem
*data
= ®s
->rx
.dsr1_0
;
329 u16
*payload
= (u16
*)frame
->data
;
331 for (i
= 0; i
< frame
->can_dlc
/ 2; i
++) {
332 *payload
++ = in_be16(data
);
333 data
+= 2 + _MSCAN_RESERVED_DSR_SIZE
;
335 /* read remaining byte if necessary */
336 if (frame
->can_dlc
& 1)
337 frame
->data
[frame
->can_dlc
- 1] = in_8(data
);
340 out_8(®s
->canrflg
, MSCAN_RXF
);
343 static void mscan_get_err_frame(struct net_device
*dev
, struct can_frame
*frame
,
346 struct mscan_priv
*priv
= netdev_priv(dev
);
347 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
348 struct net_device_stats
*stats
= &dev
->stats
;
349 enum can_state new_state
;
351 netdev_dbg(dev
, "error interrupt (canrflg=%#x)\n", canrflg
);
352 frame
->can_id
= CAN_ERR_FLAG
;
354 if (canrflg
& MSCAN_OVRIF
) {
355 frame
->can_id
|= CAN_ERR_CRTL
;
356 frame
->data
[1] = CAN_ERR_CRTL_RX_OVERFLOW
;
357 stats
->rx_over_errors
++;
363 new_state
= get_new_state(dev
, canrflg
);
364 if (new_state
!= priv
->can
.state
) {
365 can_change_state(dev
, frame
,
366 state_map
[MSCAN_STATE_TX(canrflg
)],
367 state_map
[MSCAN_STATE_RX(canrflg
)]);
369 if (priv
->can
.state
== CAN_STATE_BUS_OFF
) {
371 * The MSCAN on the MPC5200 does recover from bus-off
372 * automatically. To avoid that we stop the chip doing
373 * a light-weight stop (we are in irq-context).
375 if (priv
->type
!= MSCAN_TYPE_MPC5121
) {
376 out_8(®s
->cantier
, 0);
377 out_8(®s
->canrier
, 0);
378 setbits8(®s
->canctl0
,
379 MSCAN_SLPRQ
| MSCAN_INITRQ
);
384 priv
->shadow_statflg
= canrflg
& MSCAN_STAT_MSK
;
385 frame
->can_dlc
= CAN_ERR_DLC
;
386 out_8(®s
->canrflg
, MSCAN_ERR_IF
);
389 static int mscan_rx_poll(struct napi_struct
*napi
, int quota
)
391 struct mscan_priv
*priv
= container_of(napi
, struct mscan_priv
, napi
);
392 struct net_device
*dev
= napi
->dev
;
393 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
394 struct net_device_stats
*stats
= &dev
->stats
;
398 struct can_frame
*frame
;
401 while (npackets
< quota
) {
402 canrflg
= in_8(®s
->canrflg
);
403 if (!(canrflg
& (MSCAN_RXF
| MSCAN_ERR_IF
)))
406 skb
= alloc_can_skb(dev
, &frame
);
408 if (printk_ratelimit())
409 netdev_notice(dev
, "packet dropped\n");
411 out_8(®s
->canrflg
, canrflg
);
415 if (canrflg
& MSCAN_RXF
)
416 mscan_get_rx_frame(dev
, frame
);
417 else if (canrflg
& MSCAN_ERR_IF
)
418 mscan_get_err_frame(dev
, frame
, canrflg
);
421 stats
->rx_bytes
+= frame
->can_dlc
;
423 netif_receive_skb(skb
);
426 if (!(in_8(®s
->canrflg
) & (MSCAN_RXF
| MSCAN_ERR_IF
))) {
427 napi_complete(&priv
->napi
);
428 clear_bit(F_RX_PROGRESS
, &priv
->flags
);
429 if (priv
->can
.state
< CAN_STATE_BUS_OFF
)
430 out_8(®s
->canrier
, priv
->shadow_canrier
);
436 static irqreturn_t
mscan_isr(int irq
, void *dev_id
)
438 struct net_device
*dev
= (struct net_device
*)dev_id
;
439 struct mscan_priv
*priv
= netdev_priv(dev
);
440 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
441 struct net_device_stats
*stats
= &dev
->stats
;
442 u8 cantier
, cantflg
, canrflg
;
443 irqreturn_t ret
= IRQ_NONE
;
445 cantier
= in_8(®s
->cantier
) & MSCAN_TXE
;
446 cantflg
= in_8(®s
->cantflg
) & cantier
;
448 if (cantier
&& cantflg
) {
449 struct list_head
*tmp
, *pos
;
451 list_for_each_safe(pos
, tmp
, &priv
->tx_head
) {
452 struct tx_queue_entry
*entry
=
453 list_entry(pos
, struct tx_queue_entry
, list
);
454 u8 mask
= entry
->mask
;
456 if (!(cantflg
& mask
))
459 out_8(®s
->cantbsel
, mask
);
460 stats
->tx_bytes
+= in_8(®s
->tx
.dlr
);
462 can_get_echo_skb(dev
, entry
->id
);
463 priv
->tx_active
&= ~mask
;
467 if (list_empty(&priv
->tx_head
)) {
468 clear_bit(F_TX_WAIT_ALL
, &priv
->flags
);
469 clear_bit(F_TX_PROGRESS
, &priv
->flags
);
472 dev
->trans_start
= jiffies
;
475 if (!test_bit(F_TX_WAIT_ALL
, &priv
->flags
))
476 netif_wake_queue(dev
);
478 out_8(®s
->cantier
, priv
->tx_active
);
482 canrflg
= in_8(®s
->canrflg
);
483 if ((canrflg
& ~MSCAN_STAT_MSK
) &&
484 !test_and_set_bit(F_RX_PROGRESS
, &priv
->flags
)) {
485 if (canrflg
& ~MSCAN_STAT_MSK
) {
486 priv
->shadow_canrier
= in_8(®s
->canrier
);
487 out_8(®s
->canrier
, 0);
488 napi_schedule(&priv
->napi
);
491 clear_bit(F_RX_PROGRESS
, &priv
->flags
);
497 static int mscan_do_set_mode(struct net_device
*dev
, enum can_mode mode
)
503 ret
= mscan_restart(dev
);
506 if (netif_queue_stopped(dev
))
507 netif_wake_queue(dev
);
517 static int mscan_do_set_bittiming(struct net_device
*dev
)
519 struct mscan_priv
*priv
= netdev_priv(dev
);
520 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
521 struct can_bittiming
*bt
= &priv
->can
.bittiming
;
524 btr0
= BTR0_SET_BRP(bt
->brp
) | BTR0_SET_SJW(bt
->sjw
);
525 btr1
= (BTR1_SET_TSEG1(bt
->prop_seg
+ bt
->phase_seg1
) |
526 BTR1_SET_TSEG2(bt
->phase_seg2
) |
527 BTR1_SET_SAM(priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
));
529 netdev_info(dev
, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0
, btr1
);
531 out_8(®s
->canbtr0
, btr0
);
532 out_8(®s
->canbtr1
, btr1
);
537 static int mscan_get_berr_counter(const struct net_device
*dev
,
538 struct can_berr_counter
*bec
)
540 struct mscan_priv
*priv
= netdev_priv(dev
);
541 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
543 bec
->txerr
= in_8(®s
->cantxerr
);
544 bec
->rxerr
= in_8(®s
->canrxerr
);
549 static int mscan_open(struct net_device
*dev
)
552 struct mscan_priv
*priv
= netdev_priv(dev
);
553 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
556 ret
= clk_prepare_enable(priv
->clk_ipg
);
561 ret
= clk_prepare_enable(priv
->clk_can
);
563 goto exit_dis_ipg_clock
;
567 ret
= open_candev(dev
);
569 goto exit_dis_can_clock
;
571 napi_enable(&priv
->napi
);
573 ret
= request_irq(dev
->irq
, mscan_isr
, 0, dev
->name
, dev
);
575 netdev_err(dev
, "failed to attach interrupt\n");
576 goto exit_napi_disable
;
579 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
)
580 setbits8(®s
->canctl1
, MSCAN_LISTEN
);
582 clrbits8(®s
->canctl1
, MSCAN_LISTEN
);
584 ret
= mscan_start(dev
);
588 netif_start_queue(dev
);
593 free_irq(dev
->irq
, dev
);
595 napi_disable(&priv
->napi
);
599 clk_disable_unprepare(priv
->clk_can
);
602 clk_disable_unprepare(priv
->clk_ipg
);
607 static int mscan_close(struct net_device
*dev
)
609 struct mscan_priv
*priv
= netdev_priv(dev
);
610 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
612 netif_stop_queue(dev
);
613 napi_disable(&priv
->napi
);
615 out_8(®s
->cantier
, 0);
616 out_8(®s
->canrier
, 0);
617 mscan_set_mode(dev
, MSCAN_INIT_MODE
);
619 free_irq(dev
->irq
, dev
);
622 clk_disable_unprepare(priv
->clk_can
);
624 clk_disable_unprepare(priv
->clk_ipg
);
629 static const struct net_device_ops mscan_netdev_ops
= {
630 .ndo_open
= mscan_open
,
631 .ndo_stop
= mscan_close
,
632 .ndo_start_xmit
= mscan_start_xmit
,
633 .ndo_change_mtu
= can_change_mtu
,
636 int register_mscandev(struct net_device
*dev
, int mscan_clksrc
)
638 struct mscan_priv
*priv
= netdev_priv(dev
);
639 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
642 ctl1
= in_8(®s
->canctl1
);
644 ctl1
|= MSCAN_CLKSRC
;
646 ctl1
&= ~MSCAN_CLKSRC
;
648 if (priv
->type
== MSCAN_TYPE_MPC5121
) {
649 priv
->can
.do_get_berr_counter
= mscan_get_berr_counter
;
650 ctl1
|= MSCAN_BORM
; /* bus-off recovery upon request */
654 out_8(®s
->canctl1
, ctl1
);
657 /* acceptance mask/acceptance code (accept everything) */
658 out_be16(®s
->canidar1_0
, 0);
659 out_be16(®s
->canidar3_2
, 0);
660 out_be16(®s
->canidar5_4
, 0);
661 out_be16(®s
->canidar7_6
, 0);
663 out_be16(®s
->canidmr1_0
, 0xffff);
664 out_be16(®s
->canidmr3_2
, 0xffff);
665 out_be16(®s
->canidmr5_4
, 0xffff);
666 out_be16(®s
->canidmr7_6
, 0xffff);
667 /* Two 32 bit Acceptance Filters */
668 out_8(®s
->canidac
, MSCAN_AF_32BIT
);
670 mscan_set_mode(dev
, MSCAN_INIT_MODE
);
672 return register_candev(dev
);
675 void unregister_mscandev(struct net_device
*dev
)
677 struct mscan_priv
*priv
= netdev_priv(dev
);
678 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
679 mscan_set_mode(dev
, MSCAN_INIT_MODE
);
680 clrbits8(®s
->canctl1
, MSCAN_CANE
);
681 unregister_candev(dev
);
684 struct net_device
*alloc_mscandev(void)
686 struct net_device
*dev
;
687 struct mscan_priv
*priv
;
690 dev
= alloc_candev(sizeof(struct mscan_priv
), MSCAN_ECHO_SKB_MAX
);
693 priv
= netdev_priv(dev
);
695 dev
->netdev_ops
= &mscan_netdev_ops
;
697 dev
->flags
|= IFF_ECHO
; /* we support local echo */
699 netif_napi_add(dev
, &priv
->napi
, mscan_rx_poll
, 8);
701 priv
->can
.bittiming_const
= &mscan_bittiming_const
;
702 priv
->can
.do_set_bittiming
= mscan_do_set_bittiming
;
703 priv
->can
.do_set_mode
= mscan_do_set_mode
;
704 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_3_SAMPLES
|
705 CAN_CTRLMODE_LISTENONLY
;
707 for (i
= 0; i
< TX_QUEUE_SIZE
; i
++) {
708 priv
->tx_queue
[i
].id
= i
;
709 priv
->tx_queue
[i
].mask
= 1 << i
;
715 MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
716 MODULE_LICENSE("GPL v2");
717 MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");