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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / net / can / spi / mcp251x.c
blobc66d699640a9c1478026da5df023264a7b1ff973
1 /*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see <http://www.gnu.org/licenses/>.
32 *
33 *
34 *
35 * Your platform definition file should specify something like:
36 *
37 * static struct mcp251x_platform_data mcp251x_info = {
38 * .oscillator_frequency = 8000000,
39 * };
40 *
41 * static struct spi_board_info spi_board_info[] = {
42 * {
43 * .modalias = "mcp2510",
44 * // or "mcp2515" depending on your controller
45 * .platform_data = &mcp251x_info,
46 * .irq = IRQ_EINT13,
47 * .max_speed_hz = 2*1000*1000,
48 * .chip_select = 2,
49 * },
50 * };
51 *
52 * Please see mcp251x.h for a description of the fields in
53 * struct mcp251x_platform_data.
54 *
55 */
56
57 #include <linux/can/core.h>
58 #include <linux/can/dev.h>
59 #include <linux/can/led.h>
60 #include <linux/can/platform/mcp251x.h>
61 #include <linux/clk.h>
62 #include <linux/completion.h>
63 #include <linux/delay.h>
64 #include <linux/device.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/freezer.h>
67 #include <linux/interrupt.h>
68 #include <linux/io.h>
69 #include <linux/kernel.h>
70 #include <linux/module.h>
71 #include <linux/netdevice.h>
72 #include <linux/of.h>
73 #include <linux/of_device.h>
74 #include <linux/platform_device.h>
75 #include <linux/slab.h>
76 #include <linux/spi/spi.h>
77 #include <linux/uaccess.h>
78 #include <linux/regulator/consumer.h>
79
80 /* SPI interface instruction set */
81 #define INSTRUCTION_WRITE 0x02
82 #define INSTRUCTION_READ 0x03
83 #define INSTRUCTION_BIT_MODIFY 0x05
84 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
85 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
86 #define INSTRUCTION_RESET 0xC0
87 #define RTS_TXB0 0x01
88 #define RTS_TXB1 0x02
89 #define RTS_TXB2 0x04
90 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
91
92
93 /* MPC251x registers */
94 #define CANSTAT 0x0e
95 #define CANCTRL 0x0f
96 # define CANCTRL_REQOP_MASK 0xe0
97 # define CANCTRL_REQOP_CONF 0x80
98 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
99 # define CANCTRL_REQOP_LOOPBACK 0x40
100 # define CANCTRL_REQOP_SLEEP 0x20
101 # define CANCTRL_REQOP_NORMAL 0x00
102 # define CANCTRL_OSM 0x08
103 # define CANCTRL_ABAT 0x10
104 #define TEC 0x1c
105 #define REC 0x1d
106 #define CNF1 0x2a
107 # define CNF1_SJW_SHIFT 6
108 #define CNF2 0x29
109 # define CNF2_BTLMODE 0x80
110 # define CNF2_SAM 0x40
111 # define CNF2_PS1_SHIFT 3
112 #define CNF3 0x28
113 # define CNF3_SOF 0x08
114 # define CNF3_WAKFIL 0x04
115 # define CNF3_PHSEG2_MASK 0x07
116 #define CANINTE 0x2b
117 # define CANINTE_MERRE 0x80
118 # define CANINTE_WAKIE 0x40
119 # define CANINTE_ERRIE 0x20
120 # define CANINTE_TX2IE 0x10
121 # define CANINTE_TX1IE 0x08
122 # define CANINTE_TX0IE 0x04
123 # define CANINTE_RX1IE 0x02
124 # define CANINTE_RX0IE 0x01
125 #define CANINTF 0x2c
126 # define CANINTF_MERRF 0x80
127 # define CANINTF_WAKIF 0x40
128 # define CANINTF_ERRIF 0x20
129 # define CANINTF_TX2IF 0x10
130 # define CANINTF_TX1IF 0x08
131 # define CANINTF_TX0IF 0x04
132 # define CANINTF_RX1IF 0x02
133 # define CANINTF_RX0IF 0x01
134 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
135 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
136 # define CANINTF_ERR (CANINTF_ERRIF)
137 #define EFLG 0x2d
138 # define EFLG_EWARN 0x01
139 # define EFLG_RXWAR 0x02
140 # define EFLG_TXWAR 0x04
141 # define EFLG_RXEP 0x08
142 # define EFLG_TXEP 0x10
143 # define EFLG_TXBO 0x20
144 # define EFLG_RX0OVR 0x40
145 # define EFLG_RX1OVR 0x80
146 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
147 # define TXBCTRL_ABTF 0x40
148 # define TXBCTRL_MLOA 0x20
149 # define TXBCTRL_TXERR 0x10
150 # define TXBCTRL_TXREQ 0x08
151 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
152 # define SIDH_SHIFT 3
153 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
154 # define SIDL_SID_MASK 7
155 # define SIDL_SID_SHIFT 5
156 # define SIDL_EXIDE_SHIFT 3
157 # define SIDL_EID_SHIFT 16
158 # define SIDL_EID_MASK 3
159 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
160 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
161 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
162 # define DLC_RTR_SHIFT 6
163 #define TXBCTRL_OFF 0
164 #define TXBSIDH_OFF 1
165 #define TXBSIDL_OFF 2
166 #define TXBEID8_OFF 3
167 #define TXBEID0_OFF 4
168 #define TXBDLC_OFF 5
169 #define TXBDAT_OFF 6
170 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
171 # define RXBCTRL_BUKT 0x04
172 # define RXBCTRL_RXM0 0x20
173 # define RXBCTRL_RXM1 0x40
174 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
175 # define RXBSIDH_SHIFT 3
176 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
177 # define RXBSIDL_IDE 0x08
178 # define RXBSIDL_SRR 0x10
179 # define RXBSIDL_EID 3
180 # define RXBSIDL_SHIFT 5
181 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
182 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
183 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
184 # define RXBDLC_LEN_MASK 0x0f
185 # define RXBDLC_RTR 0x40
186 #define RXBCTRL_OFF 0
187 #define RXBSIDH_OFF 1
188 #define RXBSIDL_OFF 2
189 #define RXBEID8_OFF 3
190 #define RXBEID0_OFF 4
191 #define RXBDLC_OFF 5
192 #define RXBDAT_OFF 6
193 #define RXFSIDH(n) ((n) * 4)
194 #define RXFSIDL(n) ((n) * 4 + 1)
195 #define RXFEID8(n) ((n) * 4 + 2)
196 #define RXFEID0(n) ((n) * 4 + 3)
197 #define RXMSIDH(n) ((n) * 4 + 0x20)
198 #define RXMSIDL(n) ((n) * 4 + 0x21)
199 #define RXMEID8(n) ((n) * 4 + 0x22)
200 #define RXMEID0(n) ((n) * 4 + 0x23)
201
202 #define GET_BYTE(val, byte) \
203 (((val) >> ((byte) * 8)) & 0xff)
204 #define SET_BYTE(val, byte) \
205 (((val) & 0xff) << ((byte) * 8))
206
207 /*
208 * Buffer size required for the largest SPI transfer (i.e., reading a
209 * frame)
210 */
211 #define CAN_FRAME_MAX_DATA_LEN 8
212 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
213 #define CAN_FRAME_MAX_BITS 128
214
215 #define TX_ECHO_SKB_MAX 1
216
217 #define MCP251X_OST_DELAY_MS (5)
218
219 #define DEVICE_NAME "mcp251x"
220
221 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
222 module_param(mcp251x_enable_dma, int, S_IRUGO);
223 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
224
225 static const struct can_bittiming_const mcp251x_bittiming_const = {
226 .name = DEVICE_NAME,
227 .tseg1_min = 3,
228 .tseg1_max = 16,
229 .tseg2_min = 2,
230 .tseg2_max = 8,
231 .sjw_max = 4,
232 .brp_min = 1,
233 .brp_max = 64,
234 .brp_inc = 1,
235 };
236
237 enum mcp251x_model {
238 CAN_MCP251X_MCP2510 = 0x2510,
239 CAN_MCP251X_MCP2515 = 0x2515,
240 };
241
242 struct mcp251x_priv {
243 struct can_priv can;
244 struct net_device *net;
245 struct spi_device *spi;
246 enum mcp251x_model model;
247
248 struct mutex mcp_lock; /* SPI device lock */
249
250 u8 *spi_tx_buf;
251 u8 *spi_rx_buf;
252 dma_addr_t spi_tx_dma;
253 dma_addr_t spi_rx_dma;
254
255 struct sk_buff *tx_skb;
256 int tx_len;
257
258 struct workqueue_struct *wq;
259 struct work_struct tx_work;
260 struct work_struct restart_work;
261
262 int force_quit;
263 int after_suspend;
264 #define AFTER_SUSPEND_UP 1
265 #define AFTER_SUSPEND_DOWN 2
266 #define AFTER_SUSPEND_POWER 4
267 #define AFTER_SUSPEND_RESTART 8
268 int restart_tx;
269 struct regulator *power;
270 struct regulator *transceiver;
271 struct clk *clk;
272 };
273
274 #define MCP251X_IS(_model) \
275 static inline int mcp251x_is_##_model(struct spi_device *spi) \
276 { \
277 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
278 return priv->model == CAN_MCP251X_MCP##_model; \
279 }
280
281 MCP251X_IS(2510);
282 MCP251X_IS(2515);
283
284 static void mcp251x_clean(struct net_device *net)
285 {
286 struct mcp251x_priv *priv = netdev_priv(net);
287
288 if (priv->tx_skb || priv->tx_len)
289 net->stats.tx_errors++;
290 if (priv->tx_skb)
291 dev_kfree_skb(priv->tx_skb);
292 if (priv->tx_len)
293 can_free_echo_skb(priv->net, 0);
294 priv->tx_skb = NULL;
295 priv->tx_len = 0;
296 }
297
298 /*
299 * Note about handling of error return of mcp251x_spi_trans: accessing
300 * registers via SPI is not really different conceptually than using
301 * normal I/O assembler instructions, although it's much more
302 * complicated from a practical POV. So it's not advisable to always
303 * check the return value of this function. Imagine that every
304 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
305 * error();", it would be a great mess (well there are some situation
306 * when exception handling C++ like could be useful after all). So we
307 * just check that transfers are OK at the beginning of our
308 * conversation with the chip and to avoid doing really nasty things
309 * (like injecting bogus packets in the network stack).
310 */
311 static int mcp251x_spi_trans(struct spi_device *spi, int len)
312 {
313 struct mcp251x_priv *priv = spi_get_drvdata(spi);
314 struct spi_transfer t = {
315 .tx_buf = priv->spi_tx_buf,
316 .rx_buf = priv->spi_rx_buf,
317 .len = len,
318 .cs_change = 0,
319 };
320 struct spi_message m;
321 int ret;
322
323 spi_message_init(&m);
324
325 if (mcp251x_enable_dma) {
326 t.tx_dma = priv->spi_tx_dma;
327 t.rx_dma = priv->spi_rx_dma;
328 m.is_dma_mapped = 1;
329 }
330
331 spi_message_add_tail(&t, &m);
332
333 ret = spi_sync(spi, &m);
334 if (ret)
335 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
336 return ret;
337 }
338
339 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
340 {
341 struct mcp251x_priv *priv = spi_get_drvdata(spi);
342 u8 val = 0;
343
344 priv->spi_tx_buf[0] = INSTRUCTION_READ;
345 priv->spi_tx_buf[1] = reg;
346
347 mcp251x_spi_trans(spi, 3);
348 val = priv->spi_rx_buf[2];
349
350 return val;
351 }
352
353 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
354 uint8_t *v1, uint8_t *v2)
355 {
356 struct mcp251x_priv *priv = spi_get_drvdata(spi);
357
358 priv->spi_tx_buf[0] = INSTRUCTION_READ;
359 priv->spi_tx_buf[1] = reg;
360
361 mcp251x_spi_trans(spi, 4);
362
363 *v1 = priv->spi_rx_buf[2];
364 *v2 = priv->spi_rx_buf[3];
365 }
366
367 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
368 {
369 struct mcp251x_priv *priv = spi_get_drvdata(spi);
370
371 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
372 priv->spi_tx_buf[1] = reg;
373 priv->spi_tx_buf[2] = val;
374
375 mcp251x_spi_trans(spi, 3);
376 }
377
378 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
379 u8 mask, uint8_t val)
380 {
381 struct mcp251x_priv *priv = spi_get_drvdata(spi);
382
383 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
384 priv->spi_tx_buf[1] = reg;
385 priv->spi_tx_buf[2] = mask;
386 priv->spi_tx_buf[3] = val;
387
388 mcp251x_spi_trans(spi, 4);
389 }
390
391 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
392 int len, int tx_buf_idx)
393 {
394 struct mcp251x_priv *priv = spi_get_drvdata(spi);
395
396 if (mcp251x_is_2510(spi)) {
397 int i;
398
399 for (i = 1; i < TXBDAT_OFF + len; i++)
400 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
401 buf[i]);
402 } else {
403 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
404 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
405 }
406 }
407
408 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
409 int tx_buf_idx)
410 {
411 struct mcp251x_priv *priv = spi_get_drvdata(spi);
412 u32 sid, eid, exide, rtr;
413 u8 buf[SPI_TRANSFER_BUF_LEN];
414
415 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
416 if (exide)
417 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
418 else
419 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
420 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
421 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
422
423 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
424 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
425 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
426 (exide << SIDL_EXIDE_SHIFT) |
427 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
428 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
429 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
430 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
431 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
432 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
433
434 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
435 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
436 mcp251x_spi_trans(priv->spi, 1);
437 }
438
439 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
440 int buf_idx)
441 {
442 struct mcp251x_priv *priv = spi_get_drvdata(spi);
443
444 if (mcp251x_is_2510(spi)) {
445 int i, len;
446
447 for (i = 1; i < RXBDAT_OFF; i++)
448 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
449
450 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
451 for (; i < (RXBDAT_OFF + len); i++)
452 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
453 } else {
454 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
455 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
456 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
457 }
458 }
459
460 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
461 {
462 struct mcp251x_priv *priv = spi_get_drvdata(spi);
463 struct sk_buff *skb;
464 struct can_frame *frame;
465 u8 buf[SPI_TRANSFER_BUF_LEN];
466
467 skb = alloc_can_skb(priv->net, &frame);
468 if (!skb) {
469 dev_err(&spi->dev, "cannot allocate RX skb\n");
470 priv->net->stats.rx_dropped++;
471 return;
472 }
473
474 mcp251x_hw_rx_frame(spi, buf, buf_idx);
475 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
476 /* Extended ID format */
477 frame->can_id = CAN_EFF_FLAG;
478 frame->can_id |=
479 /* Extended ID part */
480 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
481 SET_BYTE(buf[RXBEID8_OFF], 1) |
482 SET_BYTE(buf[RXBEID0_OFF], 0) |
483 /* Standard ID part */
484 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
485 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
486 /* Remote transmission request */
487 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
488 frame->can_id |= CAN_RTR_FLAG;
489 } else {
490 /* Standard ID format */
491 frame->can_id =
492 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
493 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
494 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
495 frame->can_id |= CAN_RTR_FLAG;
496 }
497 /* Data length */
498 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
499 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
500
501 priv->net->stats.rx_packets++;
502 priv->net->stats.rx_bytes += frame->can_dlc;
503
504 can_led_event(priv->net, CAN_LED_EVENT_RX);
505
506 netif_rx_ni(skb);
507 }
508
509 static void mcp251x_hw_sleep(struct spi_device *spi)
510 {
511 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
512 }
513
514 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
515 struct net_device *net)
516 {
517 struct mcp251x_priv *priv = netdev_priv(net);
518 struct spi_device *spi = priv->spi;
519
520 if (priv->tx_skb || priv->tx_len) {
521 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
522 return NETDEV_TX_BUSY;
523 }
524
525 if (can_dropped_invalid_skb(net, skb))
526 return NETDEV_TX_OK;
527
528 netif_stop_queue(net);
529 priv->tx_skb = skb;
530 queue_work(priv->wq, &priv->tx_work);
531
532 return NETDEV_TX_OK;
533 }
534
535 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
536 {
537 struct mcp251x_priv *priv = netdev_priv(net);
538
539 switch (mode) {
540 case CAN_MODE_START:
541 mcp251x_clean(net);
542 /* We have to delay work since SPI I/O may sleep */
543 priv->can.state = CAN_STATE_ERROR_ACTIVE;
544 priv->restart_tx = 1;
545 if (priv->can.restart_ms == 0)
546 priv->after_suspend = AFTER_SUSPEND_RESTART;
547 queue_work(priv->wq, &priv->restart_work);
548 break;
549 default:
550 return -EOPNOTSUPP;
551 }
552
553 return 0;
554 }
555
556 static int mcp251x_set_normal_mode(struct spi_device *spi)
557 {
558 struct mcp251x_priv *priv = spi_get_drvdata(spi);
559 unsigned long timeout;
560
561 /* Enable interrupts */
562 mcp251x_write_reg(spi, CANINTE,
563 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
564 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
565
566 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
567 /* Put device into loopback mode */
568 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
569 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
570 /* Put device into listen-only mode */
571 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
572 } else {
573 /* Put device into normal mode */
574 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
575
576 /* Wait for the device to enter normal mode */
577 timeout = jiffies + HZ;
578 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
579 schedule();
580 if (time_after(jiffies, timeout)) {
581 dev_err(&spi->dev, "MCP251x didn't"
582 " enter in normal mode\n");
583 return -EBUSY;
584 }
585 }
586 }
587 priv->can.state = CAN_STATE_ERROR_ACTIVE;
588 return 0;
589 }
590
591 static int mcp251x_do_set_bittiming(struct net_device *net)
592 {
593 struct mcp251x_priv *priv = netdev_priv(net);
594 struct can_bittiming *bt = &priv->can.bittiming;
595 struct spi_device *spi = priv->spi;
596
597 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
598 (bt->brp - 1));
599 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
600 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
601 CNF2_SAM : 0) |
602 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
603 (bt->prop_seg - 1));
604 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
605 (bt->phase_seg2 - 1));
606 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
607 mcp251x_read_reg(spi, CNF1),
608 mcp251x_read_reg(spi, CNF2),
609 mcp251x_read_reg(spi, CNF3));
610
611 return 0;
612 }
613
614 static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
615 struct spi_device *spi)
616 {
617 mcp251x_do_set_bittiming(net);
618
619 mcp251x_write_reg(spi, RXBCTRL(0),
620 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
621 mcp251x_write_reg(spi, RXBCTRL(1),
622 RXBCTRL_RXM0 | RXBCTRL_RXM1);
623 return 0;
624 }
625
626 static int mcp251x_hw_reset(struct spi_device *spi)
627 {
628 struct mcp251x_priv *priv = spi_get_drvdata(spi);
629 u8 reg;
630 int ret;
631
632 /* Wait for oscillator startup timer after power up */
633 mdelay(MCP251X_OST_DELAY_MS);
634
635 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
636 ret = mcp251x_spi_trans(spi, 1);
637 if (ret)
638 return ret;
639
640 /* Wait for oscillator startup timer after reset */
641 mdelay(MCP251X_OST_DELAY_MS);
642
643 reg = mcp251x_read_reg(spi, CANSTAT);
644 if ((reg & CANCTRL_REQOP_MASK) != CANCTRL_REQOP_CONF)
645 return -ENODEV;
646
647 return 0;
648 }
649
650 static int mcp251x_hw_probe(struct spi_device *spi)
651 {
652 u8 ctrl;
653 int ret;
654
655 ret = mcp251x_hw_reset(spi);
656 if (ret)
657 return ret;
658
659 ctrl = mcp251x_read_reg(spi, CANCTRL);
660
661 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
662
663 /* Check for power up default value */
664 if ((ctrl & 0x17) != 0x07)
665 return -ENODEV;
666
667 return 0;
668 }
669
670 static int mcp251x_power_enable(struct regulator *reg, int enable)
671 {
672 if (IS_ERR_OR_NULL(reg))
673 return 0;
674
675 if (enable)
676 return regulator_enable(reg);
677 else
678 return regulator_disable(reg);
679 }
680
681 static void mcp251x_open_clean(struct net_device *net)
682 {
683 struct mcp251x_priv *priv = netdev_priv(net);
684 struct spi_device *spi = priv->spi;
685
686 free_irq(spi->irq, priv);
687 mcp251x_hw_sleep(spi);
688 mcp251x_power_enable(priv->transceiver, 0);
689 close_candev(net);
690 }
691
692 static int mcp251x_stop(struct net_device *net)
693 {
694 struct mcp251x_priv *priv = netdev_priv(net);
695 struct spi_device *spi = priv->spi;
696
697 close_candev(net);
698
699 priv->force_quit = 1;
700 free_irq(spi->irq, priv);
701 destroy_workqueue(priv->wq);
702 priv->wq = NULL;
703
704 mutex_lock(&priv->mcp_lock);
705
706 /* Disable and clear pending interrupts */
707 mcp251x_write_reg(spi, CANINTE, 0x00);
708 mcp251x_write_reg(spi, CANINTF, 0x00);
709
710 mcp251x_write_reg(spi, TXBCTRL(0), 0);
711 mcp251x_clean(net);
712
713 mcp251x_hw_sleep(spi);
714
715 mcp251x_power_enable(priv->transceiver, 0);
716
717 priv->can.state = CAN_STATE_STOPPED;
718
719 mutex_unlock(&priv->mcp_lock);
720
721 can_led_event(net, CAN_LED_EVENT_STOP);
722
723 return 0;
724 }
725
726 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
727 {
728 struct sk_buff *skb;
729 struct can_frame *frame;
730
731 skb = alloc_can_err_skb(net, &frame);
732 if (skb) {
733 frame->can_id |= can_id;
734 frame->data[1] = data1;
735 netif_rx_ni(skb);
736 } else {
737 netdev_err(net, "cannot allocate error skb\n");
738 }
739 }
740
741 static void mcp251x_tx_work_handler(struct work_struct *ws)
742 {
743 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
744 tx_work);
745 struct spi_device *spi = priv->spi;
746 struct net_device *net = priv->net;
747 struct can_frame *frame;
748
749 mutex_lock(&priv->mcp_lock);
750 if (priv->tx_skb) {
751 if (priv->can.state == CAN_STATE_BUS_OFF) {
752 mcp251x_clean(net);
753 } else {
754 frame = (struct can_frame *)priv->tx_skb->data;
755
756 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
757 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
758 mcp251x_hw_tx(spi, frame, 0);
759 priv->tx_len = 1 + frame->can_dlc;
760 can_put_echo_skb(priv->tx_skb, net, 0);
761 priv->tx_skb = NULL;
762 }
763 }
764 mutex_unlock(&priv->mcp_lock);
765 }
766
767 static void mcp251x_restart_work_handler(struct work_struct *ws)
768 {
769 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
770 restart_work);
771 struct spi_device *spi = priv->spi;
772 struct net_device *net = priv->net;
773
774 mutex_lock(&priv->mcp_lock);
775 if (priv->after_suspend) {
776 mcp251x_hw_reset(spi);
777 mcp251x_setup(net, priv, spi);
778 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
779 mcp251x_set_normal_mode(spi);
780 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
781 netif_device_attach(net);
782 mcp251x_clean(net);
783 mcp251x_set_normal_mode(spi);
784 netif_wake_queue(net);
785 } else {
786 mcp251x_hw_sleep(spi);
787 }
788 priv->after_suspend = 0;
789 priv->force_quit = 0;
790 }
791
792 if (priv->restart_tx) {
793 priv->restart_tx = 0;
794 mcp251x_write_reg(spi, TXBCTRL(0), 0);
795 mcp251x_clean(net);
796 netif_wake_queue(net);
797 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
798 }
799 mutex_unlock(&priv->mcp_lock);
800 }
801
802 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
803 {
804 struct mcp251x_priv *priv = dev_id;
805 struct spi_device *spi = priv->spi;
806 struct net_device *net = priv->net;
807
808 mutex_lock(&priv->mcp_lock);
809 while (!priv->force_quit) {
810 enum can_state new_state;
811 u8 intf, eflag;
812 u8 clear_intf = 0;
813 int can_id = 0, data1 = 0;
814
815 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
816
817 /* mask out flags we don't care about */
818 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
819
820 /* receive buffer 0 */
821 if (intf & CANINTF_RX0IF) {
822 mcp251x_hw_rx(spi, 0);
823 /*
824 * Free one buffer ASAP
825 * (The MCP2515 does this automatically.)
826 */
827 if (mcp251x_is_2510(spi))
828 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
829 }
830
831 /* receive buffer 1 */
832 if (intf & CANINTF_RX1IF) {
833 mcp251x_hw_rx(spi, 1);
834 /* the MCP2515 does this automatically */
835 if (mcp251x_is_2510(spi))
836 clear_intf |= CANINTF_RX1IF;
837 }
838
839 /* any error or tx interrupt we need to clear? */
840 if (intf & (CANINTF_ERR | CANINTF_TX))
841 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
842 if (clear_intf)
843 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
844
845 if (eflag)
846 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
847
848 /* Update can state */
849 if (eflag & EFLG_TXBO) {
850 new_state = CAN_STATE_BUS_OFF;
851 can_id |= CAN_ERR_BUSOFF;
852 } else if (eflag & EFLG_TXEP) {
853 new_state = CAN_STATE_ERROR_PASSIVE;
854 can_id |= CAN_ERR_CRTL;
855 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
856 } else if (eflag & EFLG_RXEP) {
857 new_state = CAN_STATE_ERROR_PASSIVE;
858 can_id |= CAN_ERR_CRTL;
859 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
860 } else if (eflag & EFLG_TXWAR) {
861 new_state = CAN_STATE_ERROR_WARNING;
862 can_id |= CAN_ERR_CRTL;
863 data1 |= CAN_ERR_CRTL_TX_WARNING;
864 } else if (eflag & EFLG_RXWAR) {
865 new_state = CAN_STATE_ERROR_WARNING;
866 can_id |= CAN_ERR_CRTL;
867 data1 |= CAN_ERR_CRTL_RX_WARNING;
868 } else {
869 new_state = CAN_STATE_ERROR_ACTIVE;
870 }
871
872 /* Update can state statistics */
873 switch (priv->can.state) {
874 case CAN_STATE_ERROR_ACTIVE:
875 if (new_state >= CAN_STATE_ERROR_WARNING &&
876 new_state <= CAN_STATE_BUS_OFF)
877 priv->can.can_stats.error_warning++;
878 case CAN_STATE_ERROR_WARNING: /* fallthrough */
879 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
880 new_state <= CAN_STATE_BUS_OFF)
881 priv->can.can_stats.error_passive++;
882 break;
883 default:
884 break;
885 }
886 priv->can.state = new_state;
887
888 if (intf & CANINTF_ERRIF) {
889 /* Handle overflow counters */
890 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
891 if (eflag & EFLG_RX0OVR) {
892 net->stats.rx_over_errors++;
893 net->stats.rx_errors++;
894 }
895 if (eflag & EFLG_RX1OVR) {
896 net->stats.rx_over_errors++;
897 net->stats.rx_errors++;
898 }
899 can_id |= CAN_ERR_CRTL;
900 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
901 }
902 mcp251x_error_skb(net, can_id, data1);
903 }
904
905 if (priv->can.state == CAN_STATE_BUS_OFF) {
906 if (priv->can.restart_ms == 0) {
907 priv->force_quit = 1;
908 can_bus_off(net);
909 mcp251x_hw_sleep(spi);
910 break;
911 }
912 }
913
914 if (intf == 0)
915 break;
916
917 if (intf & CANINTF_TX) {
918 net->stats.tx_packets++;
919 net->stats.tx_bytes += priv->tx_len - 1;
920 can_led_event(net, CAN_LED_EVENT_TX);
921 if (priv->tx_len) {
922 can_get_echo_skb(net, 0);
923 priv->tx_len = 0;
924 }
925 netif_wake_queue(net);
926 }
927
928 }
929 mutex_unlock(&priv->mcp_lock);
930 return IRQ_HANDLED;
931 }
932
933 static int mcp251x_open(struct net_device *net)
934 {
935 struct mcp251x_priv *priv = netdev_priv(net);
936 struct spi_device *spi = priv->spi;
937 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING;
938 int ret;
939
940 ret = open_candev(net);
941 if (ret) {
942 dev_err(&spi->dev, "unable to set initial baudrate!\n");
943 return ret;
944 }
945
946 mutex_lock(&priv->mcp_lock);
947 mcp251x_power_enable(priv->transceiver, 1);
948
949 priv->force_quit = 0;
950 priv->tx_skb = NULL;
951 priv->tx_len = 0;
952
953 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
954 flags | IRQF_ONESHOT, DEVICE_NAME, priv);
955 if (ret) {
956 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
957 mcp251x_power_enable(priv->transceiver, 0);
958 close_candev(net);
959 goto open_unlock;
960 }
961
962 priv->wq = create_freezable_workqueue("mcp251x_wq");
963 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
964 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
965
966 ret = mcp251x_hw_reset(spi);
967 if (ret) {
968 mcp251x_open_clean(net);
969 goto open_unlock;
970 }
971 ret = mcp251x_setup(net, priv, spi);
972 if (ret) {
973 mcp251x_open_clean(net);
974 goto open_unlock;
975 }
976 ret = mcp251x_set_normal_mode(spi);
977 if (ret) {
978 mcp251x_open_clean(net);
979 goto open_unlock;
980 }
981
982 can_led_event(net, CAN_LED_EVENT_OPEN);
983
984 netif_wake_queue(net);
985
986 open_unlock:
987 mutex_unlock(&priv->mcp_lock);
988 return ret;
989 }
990
991 static const struct net_device_ops mcp251x_netdev_ops = {
992 .ndo_open = mcp251x_open,
993 .ndo_stop = mcp251x_stop,
994 .ndo_start_xmit = mcp251x_hard_start_xmit,
995 .ndo_change_mtu = can_change_mtu,
996 };
997
998 static const struct of_device_id mcp251x_of_match[] = {
999 {
1000 .compatible = "microchip,mcp2510",
1001 .data = (void *)CAN_MCP251X_MCP2510,
1002 },
1003 {
1004 .compatible = "microchip,mcp2515",
1005 .data = (void *)CAN_MCP251X_MCP2515,
1006 },
1007 { }
1008 };
1009 MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1010
1011 static const struct spi_device_id mcp251x_id_table[] = {
1012 {
1013 .name = "mcp2510",
1014 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1015 },
1016 {
1017 .name = "mcp2515",
1018 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1019 },
1020 { }
1021 };
1022 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1023
1024 static int mcp251x_can_probe(struct spi_device *spi)
1025 {
1026 const struct of_device_id *of_id = of_match_device(mcp251x_of_match,
1027 &spi->dev);
1028 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
1029 struct net_device *net;
1030 struct mcp251x_priv *priv;
1031 struct clk *clk;
1032 int freq, ret;
1033
1034 clk = devm_clk_get(&spi->dev, NULL);
1035 if (IS_ERR(clk)) {
1036 if (pdata)
1037 freq = pdata->oscillator_frequency;
1038 else
1039 return PTR_ERR(clk);
1040 } else {
1041 freq = clk_get_rate(clk);
1042 }
1043
1044 /* Sanity check */
1045 if (freq < 1000000 || freq > 25000000)
1046 return -ERANGE;
1047
1048 /* Allocate can/net device */
1049 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1050 if (!net)
1051 return -ENOMEM;
1052
1053 if (!IS_ERR(clk)) {
1054 ret = clk_prepare_enable(clk);
1055 if (ret)
1056 goto out_free;
1057 }
1058
1059 net->netdev_ops = &mcp251x_netdev_ops;
1060 net->flags |= IFF_ECHO;
1061
1062 priv = netdev_priv(net);
1063 priv->can.bittiming_const = &mcp251x_bittiming_const;
1064 priv->can.do_set_mode = mcp251x_do_set_mode;
1065 priv->can.clock.freq = freq / 2;
1066 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1067 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1068 if (of_id)
1069 priv->model = (enum mcp251x_model)of_id->data;
1070 else
1071 priv->model = spi_get_device_id(spi)->driver_data;
1072 priv->net = net;
1073 priv->clk = clk;
1074
1075 spi_set_drvdata(spi, priv);
1076
1077 /* Configure the SPI bus */
1078 spi->bits_per_word = 8;
1079 if (mcp251x_is_2510(spi))
1080 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1081 else
1082 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1083 ret = spi_setup(spi);
1084 if (ret)
1085 goto out_clk;
1086
1087 priv->power = devm_regulator_get(&spi->dev, "vdd");
1088 priv->transceiver = devm_regulator_get(&spi->dev, "xceiver");
1089 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1090 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1091 ret = -EPROBE_DEFER;
1092 goto out_clk;
1093 }
1094
1095 ret = mcp251x_power_enable(priv->power, 1);
1096 if (ret)
1097 goto out_clk;
1098
1099 priv->spi = spi;
1100 mutex_init(&priv->mcp_lock);
1101
1102 /* If requested, allocate DMA buffers */
1103 if (mcp251x_enable_dma) {
1104 spi->dev.coherent_dma_mask = ~0;
1105
1106 /*
1107 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1108 * that much and share it between Tx and Rx DMA buffers.
1109 */
1110 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev,
1111 PAGE_SIZE,
1112 &priv->spi_tx_dma,
1113 GFP_DMA);
1114
1115 if (priv->spi_tx_buf) {
1116 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1117 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1118 (PAGE_SIZE / 2));
1119 } else {
1120 /* Fall back to non-DMA */
1121 mcp251x_enable_dma = 0;
1122 }
1123 }
1124
1125 /* Allocate non-DMA buffers */
1126 if (!mcp251x_enable_dma) {
1127 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1128 GFP_KERNEL);
1129 if (!priv->spi_tx_buf) {
1130 ret = -ENOMEM;
1131 goto error_probe;
1132 }
1133 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1134 GFP_KERNEL);
1135 if (!priv->spi_rx_buf) {
1136 ret = -ENOMEM;
1137 goto error_probe;
1138 }
1139 }
1140
1141 SET_NETDEV_DEV(net, &spi->dev);
1142
1143 /* Here is OK to not lock the MCP, no one knows about it yet */
1144 ret = mcp251x_hw_probe(spi);
1145 if (ret)
1146 goto error_probe;
1147
1148 mcp251x_hw_sleep(spi);
1149
1150 ret = register_candev(net);
1151 if (ret)
1152 goto error_probe;
1153
1154 devm_can_led_init(net);
1155
1156 return 0;
1157
1158 error_probe:
1159 mcp251x_power_enable(priv->power, 0);
1160
1161 out_clk:
1162 if (!IS_ERR(clk))
1163 clk_disable_unprepare(clk);
1164
1165 out_free:
1166 free_candev(net);
1167
1168 return ret;
1169 }
1170
1171 static int mcp251x_can_remove(struct spi_device *spi)
1172 {
1173 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1174 struct net_device *net = priv->net;
1175
1176 unregister_candev(net);
1177
1178 mcp251x_power_enable(priv->power, 0);
1179
1180 if (!IS_ERR(priv->clk))
1181 clk_disable_unprepare(priv->clk);
1182
1183 free_candev(net);
1184
1185 return 0;
1186 }
1187
1188 static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1189 {
1190 struct spi_device *spi = to_spi_device(dev);
1191 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1192 struct net_device *net = priv->net;
1193
1194 priv->force_quit = 1;
1195 disable_irq(spi->irq);
1196 /*
1197 * Note: at this point neither IST nor workqueues are running.
1198 * open/stop cannot be called anyway so locking is not needed
1199 */
1200 if (netif_running(net)) {
1201 netif_device_detach(net);
1202
1203 mcp251x_hw_sleep(spi);
1204 mcp251x_power_enable(priv->transceiver, 0);
1205 priv->after_suspend = AFTER_SUSPEND_UP;
1206 } else {
1207 priv->after_suspend = AFTER_SUSPEND_DOWN;
1208 }
1209
1210 if (!IS_ERR_OR_NULL(priv->power)) {
1211 regulator_disable(priv->power);
1212 priv->after_suspend |= AFTER_SUSPEND_POWER;
1213 }
1214
1215 return 0;
1216 }
1217
1218 static int __maybe_unused mcp251x_can_resume(struct device *dev)
1219 {
1220 struct spi_device *spi = to_spi_device(dev);
1221 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1222
1223 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1224 mcp251x_power_enable(priv->power, 1);
1225 queue_work(priv->wq, &priv->restart_work);
1226 } else {
1227 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1228 mcp251x_power_enable(priv->transceiver, 1);
1229 queue_work(priv->wq, &priv->restart_work);
1230 } else {
1231 priv->after_suspend = 0;
1232 }
1233 }
1234 priv->force_quit = 0;
1235 enable_irq(spi->irq);
1236 return 0;
1237 }
1238
1239 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1240 mcp251x_can_resume);
1241
1242 static struct spi_driver mcp251x_can_driver = {
1243 .driver = {
1244 .name = DEVICE_NAME,
1245 .owner = THIS_MODULE,
1246 .of_match_table = mcp251x_of_match,
1247 .pm = &mcp251x_can_pm_ops,
1248 },
1249 .id_table = mcp251x_id_table,
1250 .probe = mcp251x_can_probe,
1251 .remove = mcp251x_can_remove,
1252 };
1253 module_spi_driver(mcp251x_can_driver);
1254
1255 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1256 "Christian Pellegrin <chripell@evolware.org>");
1257 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1258 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support