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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_sriov_common.c
blob1659c804f1d5f4fc530f7d9b2ac11c7f9f023c6b
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic_sriov.h"
9 #include "qlcnic.h"
10 #include "qlcnic_83xx_hw.h"
11 #include <linux/types.h>
12
13 #define QLC_BC_COMMAND 0
14 #define QLC_BC_RESPONSE 1
15
16 #define QLC_MBOX_RESP_TIMEOUT (10 * HZ)
17 #define QLC_MBOX_CH_FREE_TIMEOUT (10 * HZ)
18
19 #define QLC_BC_MSG 0
20 #define QLC_BC_CFREE 1
21 #define QLC_BC_FLR 2
22 #define QLC_BC_HDR_SZ 16
23 #define QLC_BC_PAYLOAD_SZ (1024 - QLC_BC_HDR_SZ)
24
25 #define QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF 2048
26 #define QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF 512
27
28 #define QLC_83XX_VF_RESET_FAIL_THRESH 8
29 #define QLC_BC_CMD_MAX_RETRY_CNT 5
30
31 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *);
32 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *, u32);
33 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *);
34 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *);
35 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *);
36 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *,
37 struct qlcnic_cmd_args *);
38 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *, u8);
39 static void qlcnic_sriov_process_bc_cmd(struct work_struct *);
40 static int qlcnic_sriov_vf_shutdown(struct pci_dev *);
41 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *);
42 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *,
43 struct qlcnic_cmd_args *);
44
45 static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = {
46 .read_crb = qlcnic_83xx_read_crb,
47 .write_crb = qlcnic_83xx_write_crb,
48 .read_reg = qlcnic_83xx_rd_reg_indirect,
49 .write_reg = qlcnic_83xx_wrt_reg_indirect,
50 .get_mac_address = qlcnic_83xx_get_mac_address,
51 .setup_intr = qlcnic_83xx_setup_intr,
52 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
53 .mbx_cmd = qlcnic_sriov_issue_cmd,
54 .get_func_no = qlcnic_83xx_get_func_no,
55 .api_lock = qlcnic_83xx_cam_lock,
56 .api_unlock = qlcnic_83xx_cam_unlock,
57 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
58 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
59 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
60 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
61 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
62 .setup_link_event = qlcnic_83xx_setup_link_event,
63 .get_nic_info = qlcnic_83xx_get_nic_info,
64 .get_pci_info = qlcnic_83xx_get_pci_info,
65 .set_nic_info = qlcnic_83xx_set_nic_info,
66 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
67 .napi_enable = qlcnic_83xx_napi_enable,
68 .napi_disable = qlcnic_83xx_napi_disable,
69 .config_intr_coal = qlcnic_83xx_config_intr_coal,
70 .config_rss = qlcnic_83xx_config_rss,
71 .config_hw_lro = qlcnic_83xx_config_hw_lro,
72 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
73 .change_l2_filter = qlcnic_83xx_change_l2_filter,
74 .get_board_info = qlcnic_83xx_get_port_info,
75 .free_mac_list = qlcnic_sriov_vf_free_mac_list,
76 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
77 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
78 };
79
80 static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {
81 .config_bridged_mode = qlcnic_config_bridged_mode,
82 .config_led = qlcnic_config_led,
83 .cancel_idc_work = qlcnic_sriov_vf_cancel_fw_work,
84 .napi_add = qlcnic_83xx_napi_add,
85 .napi_del = qlcnic_83xx_napi_del,
86 .shutdown = qlcnic_sriov_vf_shutdown,
87 .resume = qlcnic_sriov_vf_resume,
88 .config_ipaddr = qlcnic_83xx_config_ipaddr,
89 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
90 };
91
92 static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl[] = {
93 {QLCNIC_BC_CMD_CHANNEL_INIT, 2, 2},
94 {QLCNIC_BC_CMD_CHANNEL_TERM, 2, 2},
95 {QLCNIC_BC_CMD_GET_ACL, 3, 14},
96 {QLCNIC_BC_CMD_CFG_GUEST_VLAN, 2, 2},
97 };
98
99 static inline bool qlcnic_sriov_bc_msg_check(u32 val)
100 {
101 return (val & (1 << QLC_BC_MSG)) ? true : false;
102 }
103
104 static inline bool qlcnic_sriov_channel_free_check(u32 val)
105 {
106 return (val & (1 << QLC_BC_CFREE)) ? true : false;
107 }
108
109 static inline bool qlcnic_sriov_flr_check(u32 val)
110 {
111 return (val & (1 << QLC_BC_FLR)) ? true : false;
112 }
113
114 static inline u8 qlcnic_sriov_target_func_id(u32 val)
115 {
116 return (val >> 4) & 0xff;
117 }
118
119 static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter *adapter, int vf_id)
120 {
121 struct pci_dev *dev = adapter->pdev;
122 int pos;
123 u16 stride, offset;
124
125 if (qlcnic_sriov_vf_check(adapter))
126 return 0;
127
128 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
129 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
130 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
131
132 return (dev->devfn + offset + stride * vf_id) & 0xff;
133 }
134
135 int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs)
136 {
137 struct qlcnic_sriov *sriov;
138 struct qlcnic_back_channel *bc;
139 struct workqueue_struct *wq;
140 struct qlcnic_vport *vp;
141 struct qlcnic_vf_info *vf;
142 int err, i;
143
144 if (!qlcnic_sriov_enable_check(adapter))
145 return -EIO;
146
147 sriov = kzalloc(sizeof(struct qlcnic_sriov), GFP_KERNEL);
148 if (!sriov)
149 return -ENOMEM;
150
151 adapter->ahw->sriov = sriov;
152 sriov->num_vfs = num_vfs;
153 bc = &sriov->bc;
154 sriov->vf_info = kzalloc(sizeof(struct qlcnic_vf_info) *
155 num_vfs, GFP_KERNEL);
156 if (!sriov->vf_info) {
157 err = -ENOMEM;
158 goto qlcnic_free_sriov;
159 }
160
161 wq = create_singlethread_workqueue("bc-trans");
162 if (wq == NULL) {
163 err = -ENOMEM;
164 dev_err(&adapter->pdev->dev,
165 "Cannot create bc-trans workqueue\n");
166 goto qlcnic_free_vf_info;
167 }
168
169 bc->bc_trans_wq = wq;
170
171 wq = create_singlethread_workqueue("async");
172 if (wq == NULL) {
173 err = -ENOMEM;
174 dev_err(&adapter->pdev->dev, "Cannot create async workqueue\n");
175 goto qlcnic_destroy_trans_wq;
176 }
177
178 bc->bc_async_wq = wq;
179 INIT_LIST_HEAD(&bc->async_list);
180
181 for (i = 0; i < num_vfs; i++) {
182 vf = &sriov->vf_info[i];
183 vf->adapter = adapter;
184 vf->pci_func = qlcnic_sriov_virtid_fn(adapter, i);
185 mutex_init(&vf->send_cmd_lock);
186 spin_lock_init(&vf->vlan_list_lock);
187 INIT_LIST_HEAD(&vf->rcv_act.wait_list);
188 INIT_LIST_HEAD(&vf->rcv_pend.wait_list);
189 spin_lock_init(&vf->rcv_act.lock);
190 spin_lock_init(&vf->rcv_pend.lock);
191 init_completion(&vf->ch_free_cmpl);
192
193 INIT_WORK(&vf->trans_work, qlcnic_sriov_process_bc_cmd);
194
195 if (qlcnic_sriov_pf_check(adapter)) {
196 vp = kzalloc(sizeof(struct qlcnic_vport), GFP_KERNEL);
197 if (!vp) {
198 err = -ENOMEM;
199 goto qlcnic_destroy_async_wq;
200 }
201 sriov->vf_info[i].vp = vp;
202 vp->vlan_mode = QLC_GUEST_VLAN_MODE;
203 vp->max_tx_bw = MAX_BW;
204 vp->min_tx_bw = MIN_BW;
205 vp->spoofchk = false;
206 random_ether_addr(vp->mac);
207 dev_info(&adapter->pdev->dev,
208 "MAC Address %pM is configured for VF %d\n",
209 vp->mac, i);
210 }
211 }
212
213 return 0;
214
215 qlcnic_destroy_async_wq:
216 destroy_workqueue(bc->bc_async_wq);
217
218 qlcnic_destroy_trans_wq:
219 destroy_workqueue(bc->bc_trans_wq);
220
221 qlcnic_free_vf_info:
222 kfree(sriov->vf_info);
223
224 qlcnic_free_sriov:
225 kfree(adapter->ahw->sriov);
226 return err;
227 }
228
229 void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list *t_list)
230 {
231 struct qlcnic_bc_trans *trans;
232 struct qlcnic_cmd_args cmd;
233 unsigned long flags;
234
235 spin_lock_irqsave(&t_list->lock, flags);
236
237 while (!list_empty(&t_list->wait_list)) {
238 trans = list_first_entry(&t_list->wait_list,
239 struct qlcnic_bc_trans, list);
240 list_del(&trans->list);
241 t_list->count--;
242 cmd.req.arg = (u32 *)trans->req_pay;
243 cmd.rsp.arg = (u32 *)trans->rsp_pay;
244 qlcnic_free_mbx_args(&cmd);
245 qlcnic_sriov_cleanup_transaction(trans);
246 }
247
248 spin_unlock_irqrestore(&t_list->lock, flags);
249 }
250
251 void __qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
252 {
253 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
254 struct qlcnic_back_channel *bc = &sriov->bc;
255 struct qlcnic_vf_info *vf;
256 int i;
257
258 if (!qlcnic_sriov_enable_check(adapter))
259 return;
260
261 qlcnic_sriov_cleanup_async_list(bc);
262 destroy_workqueue(bc->bc_async_wq);
263
264 for (i = 0; i < sriov->num_vfs; i++) {
265 vf = &sriov->vf_info[i];
266 qlcnic_sriov_cleanup_list(&vf->rcv_pend);
267 cancel_work_sync(&vf->trans_work);
268 qlcnic_sriov_cleanup_list(&vf->rcv_act);
269 }
270
271 destroy_workqueue(bc->bc_trans_wq);
272
273 for (i = 0; i < sriov->num_vfs; i++)
274 kfree(sriov->vf_info[i].vp);
275
276 kfree(sriov->vf_info);
277 kfree(adapter->ahw->sriov);
278 }
279
280 static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter *adapter)
281 {
282 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
283 qlcnic_sriov_cfg_bc_intr(adapter, 0);
284 __qlcnic_sriov_cleanup(adapter);
285 }
286
287 void qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
288 {
289 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
290 return;
291
292 qlcnic_sriov_free_vlans(adapter);
293
294 if (qlcnic_sriov_pf_check(adapter))
295 qlcnic_sriov_pf_cleanup(adapter);
296
297 if (qlcnic_sriov_vf_check(adapter))
298 qlcnic_sriov_vf_cleanup(adapter);
299 }
300
301 static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter *adapter, u32 *hdr,
302 u32 *pay, u8 pci_func, u8 size)
303 {
304 struct qlcnic_hardware_context *ahw = adapter->ahw;
305 struct qlcnic_mailbox *mbx = ahw->mailbox;
306 struct qlcnic_cmd_args cmd;
307 unsigned long timeout;
308 int err;
309
310 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
311 cmd.hdr = hdr;
312 cmd.pay = pay;
313 cmd.pay_size = size;
314 cmd.func_num = pci_func;
315 cmd.op_type = QLC_83XX_MBX_POST_BC_OP;
316 cmd.cmd_op = ((struct qlcnic_bc_hdr *)hdr)->cmd_op;
317
318 err = mbx->ops->enqueue_cmd(adapter, &cmd, &timeout);
319 if (err) {
320 dev_err(&adapter->pdev->dev,
321 "%s: Mailbox not available, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
322 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
323 ahw->op_mode);
324 return err;
325 }
326
327 if (!wait_for_completion_timeout(&cmd.completion, timeout)) {
328 dev_err(&adapter->pdev->dev,
329 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
330 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
331 ahw->op_mode);
332 flush_workqueue(mbx->work_q);
333 }
334
335 return cmd.rsp_opcode;
336 }
337
338 static void qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter *adapter)
339 {
340 adapter->num_rxd = QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF;
341 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
342 adapter->num_jumbo_rxd = QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF;
343 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
344 adapter->num_txd = MAX_CMD_DESCRIPTORS;
345 adapter->max_rds_rings = MAX_RDS_RINGS;
346 }
347
348 int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter *adapter,
349 struct qlcnic_info *npar_info, u16 vport_id)
350 {
351 struct device *dev = &adapter->pdev->dev;
352 struct qlcnic_cmd_args cmd;
353 int err;
354 u32 status;
355
356 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
357 if (err)
358 return err;
359
360 cmd.req.arg[1] = vport_id << 16 | 0x1;
361 err = qlcnic_issue_cmd(adapter, &cmd);
362 if (err) {
363 dev_err(&adapter->pdev->dev,
364 "Failed to get vport info, err=%d\n", err);
365 qlcnic_free_mbx_args(&cmd);
366 return err;
367 }
368
369 status = cmd.rsp.arg[2] & 0xffff;
370 if (status & BIT_0)
371 npar_info->min_tx_bw = MSW(cmd.rsp.arg[2]);
372 if (status & BIT_1)
373 npar_info->max_tx_bw = LSW(cmd.rsp.arg[3]);
374 if (status & BIT_2)
375 npar_info->max_tx_ques = MSW(cmd.rsp.arg[3]);
376 if (status & BIT_3)
377 npar_info->max_tx_mac_filters = LSW(cmd.rsp.arg[4]);
378 if (status & BIT_4)
379 npar_info->max_rx_mcast_mac_filters = MSW(cmd.rsp.arg[4]);
380 if (status & BIT_5)
381 npar_info->max_rx_ucast_mac_filters = LSW(cmd.rsp.arg[5]);
382 if (status & BIT_6)
383 npar_info->max_rx_ip_addr = MSW(cmd.rsp.arg[5]);
384 if (status & BIT_7)
385 npar_info->max_rx_lro_flow = LSW(cmd.rsp.arg[6]);
386 if (status & BIT_8)
387 npar_info->max_rx_status_rings = MSW(cmd.rsp.arg[6]);
388 if (status & BIT_9)
389 npar_info->max_rx_buf_rings = LSW(cmd.rsp.arg[7]);
390
391 npar_info->max_rx_ques = MSW(cmd.rsp.arg[7]);
392 npar_info->max_tx_vlan_keys = LSW(cmd.rsp.arg[8]);
393 npar_info->max_local_ipv6_addrs = MSW(cmd.rsp.arg[8]);
394 npar_info->max_remote_ipv6_addrs = LSW(cmd.rsp.arg[9]);
395
396 dev_info(dev, "\n\tmin_tx_bw: %d, max_tx_bw: %d max_tx_ques: %d,\n"
397 "\tmax_tx_mac_filters: %d max_rx_mcast_mac_filters: %d,\n"
398 "\tmax_rx_ucast_mac_filters: 0x%x, max_rx_ip_addr: %d,\n"
399 "\tmax_rx_lro_flow: %d max_rx_status_rings: %d,\n"
400 "\tmax_rx_buf_rings: %d, max_rx_ques: %d, max_tx_vlan_keys %d\n"
401 "\tlocal_ipv6_addr: %d, remote_ipv6_addr: %d\n",
402 npar_info->min_tx_bw, npar_info->max_tx_bw,
403 npar_info->max_tx_ques, npar_info->max_tx_mac_filters,
404 npar_info->max_rx_mcast_mac_filters,
405 npar_info->max_rx_ucast_mac_filters, npar_info->max_rx_ip_addr,
406 npar_info->max_rx_lro_flow, npar_info->max_rx_status_rings,
407 npar_info->max_rx_buf_rings, npar_info->max_rx_ques,
408 npar_info->max_tx_vlan_keys, npar_info->max_local_ipv6_addrs,
409 npar_info->max_remote_ipv6_addrs);
410
411 qlcnic_free_mbx_args(&cmd);
412 return err;
413 }
414
415 static int qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter *adapter,
416 struct qlcnic_cmd_args *cmd)
417 {
418 adapter->rx_pvid = MSW(cmd->rsp.arg[1]) & 0xffff;
419 adapter->flags &= ~QLCNIC_TAGGING_ENABLED;
420 return 0;
421 }
422
423 static int qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter *adapter,
424 struct qlcnic_cmd_args *cmd)
425 {
426 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
427 int i, num_vlans;
428 u16 *vlans;
429
430 if (sriov->allowed_vlans)
431 return 0;
432
433 sriov->any_vlan = cmd->rsp.arg[2] & 0xf;
434 sriov->num_allowed_vlans = cmd->rsp.arg[2] >> 16;
435 dev_info(&adapter->pdev->dev, "Number of allowed Guest VLANs = %d\n",
436 sriov->num_allowed_vlans);
437
438 qlcnic_sriov_alloc_vlans(adapter);
439
440 if (!sriov->any_vlan)
441 return 0;
442
443 num_vlans = sriov->num_allowed_vlans;
444 sriov->allowed_vlans = kzalloc(sizeof(u16) * num_vlans, GFP_KERNEL);
445 if (!sriov->allowed_vlans)
446 return -ENOMEM;
447
448 vlans = (u16 *)&cmd->rsp.arg[3];
449 for (i = 0; i < num_vlans; i++)
450 sriov->allowed_vlans[i] = vlans[i];
451
452 return 0;
453 }
454
455 static int qlcnic_sriov_get_vf_acl(struct qlcnic_adapter *adapter)
456 {
457 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
458 struct qlcnic_cmd_args cmd;
459 int ret = 0;
460
461 memset(&cmd, 0, sizeof(cmd));
462 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd, QLCNIC_BC_CMD_GET_ACL);
463 if (ret)
464 return ret;
465
466 ret = qlcnic_issue_cmd(adapter, &cmd);
467 if (ret) {
468 dev_err(&adapter->pdev->dev, "Failed to get ACL, err=%d\n",
469 ret);
470 } else {
471 sriov->vlan_mode = cmd.rsp.arg[1] & 0x3;
472 switch (sriov->vlan_mode) {
473 case QLC_GUEST_VLAN_MODE:
474 ret = qlcnic_sriov_set_guest_vlan_mode(adapter, &cmd);
475 break;
476 case QLC_PVID_MODE:
477 ret = qlcnic_sriov_set_pvid_mode(adapter, &cmd);
478 break;
479 }
480 }
481
482 qlcnic_free_mbx_args(&cmd);
483 return ret;
484 }
485
486 static int qlcnic_sriov_vf_init_driver(struct qlcnic_adapter *adapter)
487 {
488 struct qlcnic_hardware_context *ahw = adapter->ahw;
489 struct qlcnic_info nic_info;
490 int err;
491
492 err = qlcnic_sriov_get_vf_vport_info(adapter, &nic_info, 0);
493 if (err)
494 return err;
495
496 ahw->max_mc_count = nic_info.max_rx_mcast_mac_filters;
497
498 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
499 if (err)
500 return -EIO;
501
502 if (qlcnic_83xx_get_port_info(adapter))
503 return -EIO;
504
505 qlcnic_sriov_vf_cfg_buff_desc(adapter);
506 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
507 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
508 adapter->ahw->fw_hal_version);
509
510 ahw->physical_port = (u8) nic_info.phys_port;
511 ahw->switch_mode = nic_info.switch_mode;
512 ahw->max_mtu = nic_info.max_mtu;
513 ahw->op_mode = nic_info.op_mode;
514 ahw->capabilities = nic_info.capabilities;
515 return 0;
516 }
517
518 static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter,
519 int pci_using_dac)
520 {
521 int err;
522
523 adapter->flags |= QLCNIC_VLAN_FILTERING;
524 adapter->ahw->total_nic_func = 1;
525 INIT_LIST_HEAD(&adapter->vf_mc_list);
526 if (!qlcnic_use_msi_x && !!qlcnic_use_msi)
527 dev_warn(&adapter->pdev->dev,
528 "Device does not support MSI interrupts\n");
529
530 /* compute and set default and max tx/sds rings */
531 qlcnic_set_tx_ring_count(adapter, QLCNIC_SINGLE_RING);
532 qlcnic_set_sds_ring_count(adapter, QLCNIC_SINGLE_RING);
533
534 err = qlcnic_setup_intr(adapter);
535 if (err) {
536 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
537 goto err_out_disable_msi;
538 }
539
540 err = qlcnic_83xx_setup_mbx_intr(adapter);
541 if (err)
542 goto err_out_disable_msi;
543
544 err = qlcnic_sriov_init(adapter, 1);
545 if (err)
546 goto err_out_disable_mbx_intr;
547
548 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
549 if (err)
550 goto err_out_cleanup_sriov;
551
552 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
553 if (err)
554 goto err_out_disable_bc_intr;
555
556 err = qlcnic_sriov_vf_init_driver(adapter);
557 if (err)
558 goto err_out_send_channel_term;
559
560 err = qlcnic_sriov_get_vf_acl(adapter);
561 if (err)
562 goto err_out_send_channel_term;
563
564 err = qlcnic_setup_netdev(adapter, adapter->netdev, pci_using_dac);
565 if (err)
566 goto err_out_send_channel_term;
567
568 pci_set_drvdata(adapter->pdev, adapter);
569 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
570 adapter->netdev->name);
571
572 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
573 adapter->ahw->idc.delay);
574 return 0;
575
576 err_out_send_channel_term:
577 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
578
579 err_out_disable_bc_intr:
580 qlcnic_sriov_cfg_bc_intr(adapter, 0);
581
582 err_out_cleanup_sriov:
583 __qlcnic_sriov_cleanup(adapter);
584
585 err_out_disable_mbx_intr:
586 qlcnic_83xx_free_mbx_intr(adapter);
587
588 err_out_disable_msi:
589 qlcnic_teardown_intr(adapter);
590 return err;
591 }
592
593 static int qlcnic_sriov_check_dev_ready(struct qlcnic_adapter *adapter)
594 {
595 u32 state;
596
597 do {
598 msleep(20);
599 if (++adapter->fw_fail_cnt > QLC_BC_CMD_MAX_RETRY_CNT)
600 return -EIO;
601 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
602 } while (state != QLC_83XX_IDC_DEV_READY);
603
604 return 0;
605 }
606
607 int qlcnic_sriov_vf_init(struct qlcnic_adapter *adapter, int pci_using_dac)
608 {
609 struct qlcnic_hardware_context *ahw = adapter->ahw;
610 int err;
611
612 set_bit(QLC_83XX_MODULE_LOADED, &ahw->idc.status);
613 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
614 ahw->reset_context = 0;
615 adapter->fw_fail_cnt = 0;
616 ahw->msix_supported = 1;
617 adapter->need_fw_reset = 0;
618 adapter->flags |= QLCNIC_TX_INTR_SHARED;
619
620 err = qlcnic_sriov_check_dev_ready(adapter);
621 if (err)
622 return err;
623
624 err = qlcnic_sriov_setup_vf(adapter, pci_using_dac);
625 if (err)
626 return err;
627
628 if (qlcnic_read_mac_addr(adapter))
629 dev_warn(&adapter->pdev->dev, "failed to read mac addr\n");
630
631 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
632
633 clear_bit(__QLCNIC_RESETTING, &adapter->state);
634 return 0;
635 }
636
637 void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter *adapter)
638 {
639 struct qlcnic_hardware_context *ahw = adapter->ahw;
640
641 ahw->op_mode = QLCNIC_SRIOV_VF_FUNC;
642 dev_info(&adapter->pdev->dev,
643 "HAL Version: %d Non Privileged SRIOV function\n",
644 ahw->fw_hal_version);
645 adapter->nic_ops = &qlcnic_sriov_vf_ops;
646 set_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state);
647 return;
648 }
649
650 void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *ahw)
651 {
652 ahw->hw_ops = &qlcnic_sriov_vf_hw_ops;
653 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
654 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
655 }
656
657 static u32 qlcnic_sriov_get_bc_paysize(u32 real_pay_size, u8 curr_frag)
658 {
659 u32 pay_size;
660
661 pay_size = real_pay_size / ((curr_frag + 1) * QLC_BC_PAYLOAD_SZ);
662
663 if (pay_size)
664 pay_size = QLC_BC_PAYLOAD_SZ;
665 else
666 pay_size = real_pay_size % QLC_BC_PAYLOAD_SZ;
667
668 return pay_size;
669 }
670
671 int qlcnic_sriov_func_to_index(struct qlcnic_adapter *adapter, u8 pci_func)
672 {
673 struct qlcnic_vf_info *vf_info = adapter->ahw->sriov->vf_info;
674 u8 i;
675
676 if (qlcnic_sriov_vf_check(adapter))
677 return 0;
678
679 for (i = 0; i < adapter->ahw->sriov->num_vfs; i++) {
680 if (vf_info[i].pci_func == pci_func)
681 return i;
682 }
683
684 return -EINVAL;
685 }
686
687 static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans **trans)
688 {
689 *trans = kzalloc(sizeof(struct qlcnic_bc_trans), GFP_ATOMIC);
690 if (!*trans)
691 return -ENOMEM;
692
693 init_completion(&(*trans)->resp_cmpl);
694 return 0;
695 }
696
697 static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr **hdr,
698 u32 size)
699 {
700 *hdr = kzalloc(sizeof(struct qlcnic_bc_hdr) * size, GFP_ATOMIC);
701 if (!*hdr)
702 return -ENOMEM;
703
704 return 0;
705 }
706
707 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *mbx, u32 type)
708 {
709 const struct qlcnic_mailbox_metadata *mbx_tbl;
710 int i, size;
711
712 mbx_tbl = qlcnic_sriov_bc_mbx_tbl;
713 size = ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl);
714
715 for (i = 0; i < size; i++) {
716 if (type == mbx_tbl[i].cmd) {
717 mbx->op_type = QLC_BC_CMD;
718 mbx->req.num = mbx_tbl[i].in_args;
719 mbx->rsp.num = mbx_tbl[i].out_args;
720 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
721 GFP_ATOMIC);
722 if (!mbx->req.arg)
723 return -ENOMEM;
724 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
725 GFP_ATOMIC);
726 if (!mbx->rsp.arg) {
727 kfree(mbx->req.arg);
728 mbx->req.arg = NULL;
729 return -ENOMEM;
730 }
731 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
732 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
733 mbx->req.arg[0] = (type | (mbx->req.num << 16) |
734 (3 << 29));
735 mbx->rsp.arg[0] = (type & 0xffff) | mbx->rsp.num << 16;
736 return 0;
737 }
738 }
739 return -EINVAL;
740 }
741
742 static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans *trans,
743 struct qlcnic_cmd_args *cmd,
744 u16 seq, u8 msg_type)
745 {
746 struct qlcnic_bc_hdr *hdr;
747 int i;
748 u32 num_regs, bc_pay_sz;
749 u16 remainder;
750 u8 cmd_op, num_frags, t_num_frags;
751
752 bc_pay_sz = QLC_BC_PAYLOAD_SZ;
753 if (msg_type == QLC_BC_COMMAND) {
754 trans->req_pay = (struct qlcnic_bc_payload *)cmd->req.arg;
755 trans->rsp_pay = (struct qlcnic_bc_payload *)cmd->rsp.arg;
756 num_regs = cmd->req.num;
757 trans->req_pay_size = (num_regs * 4);
758 num_regs = cmd->rsp.num;
759 trans->rsp_pay_size = (num_regs * 4);
760 cmd_op = cmd->req.arg[0] & 0xff;
761 remainder = (trans->req_pay_size) % (bc_pay_sz);
762 num_frags = (trans->req_pay_size) / (bc_pay_sz);
763 if (remainder)
764 num_frags++;
765 t_num_frags = num_frags;
766 if (qlcnic_sriov_alloc_bc_msg(&trans->req_hdr, num_frags))
767 return -ENOMEM;
768 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
769 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
770 if (remainder)
771 num_frags++;
772 if (qlcnic_sriov_alloc_bc_msg(&trans->rsp_hdr, num_frags))
773 return -ENOMEM;
774 num_frags = t_num_frags;
775 hdr = trans->req_hdr;
776 } else {
777 cmd->req.arg = (u32 *)trans->req_pay;
778 cmd->rsp.arg = (u32 *)trans->rsp_pay;
779 cmd_op = cmd->req.arg[0] & 0xff;
780 cmd->cmd_op = cmd_op;
781 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
782 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
783 if (remainder)
784 num_frags++;
785 cmd->req.num = trans->req_pay_size / 4;
786 cmd->rsp.num = trans->rsp_pay_size / 4;
787 hdr = trans->rsp_hdr;
788 cmd->op_type = trans->req_hdr->op_type;
789 }
790
791 trans->trans_id = seq;
792 trans->cmd_id = cmd_op;
793 for (i = 0; i < num_frags; i++) {
794 hdr[i].version = 2;
795 hdr[i].msg_type = msg_type;
796 hdr[i].op_type = cmd->op_type;
797 hdr[i].num_cmds = 1;
798 hdr[i].num_frags = num_frags;
799 hdr[i].frag_num = i + 1;
800 hdr[i].cmd_op = cmd_op;
801 hdr[i].seq_id = seq;
802 }
803 return 0;
804 }
805
806 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *trans)
807 {
808 if (!trans)
809 return;
810 kfree(trans->req_hdr);
811 kfree(trans->rsp_hdr);
812 kfree(trans);
813 }
814
815 static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info *vf,
816 struct qlcnic_bc_trans *trans, u8 type)
817 {
818 struct qlcnic_trans_list *t_list;
819 unsigned long flags;
820 int ret = 0;
821
822 if (type == QLC_BC_RESPONSE) {
823 t_list = &vf->rcv_act;
824 spin_lock_irqsave(&t_list->lock, flags);
825 t_list->count--;
826 list_del(&trans->list);
827 if (t_list->count > 0)
828 ret = 1;
829 spin_unlock_irqrestore(&t_list->lock, flags);
830 }
831 if (type == QLC_BC_COMMAND) {
832 while (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
833 msleep(100);
834 vf->send_cmd = NULL;
835 clear_bit(QLC_BC_VF_SEND, &vf->state);
836 }
837 return ret;
838 }
839
840 static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov *sriov,
841 struct qlcnic_vf_info *vf,
842 work_func_t func)
843 {
844 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
845 vf->adapter->need_fw_reset)
846 return;
847
848 queue_work(sriov->bc.bc_trans_wq, &vf->trans_work);
849 }
850
851 static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans *trans)
852 {
853 struct completion *cmpl = &trans->resp_cmpl;
854
855 if (wait_for_completion_timeout(cmpl, QLC_MBOX_RESP_TIMEOUT))
856 trans->trans_state = QLC_END;
857 else
858 trans->trans_state = QLC_ABORT;
859
860 return;
861 }
862
863 static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans *trans,
864 u8 type)
865 {
866 if (type == QLC_BC_RESPONSE) {
867 trans->curr_rsp_frag++;
868 if (trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
869 trans->trans_state = QLC_INIT;
870 else
871 trans->trans_state = QLC_END;
872 } else {
873 trans->curr_req_frag++;
874 if (trans->curr_req_frag < trans->req_hdr->num_frags)
875 trans->trans_state = QLC_INIT;
876 else
877 trans->trans_state = QLC_WAIT_FOR_RESP;
878 }
879 }
880
881 static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans *trans,
882 u8 type)
883 {
884 struct qlcnic_vf_info *vf = trans->vf;
885 struct completion *cmpl = &vf->ch_free_cmpl;
886
887 if (!wait_for_completion_timeout(cmpl, QLC_MBOX_CH_FREE_TIMEOUT)) {
888 trans->trans_state = QLC_ABORT;
889 return;
890 }
891
892 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
893 qlcnic_sriov_handle_multi_frags(trans, type);
894 }
895
896 static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter *adapter,
897 u32 *hdr, u32 *pay, u32 size)
898 {
899 struct qlcnic_hardware_context *ahw = adapter->ahw;
900 u32 fw_mbx;
901 u8 i, max = 2, hdr_size, j;
902
903 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
904 max = (size / sizeof(u32)) + hdr_size;
905
906 fw_mbx = readl(QLCNIC_MBX_FW(ahw, 0));
907 for (i = 2, j = 0; j < hdr_size; i++, j++)
908 *(hdr++) = readl(QLCNIC_MBX_FW(ahw, i));
909 for (; j < max; i++, j++)
910 *(pay++) = readl(QLCNIC_MBX_FW(ahw, i));
911 }
912
913 static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info *vf)
914 {
915 int ret = -EBUSY;
916 u32 timeout = 10000;
917
918 do {
919 if (!test_and_set_bit(QLC_BC_VF_CHANNEL, &vf->state)) {
920 ret = 0;
921 break;
922 }
923 mdelay(1);
924 } while (--timeout);
925
926 return ret;
927 }
928
929 static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans *trans, u8 type)
930 {
931 struct qlcnic_vf_info *vf = trans->vf;
932 u32 pay_size, hdr_size;
933 u32 *hdr, *pay;
934 int ret;
935 u8 pci_func = trans->func_id;
936
937 if (__qlcnic_sriov_issue_bc_post(vf))
938 return -EBUSY;
939
940 if (type == QLC_BC_COMMAND) {
941 hdr = (u32 *)(trans->req_hdr + trans->curr_req_frag);
942 pay = (u32 *)(trans->req_pay + trans->curr_req_frag);
943 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
944 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
945 trans->curr_req_frag);
946 pay_size = (pay_size / sizeof(u32));
947 } else {
948 hdr = (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag);
949 pay = (u32 *)(trans->rsp_pay + trans->curr_rsp_frag);
950 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
951 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
952 trans->curr_rsp_frag);
953 pay_size = (pay_size / sizeof(u32));
954 }
955
956 ret = qlcnic_sriov_post_bc_msg(vf->adapter, hdr, pay,
957 pci_func, pay_size);
958 return ret;
959 }
960
961 static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans *trans,
962 struct qlcnic_vf_info *vf, u8 type)
963 {
964 bool flag = true;
965 int err = -EIO;
966
967 while (flag) {
968 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
969 vf->adapter->need_fw_reset)
970 trans->trans_state = QLC_ABORT;
971
972 switch (trans->trans_state) {
973 case QLC_INIT:
974 trans->trans_state = QLC_WAIT_FOR_CHANNEL_FREE;
975 if (qlcnic_sriov_issue_bc_post(trans, type))
976 trans->trans_state = QLC_ABORT;
977 break;
978 case QLC_WAIT_FOR_CHANNEL_FREE:
979 qlcnic_sriov_wait_for_channel_free(trans, type);
980 break;
981 case QLC_WAIT_FOR_RESP:
982 qlcnic_sriov_wait_for_resp(trans);
983 break;
984 case QLC_END:
985 err = 0;
986 flag = false;
987 break;
988 case QLC_ABORT:
989 err = -EIO;
990 flag = false;
991 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
992 break;
993 default:
994 err = -EIO;
995 flag = false;
996 }
997 }
998 return err;
999 }
1000
1001 static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter *adapter,
1002 struct qlcnic_bc_trans *trans, int pci_func)
1003 {
1004 struct qlcnic_vf_info *vf;
1005 int err, index = qlcnic_sriov_func_to_index(adapter, pci_func);
1006
1007 if (index < 0)
1008 return -EIO;
1009
1010 vf = &adapter->ahw->sriov->vf_info[index];
1011 trans->vf = vf;
1012 trans->func_id = pci_func;
1013
1014 if (!test_bit(QLC_BC_VF_STATE, &vf->state)) {
1015 if (qlcnic_sriov_pf_check(adapter))
1016 return -EIO;
1017 if (qlcnic_sriov_vf_check(adapter) &&
1018 trans->cmd_id != QLCNIC_BC_CMD_CHANNEL_INIT)
1019 return -EIO;
1020 }
1021
1022 mutex_lock(&vf->send_cmd_lock);
1023 vf->send_cmd = trans;
1024 err = __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_COMMAND);
1025 qlcnic_sriov_clear_trans(vf, trans, QLC_BC_COMMAND);
1026 mutex_unlock(&vf->send_cmd_lock);
1027 return err;
1028 }
1029
1030 static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter *adapter,
1031 struct qlcnic_bc_trans *trans,
1032 struct qlcnic_cmd_args *cmd)
1033 {
1034 #ifdef CONFIG_QLCNIC_SRIOV
1035 if (qlcnic_sriov_pf_check(adapter)) {
1036 qlcnic_sriov_pf_process_bc_cmd(adapter, trans, cmd);
1037 return;
1038 }
1039 #endif
1040 cmd->rsp.arg[0] |= (0x9 << 25);
1041 return;
1042 }
1043
1044 static void qlcnic_sriov_process_bc_cmd(struct work_struct *work)
1045 {
1046 struct qlcnic_vf_info *vf = container_of(work, struct qlcnic_vf_info,
1047 trans_work);
1048 struct qlcnic_bc_trans *trans = NULL;
1049 struct qlcnic_adapter *adapter = vf->adapter;
1050 struct qlcnic_cmd_args cmd;
1051 u8 req;
1052
1053 if (adapter->need_fw_reset)
1054 return;
1055
1056 if (test_bit(QLC_BC_VF_FLR, &vf->state))
1057 return;
1058
1059 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1060 trans = list_first_entry(&vf->rcv_act.wait_list,
1061 struct qlcnic_bc_trans, list);
1062 adapter = vf->adapter;
1063
1064 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, trans->req_hdr->seq_id,
1065 QLC_BC_RESPONSE))
1066 goto cleanup_trans;
1067
1068 __qlcnic_sriov_process_bc_cmd(adapter, trans, &cmd);
1069 trans->trans_state = QLC_INIT;
1070 __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_RESPONSE);
1071
1072 cleanup_trans:
1073 qlcnic_free_mbx_args(&cmd);
1074 req = qlcnic_sriov_clear_trans(vf, trans, QLC_BC_RESPONSE);
1075 qlcnic_sriov_cleanup_transaction(trans);
1076 if (req)
1077 qlcnic_sriov_schedule_bc_cmd(adapter->ahw->sriov, vf,
1078 qlcnic_sriov_process_bc_cmd);
1079 }
1080
1081 static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr *hdr,
1082 struct qlcnic_vf_info *vf)
1083 {
1084 struct qlcnic_bc_trans *trans;
1085 u32 pay_size;
1086
1087 if (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
1088 return;
1089
1090 trans = vf->send_cmd;
1091
1092 if (trans == NULL)
1093 goto clear_send;
1094
1095 if (trans->trans_id != hdr->seq_id)
1096 goto clear_send;
1097
1098 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
1099 trans->curr_rsp_frag);
1100 qlcnic_sriov_pull_bc_msg(vf->adapter,
1101 (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag),
1102 (u32 *)(trans->rsp_pay + trans->curr_rsp_frag),
1103 pay_size);
1104 if (++trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
1105 goto clear_send;
1106
1107 complete(&trans->resp_cmpl);
1108
1109 clear_send:
1110 clear_bit(QLC_BC_VF_SEND, &vf->state);
1111 }
1112
1113 int __qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1114 struct qlcnic_vf_info *vf,
1115 struct qlcnic_bc_trans *trans)
1116 {
1117 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1118
1119 t_list->count++;
1120 list_add_tail(&trans->list, &t_list->wait_list);
1121 if (t_list->count == 1)
1122 qlcnic_sriov_schedule_bc_cmd(sriov, vf,
1123 qlcnic_sriov_process_bc_cmd);
1124 return 0;
1125 }
1126
1127 static int qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1128 struct qlcnic_vf_info *vf,
1129 struct qlcnic_bc_trans *trans)
1130 {
1131 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1132
1133 spin_lock(&t_list->lock);
1134
1135 __qlcnic_sriov_add_act_list(sriov, vf, trans);
1136
1137 spin_unlock(&t_list->lock);
1138 return 0;
1139 }
1140
1141 static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov *sriov,
1142 struct qlcnic_vf_info *vf,
1143 struct qlcnic_bc_hdr *hdr)
1144 {
1145 struct qlcnic_bc_trans *trans = NULL;
1146 struct list_head *node;
1147 u32 pay_size, curr_frag;
1148 u8 found = 0, active = 0;
1149
1150 spin_lock(&vf->rcv_pend.lock);
1151 if (vf->rcv_pend.count > 0) {
1152 list_for_each(node, &vf->rcv_pend.wait_list) {
1153 trans = list_entry(node, struct qlcnic_bc_trans, list);
1154 if (trans->trans_id == hdr->seq_id) {
1155 found = 1;
1156 break;
1157 }
1158 }
1159 }
1160
1161 if (found) {
1162 curr_frag = trans->curr_req_frag;
1163 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1164 curr_frag);
1165 qlcnic_sriov_pull_bc_msg(vf->adapter,
1166 (u32 *)(trans->req_hdr + curr_frag),
1167 (u32 *)(trans->req_pay + curr_frag),
1168 pay_size);
1169 trans->curr_req_frag++;
1170 if (trans->curr_req_frag >= hdr->num_frags) {
1171 vf->rcv_pend.count--;
1172 list_del(&trans->list);
1173 active = 1;
1174 }
1175 }
1176 spin_unlock(&vf->rcv_pend.lock);
1177
1178 if (active)
1179 if (qlcnic_sriov_add_act_list(sriov, vf, trans))
1180 qlcnic_sriov_cleanup_transaction(trans);
1181
1182 return;
1183 }
1184
1185 static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov *sriov,
1186 struct qlcnic_bc_hdr *hdr,
1187 struct qlcnic_vf_info *vf)
1188 {
1189 struct qlcnic_bc_trans *trans;
1190 struct qlcnic_adapter *adapter = vf->adapter;
1191 struct qlcnic_cmd_args cmd;
1192 u32 pay_size;
1193 int err;
1194 u8 cmd_op;
1195
1196 if (adapter->need_fw_reset)
1197 return;
1198
1199 if (!test_bit(QLC_BC_VF_STATE, &vf->state) &&
1200 hdr->op_type != QLC_BC_CMD &&
1201 hdr->cmd_op != QLCNIC_BC_CMD_CHANNEL_INIT)
1202 return;
1203
1204 if (hdr->frag_num > 1) {
1205 qlcnic_sriov_handle_pending_trans(sriov, vf, hdr);
1206 return;
1207 }
1208
1209 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1210 cmd_op = hdr->cmd_op;
1211 if (qlcnic_sriov_alloc_bc_trans(&trans))
1212 return;
1213
1214 if (hdr->op_type == QLC_BC_CMD)
1215 err = qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op);
1216 else
1217 err = qlcnic_alloc_mbx_args(&cmd, adapter, cmd_op);
1218
1219 if (err) {
1220 qlcnic_sriov_cleanup_transaction(trans);
1221 return;
1222 }
1223
1224 cmd.op_type = hdr->op_type;
1225 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, hdr->seq_id,
1226 QLC_BC_COMMAND)) {
1227 qlcnic_free_mbx_args(&cmd);
1228 qlcnic_sriov_cleanup_transaction(trans);
1229 return;
1230 }
1231
1232 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1233 trans->curr_req_frag);
1234 qlcnic_sriov_pull_bc_msg(vf->adapter,
1235 (u32 *)(trans->req_hdr + trans->curr_req_frag),
1236 (u32 *)(trans->req_pay + trans->curr_req_frag),
1237 pay_size);
1238 trans->func_id = vf->pci_func;
1239 trans->vf = vf;
1240 trans->trans_id = hdr->seq_id;
1241 trans->curr_req_frag++;
1242
1243 if (qlcnic_sriov_soft_flr_check(adapter, trans, vf))
1244 return;
1245
1246 if (trans->curr_req_frag == trans->req_hdr->num_frags) {
1247 if (qlcnic_sriov_add_act_list(sriov, vf, trans)) {
1248 qlcnic_free_mbx_args(&cmd);
1249 qlcnic_sriov_cleanup_transaction(trans);
1250 }
1251 } else {
1252 spin_lock(&vf->rcv_pend.lock);
1253 list_add_tail(&trans->list, &vf->rcv_pend.wait_list);
1254 vf->rcv_pend.count++;
1255 spin_unlock(&vf->rcv_pend.lock);
1256 }
1257 }
1258
1259 static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov *sriov,
1260 struct qlcnic_vf_info *vf)
1261 {
1262 struct qlcnic_bc_hdr hdr;
1263 u32 *ptr = (u32 *)&hdr;
1264 u8 msg_type, i;
1265
1266 for (i = 2; i < 6; i++)
1267 ptr[i - 2] = readl(QLCNIC_MBX_FW(vf->adapter->ahw, i));
1268 msg_type = hdr.msg_type;
1269
1270 switch (msg_type) {
1271 case QLC_BC_COMMAND:
1272 qlcnic_sriov_handle_bc_cmd(sriov, &hdr, vf);
1273 break;
1274 case QLC_BC_RESPONSE:
1275 qlcnic_sriov_handle_bc_resp(&hdr, vf);
1276 break;
1277 }
1278 }
1279
1280 static void qlcnic_sriov_handle_flr_event(struct qlcnic_sriov *sriov,
1281 struct qlcnic_vf_info *vf)
1282 {
1283 struct qlcnic_adapter *adapter = vf->adapter;
1284
1285 if (qlcnic_sriov_pf_check(adapter))
1286 qlcnic_sriov_pf_handle_flr(sriov, vf);
1287 else
1288 dev_err(&adapter->pdev->dev,
1289 "Invalid event to VF. VF should not get FLR event\n");
1290 }
1291
1292 void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *adapter, u32 event)
1293 {
1294 struct qlcnic_vf_info *vf;
1295 struct qlcnic_sriov *sriov;
1296 int index;
1297 u8 pci_func;
1298
1299 sriov = adapter->ahw->sriov;
1300 pci_func = qlcnic_sriov_target_func_id(event);
1301 index = qlcnic_sriov_func_to_index(adapter, pci_func);
1302
1303 if (index < 0)
1304 return;
1305
1306 vf = &sriov->vf_info[index];
1307 vf->pci_func = pci_func;
1308
1309 if (qlcnic_sriov_channel_free_check(event))
1310 complete(&vf->ch_free_cmpl);
1311
1312 if (qlcnic_sriov_flr_check(event)) {
1313 qlcnic_sriov_handle_flr_event(sriov, vf);
1314 return;
1315 }
1316
1317 if (qlcnic_sriov_bc_msg_check(event))
1318 qlcnic_sriov_handle_msg_event(sriov, vf);
1319 }
1320
1321 int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *adapter, u8 enable)
1322 {
1323 struct qlcnic_cmd_args cmd;
1324 int err;
1325
1326 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
1327 return 0;
1328
1329 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_BC_EVENT_SETUP))
1330 return -ENOMEM;
1331
1332 if (enable)
1333 cmd.req.arg[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
1334
1335 err = qlcnic_83xx_issue_cmd(adapter, &cmd);
1336
1337 if (err != QLCNIC_RCODE_SUCCESS) {
1338 dev_err(&adapter->pdev->dev,
1339 "Failed to %s bc events, err=%d\n",
1340 (enable ? "enable" : "disable"), err);
1341 }
1342
1343 qlcnic_free_mbx_args(&cmd);
1344 return err;
1345 }
1346
1347 static int qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter *adapter,
1348 struct qlcnic_bc_trans *trans)
1349 {
1350 u8 max = QLC_BC_CMD_MAX_RETRY_CNT;
1351 u32 state;
1352
1353 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1354 if (state == QLC_83XX_IDC_DEV_READY) {
1355 msleep(20);
1356 clear_bit(QLC_BC_VF_CHANNEL, &trans->vf->state);
1357 trans->trans_state = QLC_INIT;
1358 if (++adapter->fw_fail_cnt > max)
1359 return -EIO;
1360 else
1361 return 0;
1362 }
1363
1364 return -EIO;
1365 }
1366
1367 static int __qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1368 struct qlcnic_cmd_args *cmd)
1369 {
1370 struct qlcnic_hardware_context *ahw = adapter->ahw;
1371 struct qlcnic_mailbox *mbx = ahw->mailbox;
1372 struct device *dev = &adapter->pdev->dev;
1373 struct qlcnic_bc_trans *trans;
1374 int err;
1375 u32 rsp_data, opcode, mbx_err_code, rsp;
1376 u16 seq = ++adapter->ahw->sriov->bc.trans_counter;
1377 u8 func = ahw->pci_func;
1378
1379 rsp = qlcnic_sriov_alloc_bc_trans(&trans);
1380 if (rsp)
1381 goto free_cmd;
1382
1383 rsp = qlcnic_sriov_prepare_bc_hdr(trans, cmd, seq, QLC_BC_COMMAND);
1384 if (rsp)
1385 goto cleanup_transaction;
1386
1387 retry:
1388 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
1389 rsp = -EIO;
1390 QLCDB(adapter, DRV, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n",
1391 QLCNIC_MBX_RSP(cmd->req.arg[0]), func);
1392 goto err_out;
1393 }
1394
1395 err = qlcnic_sriov_send_bc_cmd(adapter, trans, func);
1396 if (err) {
1397 dev_err(dev, "MBX command 0x%x timed out for VF %d\n",
1398 (cmd->req.arg[0] & 0xffff), func);
1399 rsp = QLCNIC_RCODE_TIMEOUT;
1400
1401 /* After adapter reset PF driver may take some time to
1402 * respond to VF's request. Retry request till maximum retries.
1403 */
1404 if ((trans->req_hdr->cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT) &&
1405 !qlcnic_sriov_retry_bc_cmd(adapter, trans))
1406 goto retry;
1407
1408 goto err_out;
1409 }
1410
1411 rsp_data = cmd->rsp.arg[0];
1412 mbx_err_code = QLCNIC_MBX_STATUS(rsp_data);
1413 opcode = QLCNIC_MBX_RSP(cmd->req.arg[0]);
1414
1415 if ((mbx_err_code == QLCNIC_MBX_RSP_OK) ||
1416 (mbx_err_code == QLCNIC_MBX_PORT_RSP_OK)) {
1417 rsp = QLCNIC_RCODE_SUCCESS;
1418 } else {
1419 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1420 rsp = QLCNIC_RCODE_SUCCESS;
1421 } else {
1422 rsp = mbx_err_code;
1423 if (!rsp)
1424 rsp = 1;
1425
1426 dev_err(dev,
1427 "MBX command 0x%x failed with err:0x%x for VF %d\n",
1428 opcode, mbx_err_code, func);
1429 }
1430 }
1431
1432 err_out:
1433 if (rsp == QLCNIC_RCODE_TIMEOUT) {
1434 ahw->reset_context = 1;
1435 adapter->need_fw_reset = 1;
1436 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1437 }
1438
1439 cleanup_transaction:
1440 qlcnic_sriov_cleanup_transaction(trans);
1441
1442 free_cmd:
1443 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1444 qlcnic_free_mbx_args(cmd);
1445 kfree(cmd);
1446 }
1447
1448 return rsp;
1449 }
1450
1451
1452 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1453 struct qlcnic_cmd_args *cmd)
1454 {
1455 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT)
1456 return qlcnic_sriov_async_issue_cmd(adapter, cmd);
1457 else
1458 return __qlcnic_sriov_issue_cmd(adapter, cmd);
1459 }
1460
1461 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *adapter, u8 cmd_op)
1462 {
1463 struct qlcnic_cmd_args cmd;
1464 struct qlcnic_vf_info *vf = &adapter->ahw->sriov->vf_info[0];
1465 int ret;
1466
1467 memset(&cmd, 0, sizeof(cmd));
1468 if (qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op))
1469 return -ENOMEM;
1470
1471 ret = qlcnic_issue_cmd(adapter, &cmd);
1472 if (ret) {
1473 dev_err(&adapter->pdev->dev,
1474 "Failed bc channel %s %d\n", cmd_op ? "term" : "init",
1475 ret);
1476 goto out;
1477 }
1478
1479 cmd_op = (cmd.rsp.arg[0] & 0xff);
1480 if (cmd.rsp.arg[0] >> 25 == 2)
1481 return 2;
1482 if (cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT)
1483 set_bit(QLC_BC_VF_STATE, &vf->state);
1484 else
1485 clear_bit(QLC_BC_VF_STATE, &vf->state);
1486
1487 out:
1488 qlcnic_free_mbx_args(&cmd);
1489 return ret;
1490 }
1491
1492 static void qlcnic_vf_add_mc_list(struct net_device *netdev, const u8 *mac)
1493 {
1494 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1495 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1496 struct qlcnic_vf_info *vf;
1497 u16 vlan_id;
1498 int i;
1499
1500 vf = &adapter->ahw->sriov->vf_info[0];
1501
1502 if (!qlcnic_sriov_check_any_vlan(vf)) {
1503 qlcnic_nic_add_mac(adapter, mac, 0);
1504 } else {
1505 spin_lock(&vf->vlan_list_lock);
1506 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1507 vlan_id = vf->sriov_vlans[i];
1508 if (vlan_id)
1509 qlcnic_nic_add_mac(adapter, mac, vlan_id);
1510 }
1511 spin_unlock(&vf->vlan_list_lock);
1512 if (qlcnic_84xx_check(adapter))
1513 qlcnic_nic_add_mac(adapter, mac, 0);
1514 }
1515 }
1516
1517 void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel *bc)
1518 {
1519 struct list_head *head = &bc->async_list;
1520 struct qlcnic_async_work_list *entry;
1521
1522 flush_workqueue(bc->bc_async_wq);
1523 while (!list_empty(head)) {
1524 entry = list_entry(head->next, struct qlcnic_async_work_list,
1525 list);
1526 cancel_work_sync(&entry->work);
1527 list_del(&entry->list);
1528 kfree(entry);
1529 }
1530 }
1531
1532 void qlcnic_sriov_vf_set_multi(struct net_device *netdev)
1533 {
1534 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1535 struct qlcnic_hardware_context *ahw = adapter->ahw;
1536 static const u8 bcast_addr[ETH_ALEN] = {
1537 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
1538 };
1539 struct netdev_hw_addr *ha;
1540 u32 mode = VPORT_MISS_MODE_DROP;
1541
1542 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
1543 return;
1544
1545 if (netdev->flags & IFF_PROMISC) {
1546 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
1547 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1548 } else if ((netdev->flags & IFF_ALLMULTI) ||
1549 (netdev_mc_count(netdev) > ahw->max_mc_count)) {
1550 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1551 } else {
1552 qlcnic_vf_add_mc_list(netdev, bcast_addr);
1553 if (!netdev_mc_empty(netdev)) {
1554 netdev_for_each_mc_addr(ha, netdev)
1555 qlcnic_vf_add_mc_list(netdev, ha->addr);
1556 }
1557 }
1558
1559 /* configure unicast MAC address, if there is not sufficient space
1560 * to store all the unicast addresses then enable promiscuous mode
1561 */
1562 if (netdev_uc_count(netdev) > ahw->max_uc_count) {
1563 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1564 } else if (!netdev_uc_empty(netdev)) {
1565 netdev_for_each_uc_addr(ha, netdev)
1566 qlcnic_vf_add_mc_list(netdev, ha->addr);
1567 }
1568
1569 if (adapter->pdev->is_virtfn) {
1570 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
1571 !adapter->fdb_mac_learn) {
1572 qlcnic_alloc_lb_filters_mem(adapter);
1573 adapter->drv_mac_learn = 1;
1574 adapter->rx_mac_learn = true;
1575 } else {
1576 adapter->drv_mac_learn = 0;
1577 adapter->rx_mac_learn = false;
1578 }
1579 }
1580
1581 qlcnic_nic_set_promisc(adapter, mode);
1582 }
1583
1584 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work)
1585 {
1586 struct qlcnic_async_work_list *entry;
1587 struct qlcnic_adapter *adapter;
1588 struct qlcnic_cmd_args *cmd;
1589
1590 entry = container_of(work, struct qlcnic_async_work_list, work);
1591 adapter = entry->ptr;
1592 cmd = entry->cmd;
1593 __qlcnic_sriov_issue_cmd(adapter, cmd);
1594 return;
1595 }
1596
1597 static struct qlcnic_async_work_list *
1598 qlcnic_sriov_get_free_node_async_work(struct qlcnic_back_channel *bc)
1599 {
1600 struct list_head *node;
1601 struct qlcnic_async_work_list *entry = NULL;
1602 u8 empty = 0;
1603
1604 list_for_each(node, &bc->async_list) {
1605 entry = list_entry(node, struct qlcnic_async_work_list, list);
1606 if (!work_pending(&entry->work)) {
1607 empty = 1;
1608 break;
1609 }
1610 }
1611
1612 if (!empty) {
1613 entry = kzalloc(sizeof(struct qlcnic_async_work_list),
1614 GFP_ATOMIC);
1615 if (entry == NULL)
1616 return NULL;
1617 list_add_tail(&entry->list, &bc->async_list);
1618 }
1619
1620 return entry;
1621 }
1622
1623 static void qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel *bc,
1624 work_func_t func, void *data,
1625 struct qlcnic_cmd_args *cmd)
1626 {
1627 struct qlcnic_async_work_list *entry = NULL;
1628
1629 entry = qlcnic_sriov_get_free_node_async_work(bc);
1630 if (!entry)
1631 return;
1632
1633 entry->ptr = data;
1634 entry->cmd = cmd;
1635 INIT_WORK(&entry->work, func);
1636 queue_work(bc->bc_async_wq, &entry->work);
1637 }
1638
1639 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *adapter,
1640 struct qlcnic_cmd_args *cmd)
1641 {
1642
1643 struct qlcnic_back_channel *bc = &adapter->ahw->sriov->bc;
1644
1645 if (adapter->need_fw_reset)
1646 return -EIO;
1647
1648 qlcnic_sriov_schedule_async_cmd(bc, qlcnic_sriov_handle_async_issue_cmd,
1649 adapter, cmd);
1650 return 0;
1651 }
1652
1653 static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter *adapter)
1654 {
1655 int err;
1656
1657 adapter->need_fw_reset = 0;
1658 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
1659 qlcnic_83xx_enable_mbx_interrupt(adapter);
1660
1661 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
1662 if (err)
1663 return err;
1664
1665 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
1666 if (err)
1667 goto err_out_cleanup_bc_intr;
1668
1669 err = qlcnic_sriov_vf_init_driver(adapter);
1670 if (err)
1671 goto err_out_term_channel;
1672
1673 return 0;
1674
1675 err_out_term_channel:
1676 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
1677
1678 err_out_cleanup_bc_intr:
1679 qlcnic_sriov_cfg_bc_intr(adapter, 0);
1680 return err;
1681 }
1682
1683 static void qlcnic_sriov_vf_attach(struct qlcnic_adapter *adapter)
1684 {
1685 struct net_device *netdev = adapter->netdev;
1686
1687 if (netif_running(netdev)) {
1688 if (!qlcnic_up(adapter, netdev))
1689 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1690 }
1691
1692 netif_device_attach(netdev);
1693 }
1694
1695 static void qlcnic_sriov_vf_detach(struct qlcnic_adapter *adapter)
1696 {
1697 struct qlcnic_hardware_context *ahw = adapter->ahw;
1698 struct qlcnic_intrpt_config *intr_tbl = ahw->intr_tbl;
1699 struct net_device *netdev = adapter->netdev;
1700 u8 i, max_ints = ahw->num_msix - 1;
1701
1702 netif_device_detach(netdev);
1703 qlcnic_83xx_detach_mailbox_work(adapter);
1704 qlcnic_83xx_disable_mbx_intr(adapter);
1705
1706 if (netif_running(netdev))
1707 qlcnic_down(adapter, netdev);
1708
1709 for (i = 0; i < max_ints; i++) {
1710 intr_tbl[i].id = i;
1711 intr_tbl[i].enabled = 0;
1712 intr_tbl[i].src = 0;
1713 }
1714 ahw->reset_context = 0;
1715 }
1716
1717 static int qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter *adapter)
1718 {
1719 struct qlcnic_hardware_context *ahw = adapter->ahw;
1720 struct device *dev = &adapter->pdev->dev;
1721 struct qlc_83xx_idc *idc = &ahw->idc;
1722 u8 func = ahw->pci_func;
1723 u32 state;
1724
1725 if ((idc->prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
1726 (idc->prev_state == QLC_83XX_IDC_DEV_INIT)) {
1727 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1728 qlcnic_sriov_vf_attach(adapter);
1729 adapter->fw_fail_cnt = 0;
1730 dev_info(dev,
1731 "%s: Reinitialization of VF 0x%x done after FW reset\n",
1732 __func__, func);
1733 } else {
1734 dev_err(dev,
1735 "%s: Reinitialization of VF 0x%x failed after FW reset\n",
1736 __func__, func);
1737 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1738 dev_info(dev, "Current state 0x%x after FW reset\n",
1739 state);
1740 }
1741 }
1742
1743 return 0;
1744 }
1745
1746 static int qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter *adapter)
1747 {
1748 struct qlcnic_hardware_context *ahw = adapter->ahw;
1749 struct qlcnic_mailbox *mbx = ahw->mailbox;
1750 struct device *dev = &adapter->pdev->dev;
1751 struct qlc_83xx_idc *idc = &ahw->idc;
1752 u8 func = ahw->pci_func;
1753 u32 state;
1754
1755 adapter->reset_ctx_cnt++;
1756
1757 /* Skip the context reset and check if FW is hung */
1758 if (adapter->reset_ctx_cnt < 3) {
1759 adapter->need_fw_reset = 1;
1760 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1761 dev_info(dev,
1762 "Resetting context, wait here to check if FW is in failed state\n");
1763 return 0;
1764 }
1765
1766 /* Check if number of resets exceed the threshold.
1767 * If it exceeds the threshold just fail the VF.
1768 */
1769 if (adapter->reset_ctx_cnt > QLC_83XX_VF_RESET_FAIL_THRESH) {
1770 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1771 adapter->tx_timeo_cnt = 0;
1772 adapter->fw_fail_cnt = 0;
1773 adapter->reset_ctx_cnt = 0;
1774 qlcnic_sriov_vf_detach(adapter);
1775 dev_err(dev,
1776 "Device context resets have exceeded the threshold, device interface will be shutdown\n");
1777 return -EIO;
1778 }
1779
1780 dev_info(dev, "Resetting context of VF 0x%x\n", func);
1781 dev_info(dev, "%s: Context reset count %d for VF 0x%x\n",
1782 __func__, adapter->reset_ctx_cnt, func);
1783 set_bit(__QLCNIC_RESETTING, &adapter->state);
1784 adapter->need_fw_reset = 1;
1785 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1786 qlcnic_sriov_vf_detach(adapter);
1787 adapter->need_fw_reset = 0;
1788
1789 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1790 qlcnic_sriov_vf_attach(adapter);
1791 adapter->tx_timeo_cnt = 0;
1792 adapter->reset_ctx_cnt = 0;
1793 adapter->fw_fail_cnt = 0;
1794 dev_info(dev, "Done resetting context for VF 0x%x\n", func);
1795 } else {
1796 dev_err(dev, "%s: Reinitialization of VF 0x%x failed\n",
1797 __func__, func);
1798 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1799 dev_info(dev, "%s: Current state 0x%x\n", __func__, state);
1800 }
1801
1802 return 0;
1803 }
1804
1805 static int qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter *adapter)
1806 {
1807 struct qlcnic_hardware_context *ahw = adapter->ahw;
1808 int ret = 0;
1809
1810 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY)
1811 ret = qlcnic_sriov_vf_handle_dev_ready(adapter);
1812 else if (ahw->reset_context)
1813 ret = qlcnic_sriov_vf_handle_context_reset(adapter);
1814
1815 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1816 return ret;
1817 }
1818
1819 static int qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter *adapter)
1820 {
1821 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1822
1823 dev_err(&adapter->pdev->dev, "Device is in failed state\n");
1824 if (idc->prev_state == QLC_83XX_IDC_DEV_READY)
1825 qlcnic_sriov_vf_detach(adapter);
1826
1827 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1828 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1829 return -EIO;
1830 }
1831
1832 static int
1833 qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter *adapter)
1834 {
1835 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1836 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1837
1838 dev_info(&adapter->pdev->dev, "Device is in quiescent state\n");
1839 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1840 set_bit(__QLCNIC_RESETTING, &adapter->state);
1841 adapter->tx_timeo_cnt = 0;
1842 adapter->reset_ctx_cnt = 0;
1843 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1844 qlcnic_sriov_vf_detach(adapter);
1845 }
1846
1847 return 0;
1848 }
1849
1850 static int qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter *adapter)
1851 {
1852 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1853 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1854 u8 func = adapter->ahw->pci_func;
1855
1856 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1857 dev_err(&adapter->pdev->dev,
1858 "Firmware hang detected by VF 0x%x\n", func);
1859 set_bit(__QLCNIC_RESETTING, &adapter->state);
1860 adapter->tx_timeo_cnt = 0;
1861 adapter->reset_ctx_cnt = 0;
1862 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1863 qlcnic_sriov_vf_detach(adapter);
1864 }
1865 return 0;
1866 }
1867
1868 static int qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter *adapter)
1869 {
1870 dev_err(&adapter->pdev->dev, "%s: Device in unknown state\n", __func__);
1871 return 0;
1872 }
1873
1874 static void qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter *adapter)
1875 {
1876 if (adapter->fhash.fnum)
1877 qlcnic_prune_lb_filters(adapter);
1878 }
1879
1880 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *work)
1881 {
1882 struct qlcnic_adapter *adapter;
1883 struct qlc_83xx_idc *idc;
1884 int ret = 0;
1885
1886 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1887 idc = &adapter->ahw->idc;
1888 idc->curr_state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1889
1890 switch (idc->curr_state) {
1891 case QLC_83XX_IDC_DEV_READY:
1892 ret = qlcnic_sriov_vf_idc_ready_state(adapter);
1893 break;
1894 case QLC_83XX_IDC_DEV_NEED_RESET:
1895 case QLC_83XX_IDC_DEV_INIT:
1896 ret = qlcnic_sriov_vf_idc_init_reset_state(adapter);
1897 break;
1898 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1899 ret = qlcnic_sriov_vf_idc_need_quiescent_state(adapter);
1900 break;
1901 case QLC_83XX_IDC_DEV_FAILED:
1902 ret = qlcnic_sriov_vf_idc_failed_state(adapter);
1903 break;
1904 case QLC_83XX_IDC_DEV_QUISCENT:
1905 break;
1906 default:
1907 ret = qlcnic_sriov_vf_idc_unknown_state(adapter);
1908 }
1909
1910 idc->prev_state = idc->curr_state;
1911 qlcnic_sriov_vf_periodic_tasks(adapter);
1912
1913 if (!ret && test_bit(QLC_83XX_MODULE_LOADED, &idc->status))
1914 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
1915 idc->delay);
1916 }
1917
1918 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *adapter)
1919 {
1920 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1921 msleep(20);
1922
1923 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1924 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1925 cancel_delayed_work_sync(&adapter->fw_work);
1926 }
1927
1928 static int qlcnic_sriov_check_vlan_id(struct qlcnic_sriov *sriov,
1929 struct qlcnic_vf_info *vf, u16 vlan_id)
1930 {
1931 int i, err = -EINVAL;
1932
1933 if (!vf->sriov_vlans)
1934 return err;
1935
1936 spin_lock_bh(&vf->vlan_list_lock);
1937
1938 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1939 if (vf->sriov_vlans[i] == vlan_id) {
1940 err = 0;
1941 break;
1942 }
1943 }
1944
1945 spin_unlock_bh(&vf->vlan_list_lock);
1946 return err;
1947 }
1948
1949 static int qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov *sriov,
1950 struct qlcnic_vf_info *vf)
1951 {
1952 int err = 0;
1953
1954 spin_lock_bh(&vf->vlan_list_lock);
1955
1956 if (vf->num_vlan >= sriov->num_allowed_vlans)
1957 err = -EINVAL;
1958
1959 spin_unlock_bh(&vf->vlan_list_lock);
1960 return err;
1961 }
1962
1963 static int qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter *adapter,
1964 u16 vid, u8 enable)
1965 {
1966 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1967 struct qlcnic_vf_info *vf;
1968 bool vlan_exist;
1969 u8 allowed = 0;
1970 int i;
1971
1972 vf = &adapter->ahw->sriov->vf_info[0];
1973 vlan_exist = qlcnic_sriov_check_any_vlan(vf);
1974 if (sriov->vlan_mode != QLC_GUEST_VLAN_MODE)
1975 return -EINVAL;
1976
1977 if (enable) {
1978 if (qlcnic_83xx_vf_check(adapter) && vlan_exist)
1979 return -EINVAL;
1980
1981 if (qlcnic_sriov_validate_num_vlans(sriov, vf))
1982 return -EINVAL;
1983
1984 if (sriov->any_vlan) {
1985 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1986 if (sriov->allowed_vlans[i] == vid)
1987 allowed = 1;
1988 }
1989
1990 if (!allowed)
1991 return -EINVAL;
1992 }
1993 } else {
1994 if (!vlan_exist || qlcnic_sriov_check_vlan_id(sriov, vf, vid))
1995 return -EINVAL;
1996 }
1997
1998 return 0;
1999 }
2000
2001 static void qlcnic_sriov_vlan_operation(struct qlcnic_vf_info *vf, u16 vlan_id,
2002 enum qlcnic_vlan_operations opcode)
2003 {
2004 struct qlcnic_adapter *adapter = vf->adapter;
2005 struct qlcnic_sriov *sriov;
2006
2007 sriov = adapter->ahw->sriov;
2008
2009 if (!vf->sriov_vlans)
2010 return;
2011
2012 spin_lock_bh(&vf->vlan_list_lock);
2013
2014 switch (opcode) {
2015 case QLC_VLAN_ADD:
2016 qlcnic_sriov_add_vlan_id(sriov, vf, vlan_id);
2017 break;
2018 case QLC_VLAN_DELETE:
2019 qlcnic_sriov_del_vlan_id(sriov, vf, vlan_id);
2020 break;
2021 default:
2022 netdev_err(adapter->netdev, "Invalid VLAN operation\n");
2023 }
2024
2025 spin_unlock_bh(&vf->vlan_list_lock);
2026 return;
2027 }
2028
2029 int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter *adapter,
2030 u16 vid, u8 enable)
2031 {
2032 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2033 struct net_device *netdev = adapter->netdev;
2034 struct qlcnic_vf_info *vf;
2035 struct qlcnic_cmd_args cmd;
2036 int ret;
2037
2038 memset(&cmd, 0, sizeof(cmd));
2039 if (vid == 0)
2040 return 0;
2041
2042 vf = &adapter->ahw->sriov->vf_info[0];
2043 ret = qlcnic_sriov_validate_vlan_cfg(adapter, vid, enable);
2044 if (ret)
2045 return ret;
2046
2047 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd,
2048 QLCNIC_BC_CMD_CFG_GUEST_VLAN);
2049 if (ret)
2050 return ret;
2051
2052 cmd.req.arg[1] = (enable & 1) | vid << 16;
2053
2054 qlcnic_sriov_cleanup_async_list(&sriov->bc);
2055 ret = qlcnic_issue_cmd(adapter, &cmd);
2056 if (ret) {
2057 dev_err(&adapter->pdev->dev,
2058 "Failed to configure guest VLAN, err=%d\n", ret);
2059 } else {
2060 netif_addr_lock_bh(netdev);
2061 qlcnic_free_mac_list(adapter);
2062 netif_addr_unlock_bh(netdev);
2063
2064 if (enable)
2065 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_ADD);
2066 else
2067 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_DELETE);
2068
2069 netif_addr_lock_bh(netdev);
2070 qlcnic_set_multi(netdev);
2071 netif_addr_unlock_bh(netdev);
2072 }
2073
2074 qlcnic_free_mbx_args(&cmd);
2075 return ret;
2076 }
2077
2078 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *adapter)
2079 {
2080 struct list_head *head = &adapter->mac_list;
2081 struct qlcnic_mac_vlan_list *cur;
2082
2083 while (!list_empty(head)) {
2084 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
2085 qlcnic_sre_macaddr_change(adapter, cur->mac_addr, cur->vlan_id,
2086 QLCNIC_MAC_DEL);
2087 list_del(&cur->list);
2088 kfree(cur);
2089 }
2090 }
2091
2092
2093 static int qlcnic_sriov_vf_shutdown(struct pci_dev *pdev)
2094 {
2095 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
2096 struct net_device *netdev = adapter->netdev;
2097 int retval;
2098
2099 netif_device_detach(netdev);
2100 qlcnic_cancel_idc_work(adapter);
2101
2102 if (netif_running(netdev))
2103 qlcnic_down(adapter, netdev);
2104
2105 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
2106 qlcnic_sriov_cfg_bc_intr(adapter, 0);
2107 qlcnic_83xx_disable_mbx_intr(adapter);
2108 cancel_delayed_work_sync(&adapter->idc_aen_work);
2109
2110 retval = pci_save_state(pdev);
2111 if (retval)
2112 return retval;
2113
2114 return 0;
2115 }
2116
2117 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *adapter)
2118 {
2119 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
2120 struct net_device *netdev = adapter->netdev;
2121 int err;
2122
2123 set_bit(QLC_83XX_MODULE_LOADED, &idc->status);
2124 qlcnic_83xx_enable_mbx_interrupt(adapter);
2125 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
2126 if (err)
2127 return err;
2128
2129 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
2130 if (!err) {
2131 if (netif_running(netdev)) {
2132 err = qlcnic_up(adapter, netdev);
2133 if (!err)
2134 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
2135 }
2136 }
2137
2138 netif_device_attach(netdev);
2139 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
2140 idc->delay);
2141 return err;
2142 }
2143
2144 void qlcnic_sriov_alloc_vlans(struct qlcnic_adapter *adapter)
2145 {
2146 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2147 struct qlcnic_vf_info *vf;
2148 int i;
2149
2150 for (i = 0; i < sriov->num_vfs; i++) {
2151 vf = &sriov->vf_info[i];
2152 vf->sriov_vlans = kcalloc(sriov->num_allowed_vlans,
2153 sizeof(*vf->sriov_vlans), GFP_KERNEL);
2154 }
2155 }
2156
2157 void qlcnic_sriov_free_vlans(struct qlcnic_adapter *adapter)
2158 {
2159 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2160 struct qlcnic_vf_info *vf;
2161 int i;
2162
2163 for (i = 0; i < sriov->num_vfs; i++) {
2164 vf = &sriov->vf_info[i];
2165 kfree(vf->sriov_vlans);
2166 vf->sriov_vlans = NULL;
2167 }
2168 }
2169
2170 void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov *sriov,
2171 struct qlcnic_vf_info *vf, u16 vlan_id)
2172 {
2173 int i;
2174
2175 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2176 if (!vf->sriov_vlans[i]) {
2177 vf->sriov_vlans[i] = vlan_id;
2178 vf->num_vlan++;
2179 return;
2180 }
2181 }
2182 }
2183
2184 void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov *sriov,
2185 struct qlcnic_vf_info *vf, u16 vlan_id)
2186 {
2187 int i;
2188
2189 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2190 if (vf->sriov_vlans[i] == vlan_id) {
2191 vf->sriov_vlans[i] = 0;
2192 vf->num_vlan--;
2193 return;
2194 }
2195 }
2196 }
2197
2198 bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info *vf)
2199 {
2200 bool err = false;
2201
2202 spin_lock_bh(&vf->vlan_list_lock);
2203
2204 if (vf->num_vlan)
2205 err = true;
2206
2207 spin_unlock_bh(&vf->vlan_list_lock);
2208 return err;
2209 }
Linux with added FPC-III support