2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2009-2012 Cavium, Inc.
9 #include <linux/platform_device.h>
10 #include <linux/of_mdio.h>
11 #include <linux/delay.h>
12 #include <linux/module.h>
13 #include <linux/gfp.h>
14 #include <linux/phy.h>
17 #include <asm/octeon/octeon.h>
18 #include <asm/octeon/cvmx-smix-defs.h>
20 #define DRV_VERSION "1.0"
21 #define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
24 #define SMI_WR_DAT 0x8
25 #define SMI_RD_DAT 0x10
29 enum octeon_mdiobus_mode
{
35 struct octeon_mdiobus
{
36 struct mii_bus
*mii_bus
;
38 resource_size_t mdio_phys
;
39 resource_size_t regsize
;
40 enum octeon_mdiobus_mode mode
;
41 int phy_irq
[PHY_MAX_ADDR
];
44 static void octeon_mdiobus_set_mode(struct octeon_mdiobus
*p
,
45 enum octeon_mdiobus_mode m
)
47 union cvmx_smix_clk smi_clk
;
52 smi_clk
.u64
= cvmx_read_csr(p
->register_base
+ SMI_CLK
);
53 smi_clk
.s
.mode
= (m
== C45
) ? 1 : 0;
54 smi_clk
.s
.preamble
= 1;
55 cvmx_write_csr(p
->register_base
+ SMI_CLK
, smi_clk
.u64
);
59 static int octeon_mdiobus_c45_addr(struct octeon_mdiobus
*p
,
60 int phy_id
, int regnum
)
62 union cvmx_smix_cmd smi_cmd
;
63 union cvmx_smix_wr_dat smi_wr
;
66 octeon_mdiobus_set_mode(p
, C45
);
69 smi_wr
.s
.dat
= regnum
& 0xffff;
70 cvmx_write_csr(p
->register_base
+ SMI_WR_DAT
, smi_wr
.u64
);
72 regnum
= (regnum
>> 16) & 0x1f;
75 smi_cmd
.s
.phy_op
= 0; /* MDIO_CLAUSE_45_ADDRESS */
76 smi_cmd
.s
.phy_adr
= phy_id
;
77 smi_cmd
.s
.reg_adr
= regnum
;
78 cvmx_write_csr(p
->register_base
+ SMI_CMD
, smi_cmd
.u64
);
81 /* Wait 1000 clocks so we don't saturate the RSL bus
85 smi_wr
.u64
= cvmx_read_csr(p
->register_base
+ SMI_WR_DAT
);
86 } while (smi_wr
.s
.pending
&& --timeout
);
93 static int octeon_mdiobus_read(struct mii_bus
*bus
, int phy_id
, int regnum
)
95 struct octeon_mdiobus
*p
= bus
->priv
;
96 union cvmx_smix_cmd smi_cmd
;
97 union cvmx_smix_rd_dat smi_rd
;
98 unsigned int op
= 1; /* MDIO_CLAUSE_22_READ */
101 if (regnum
& MII_ADDR_C45
) {
102 int r
= octeon_mdiobus_c45_addr(p
, phy_id
, regnum
);
106 regnum
= (regnum
>> 16) & 0x1f;
107 op
= 3; /* MDIO_CLAUSE_45_READ */
109 octeon_mdiobus_set_mode(p
, C22
);
114 smi_cmd
.s
.phy_op
= op
;
115 smi_cmd
.s
.phy_adr
= phy_id
;
116 smi_cmd
.s
.reg_adr
= regnum
;
117 cvmx_write_csr(p
->register_base
+ SMI_CMD
, smi_cmd
.u64
);
120 /* Wait 1000 clocks so we don't saturate the RSL bus
124 smi_rd
.u64
= cvmx_read_csr(p
->register_base
+ SMI_RD_DAT
);
125 } while (smi_rd
.s
.pending
&& --timeout
);
133 static int octeon_mdiobus_write(struct mii_bus
*bus
, int phy_id
,
136 struct octeon_mdiobus
*p
= bus
->priv
;
137 union cvmx_smix_cmd smi_cmd
;
138 union cvmx_smix_wr_dat smi_wr
;
139 unsigned int op
= 0; /* MDIO_CLAUSE_22_WRITE */
143 if (regnum
& MII_ADDR_C45
) {
144 int r
= octeon_mdiobus_c45_addr(p
, phy_id
, regnum
);
148 regnum
= (regnum
>> 16) & 0x1f;
149 op
= 1; /* MDIO_CLAUSE_45_WRITE */
151 octeon_mdiobus_set_mode(p
, C22
);
156 cvmx_write_csr(p
->register_base
+ SMI_WR_DAT
, smi_wr
.u64
);
159 smi_cmd
.s
.phy_op
= op
;
160 smi_cmd
.s
.phy_adr
= phy_id
;
161 smi_cmd
.s
.reg_adr
= regnum
;
162 cvmx_write_csr(p
->register_base
+ SMI_CMD
, smi_cmd
.u64
);
165 /* Wait 1000 clocks so we don't saturate the RSL bus
169 smi_wr
.u64
= cvmx_read_csr(p
->register_base
+ SMI_WR_DAT
);
170 } while (smi_wr
.s
.pending
&& --timeout
);
178 static int octeon_mdiobus_probe(struct platform_device
*pdev
)
180 struct octeon_mdiobus
*bus
;
181 struct resource
*res_mem
;
182 union cvmx_smix_en smi_en
;
185 bus
= devm_kzalloc(&pdev
->dev
, sizeof(*bus
), GFP_KERNEL
);
189 res_mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
191 if (res_mem
== NULL
) {
192 dev_err(&pdev
->dev
, "found no memory resource\n");
196 bus
->mdio_phys
= res_mem
->start
;
197 bus
->regsize
= resource_size(res_mem
);
198 if (!devm_request_mem_region(&pdev
->dev
, bus
->mdio_phys
, bus
->regsize
,
200 dev_err(&pdev
->dev
, "request_mem_region failed\n");
204 (u64
)devm_ioremap(&pdev
->dev
, bus
->mdio_phys
, bus
->regsize
);
206 bus
->mii_bus
= mdiobus_alloc();
213 cvmx_write_csr(bus
->register_base
+ SMI_EN
, smi_en
.u64
);
215 bus
->mii_bus
->priv
= bus
;
216 bus
->mii_bus
->irq
= bus
->phy_irq
;
217 bus
->mii_bus
->name
= "mdio-octeon";
218 snprintf(bus
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%llx", bus
->register_base
);
219 bus
->mii_bus
->parent
= &pdev
->dev
;
221 bus
->mii_bus
->read
= octeon_mdiobus_read
;
222 bus
->mii_bus
->write
= octeon_mdiobus_write
;
224 platform_set_drvdata(pdev
, bus
);
226 err
= of_mdiobus_register(bus
->mii_bus
, pdev
->dev
.of_node
);
230 dev_info(&pdev
->dev
, "Version " DRV_VERSION
"\n");
234 mdiobus_free(bus
->mii_bus
);
237 cvmx_write_csr(bus
->register_base
+ SMI_EN
, smi_en
.u64
);
241 static int octeon_mdiobus_remove(struct platform_device
*pdev
)
243 struct octeon_mdiobus
*bus
;
244 union cvmx_smix_en smi_en
;
246 bus
= platform_get_drvdata(pdev
);
248 mdiobus_unregister(bus
->mii_bus
);
249 mdiobus_free(bus
->mii_bus
);
251 cvmx_write_csr(bus
->register_base
+ SMI_EN
, smi_en
.u64
);
255 static struct of_device_id octeon_mdiobus_match
[] = {
257 .compatible
= "cavium,octeon-3860-mdio",
261 MODULE_DEVICE_TABLE(of
, octeon_mdiobus_match
);
263 static struct platform_driver octeon_mdiobus_driver
= {
265 .name
= "mdio-octeon",
266 .of_match_table
= octeon_mdiobus_match
,
268 .probe
= octeon_mdiobus_probe
,
269 .remove
= octeon_mdiobus_remove
,
272 void octeon_mdiobus_force_mod_depencency(void)
274 /* Let ethernet drivers force us to be loaded. */
276 EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency
);
278 module_platform_driver(octeon_mdiobus_driver
);
280 MODULE_DESCRIPTION(DRV_DESCRIPTION
);
281 MODULE_VERSION(DRV_VERSION
);
282 MODULE_AUTHOR("David Daney");
283 MODULE_LICENSE("GPL");