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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_nx.c
blob54cb2ac9339bdd4441b9125333222bbfefb3732c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include <linux/delay.h>
9 #include <linux/pci.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
13
14 #define MASK(n) ((1ULL<<(n))-1)
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
25 #define BLOCK_PROTECT_BITS 0x0F
26
27 /* CRB window related */
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
33 ((off) & 0xf0000))
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
36
37 #define MAX_CRB_XFORM 60
38 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
39 static int qla82xx_crb_table_initialized;
40
41 #define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
44
45 static void qla82xx_crb_addr_transform_setup(void)
46 {
47 qla82xx_crb_addr_transform(XDMA);
48 qla82xx_crb_addr_transform(TIMR);
49 qla82xx_crb_addr_transform(SRE);
50 qla82xx_crb_addr_transform(SQN3);
51 qla82xx_crb_addr_transform(SQN2);
52 qla82xx_crb_addr_transform(SQN1);
53 qla82xx_crb_addr_transform(SQN0);
54 qla82xx_crb_addr_transform(SQS3);
55 qla82xx_crb_addr_transform(SQS2);
56 qla82xx_crb_addr_transform(SQS1);
57 qla82xx_crb_addr_transform(SQS0);
58 qla82xx_crb_addr_transform(RPMX7);
59 qla82xx_crb_addr_transform(RPMX6);
60 qla82xx_crb_addr_transform(RPMX5);
61 qla82xx_crb_addr_transform(RPMX4);
62 qla82xx_crb_addr_transform(RPMX3);
63 qla82xx_crb_addr_transform(RPMX2);
64 qla82xx_crb_addr_transform(RPMX1);
65 qla82xx_crb_addr_transform(RPMX0);
66 qla82xx_crb_addr_transform(ROMUSB);
67 qla82xx_crb_addr_transform(SN);
68 qla82xx_crb_addr_transform(QMN);
69 qla82xx_crb_addr_transform(QMS);
70 qla82xx_crb_addr_transform(PGNI);
71 qla82xx_crb_addr_transform(PGND);
72 qla82xx_crb_addr_transform(PGN3);
73 qla82xx_crb_addr_transform(PGN2);
74 qla82xx_crb_addr_transform(PGN1);
75 qla82xx_crb_addr_transform(PGN0);
76 qla82xx_crb_addr_transform(PGSI);
77 qla82xx_crb_addr_transform(PGSD);
78 qla82xx_crb_addr_transform(PGS3);
79 qla82xx_crb_addr_transform(PGS2);
80 qla82xx_crb_addr_transform(PGS1);
81 qla82xx_crb_addr_transform(PGS0);
82 qla82xx_crb_addr_transform(PS);
83 qla82xx_crb_addr_transform(PH);
84 qla82xx_crb_addr_transform(NIU);
85 qla82xx_crb_addr_transform(I2Q);
86 qla82xx_crb_addr_transform(EG);
87 qla82xx_crb_addr_transform(MN);
88 qla82xx_crb_addr_transform(MS);
89 qla82xx_crb_addr_transform(CAS2);
90 qla82xx_crb_addr_transform(CAS1);
91 qla82xx_crb_addr_transform(CAS0);
92 qla82xx_crb_addr_transform(CAM);
93 qla82xx_crb_addr_transform(C2C1);
94 qla82xx_crb_addr_transform(C2C0);
95 qla82xx_crb_addr_transform(SMB);
96 qla82xx_crb_addr_transform(OCM0);
97 /*
98 * Used only in P3 just define it for P2 also.
99 */
100 qla82xx_crb_addr_transform(I2C0);
101
102 qla82xx_crb_table_initialized = 1;
103 }
104
105 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
106 {{{0, 0, 0, 0} } },
107 {{{1, 0x0100000, 0x0102000, 0x120000},
108 {1, 0x0110000, 0x0120000, 0x130000},
109 {1, 0x0120000, 0x0122000, 0x124000},
110 {1, 0x0130000, 0x0132000, 0x126000},
111 {1, 0x0140000, 0x0142000, 0x128000},
112 {1, 0x0150000, 0x0152000, 0x12a000},
113 {1, 0x0160000, 0x0170000, 0x110000},
114 {1, 0x0170000, 0x0172000, 0x12e000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {1, 0x01e0000, 0x01e0800, 0x122000},
122 {0, 0x0000000, 0x0000000, 0x000000} } } ,
123 {{{1, 0x0200000, 0x0210000, 0x180000} } },
124 {{{0, 0, 0, 0} } },
125 {{{1, 0x0400000, 0x0401000, 0x169000} } },
126 {{{1, 0x0500000, 0x0510000, 0x140000} } },
127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
129 {{{1, 0x0800000, 0x0802000, 0x170000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {1, 0x08f0000, 0x08f2000, 0x172000} } },
145 {{{1, 0x0900000, 0x0902000, 0x174000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {1, 0x09f0000, 0x09f2000, 0x176000} } },
161 {{{0, 0x0a00000, 0x0a02000, 0x178000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
177 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
198 {{{1, 0x1100000, 0x1101000, 0x160000} } },
199 {{{1, 0x1200000, 0x1201000, 0x161000} } },
200 {{{1, 0x1300000, 0x1301000, 0x162000} } },
201 {{{1, 0x1400000, 0x1401000, 0x163000} } },
202 {{{1, 0x1500000, 0x1501000, 0x165000} } },
203 {{{1, 0x1600000, 0x1601000, 0x166000} } },
204 {{{0, 0, 0, 0} } },
205 {{{0, 0, 0, 0} } },
206 {{{0, 0, 0, 0} } },
207 {{{0, 0, 0, 0} } },
208 {{{0, 0, 0, 0} } },
209 {{{0, 0, 0, 0} } },
210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
213 {{{0} } },
214 {{{1, 0x2100000, 0x2102000, 0x120000},
215 {1, 0x2110000, 0x2120000, 0x130000},
216 {1, 0x2120000, 0x2122000, 0x124000},
217 {1, 0x2130000, 0x2132000, 0x126000},
218 {1, 0x2140000, 0x2142000, 0x128000},
219 {1, 0x2150000, 0x2152000, 0x12a000},
220 {1, 0x2160000, 0x2170000, 0x110000},
221 {1, 0x2170000, 0x2172000, 0x12e000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000} } },
230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
231 {{{0} } },
232 {{{0} } },
233 {{{0} } },
234 {{{0} } },
235 {{{0} } },
236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
237 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
248 {{{0} } },
249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
255 {{{0} } },
256 {{{0} } },
257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
260 };
261
262 /*
263 * top 12 bits of crb internal address (hub, agent)
264 */
265 static unsigned qla82xx_crb_hub_agt[64] = {
266 0,
267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
270 0,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
293 0,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
296 0,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
298 0,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
301 0,
302 0,
303 0,
304 0,
305 0,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
307 0,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
318 0,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
323 0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
327 0,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
329 0,
330 };
331
332 /* Device states */
333 static char *q_dev_state[] = {
334 "Unknown",
335 "Cold",
336 "Initializing",
337 "Ready",
338 "Need Reset",
339 "Need Quiescent",
340 "Failed",
341 "Quiescent",
342 };
343
344 char *qdev_state(uint32_t dev_state)
345 {
346 return q_dev_state[dev_state];
347 }
348
349 /*
350 * In: 'off' is offset from CRB space in 128M pci map
351 * Out: 'off' is 2M pci map addr
352 * side effect: lock crb window
353 */
354 static void
355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
356 {
357 u32 win_read;
358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
359
360 ha->crb_win = CRB_HI(*off);
361 writel(ha->crb_win,
362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
363
364 /* Read back value to make sure write has gone through before trying
365 * to use it.
366 */
367 win_read = RD_REG_DWORD((void __iomem *)
368 (CRB_WINDOW_2M + ha->nx_pcibase));
369 if (win_read != ha->crb_win) {
370 ql_dbg(ql_dbg_p3p, vha, 0xb000,
371 "%s: Written crbwin (0x%x) "
372 "!= Read crbwin (0x%x), off=0x%lx.\n",
373 __func__, ha->crb_win, win_read, *off);
374 }
375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
376 }
377
378 static inline unsigned long
379 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
380 {
381 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
382 /* See if we are currently pointing to the region we want to use next */
383 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
384 /* No need to change window. PCIX and PCIEregs are in both
385 * regs are in both windows.
386 */
387 return off;
388 }
389
390 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
391 /* We are in first CRB window */
392 if (ha->curr_window != 0)
393 WARN_ON(1);
394 return off;
395 }
396
397 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
398 /* We are in second CRB window */
399 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
400
401 if (ha->curr_window != 1)
402 return off;
403
404 /* We are in the QM or direct access
405 * register region - do nothing
406 */
407 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
408 (off < QLA82XX_PCI_CAMQM_MAX))
409 return off;
410 }
411 /* strange address given */
412 ql_dbg(ql_dbg_p3p, vha, 0xb001,
413 "%s: Warning: unm_nic_pci_set_crbwindow "
414 "called with an unknown address(%llx).\n",
415 QLA2XXX_DRIVER_NAME, off);
416 return off;
417 }
418
419 static int
420 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
421 {
422 struct crb_128M_2M_sub_block_map *m;
423
424 if (*off >= QLA82XX_CRB_MAX)
425 return -1;
426
427 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
428 *off = (*off - QLA82XX_PCI_CAMQM) +
429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
430 return 0;
431 }
432
433 if (*off < QLA82XX_PCI_CRBSPACE)
434 return -1;
435
436 *off -= QLA82XX_PCI_CRBSPACE;
437
438 /* Try direct map */
439 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
440
441 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
442 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
443 return 0;
444 }
445 /* Not in direct map, use crb window */
446 return 1;
447 }
448
449 #define CRB_WIN_LOCK_TIMEOUT 100000000
450 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
451 {
452 int done = 0, timeout = 0;
453
454 while (!done) {
455 /* acquire semaphore3 from PCI HW block */
456 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
457 if (done == 1)
458 break;
459 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
460 return -1;
461 timeout++;
462 }
463 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
464 return 0;
465 }
466
467 int
468 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
469 {
470 unsigned long flags = 0;
471 int rv;
472
473 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
474
475 BUG_ON(rv == -1);
476
477 if (rv == 1) {
478 write_lock_irqsave(&ha->hw_lock, flags);
479 qla82xx_crb_win_lock(ha);
480 qla82xx_pci_set_crbwindow_2M(ha, &off);
481 }
482
483 writel(data, (void __iomem *)off);
484
485 if (rv == 1) {
486 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
487 write_unlock_irqrestore(&ha->hw_lock, flags);
488 }
489 return 0;
490 }
491
492 int
493 qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
494 {
495 unsigned long flags = 0;
496 int rv;
497 u32 data;
498
499 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
500
501 BUG_ON(rv == -1);
502
503 if (rv == 1) {
504 write_lock_irqsave(&ha->hw_lock, flags);
505 qla82xx_crb_win_lock(ha);
506 qla82xx_pci_set_crbwindow_2M(ha, &off);
507 }
508 data = RD_REG_DWORD((void __iomem *)off);
509
510 if (rv == 1) {
511 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
512 write_unlock_irqrestore(&ha->hw_lock, flags);
513 }
514 return data;
515 }
516
517 #define IDC_LOCK_TIMEOUT 100000000
518 int qla82xx_idc_lock(struct qla_hw_data *ha)
519 {
520 int i;
521 int done = 0, timeout = 0;
522
523 while (!done) {
524 /* acquire semaphore5 from PCI HW block */
525 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
526 if (done == 1)
527 break;
528 if (timeout >= IDC_LOCK_TIMEOUT)
529 return -1;
530
531 timeout++;
532
533 /* Yield CPU */
534 if (!in_interrupt())
535 schedule();
536 else {
537 for (i = 0; i < 20; i++)
538 cpu_relax();
539 }
540 }
541
542 return 0;
543 }
544
545 void qla82xx_idc_unlock(struct qla_hw_data *ha)
546 {
547 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
548 }
549
550 /* PCI Windowing for DDR regions. */
551 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
552 (((addr) <= (high)) && ((addr) >= (low)))
553 /*
554 * check memory access boundary.
555 * used by test agent. support ddr access only for now
556 */
557 static unsigned long
558 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
559 unsigned long long addr, int size)
560 {
561 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
562 QLA82XX_ADDR_DDR_NET_MAX) ||
563 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET,
564 QLA82XX_ADDR_DDR_NET_MAX) ||
565 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
566 return 0;
567 else
568 return 1;
569 }
570
571 static int qla82xx_pci_set_window_warning_count;
572
573 static unsigned long
574 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
575 {
576 int window;
577 u32 win_read;
578 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
579
580 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
581 QLA82XX_ADDR_DDR_NET_MAX)) {
582 /* DDR network side */
583 window = MN_WIN(addr);
584 ha->ddr_mn_window = window;
585 qla82xx_wr_32(ha,
586 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
587 win_read = qla82xx_rd_32(ha,
588 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
589 if ((win_read << 17) != window) {
590 ql_dbg(ql_dbg_p3p, vha, 0xb003,
591 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
592 __func__, window, win_read);
593 }
594 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
595 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
596 QLA82XX_ADDR_OCM0_MAX)) {
597 unsigned int temp1;
598 if ((addr & 0x00ff800) == 0xff800) {
599 ql_log(ql_log_warn, vha, 0xb004,
600 "%s: QM access not handled.\n", __func__);
601 addr = -1UL;
602 }
603 window = OCM_WIN(addr);
604 ha->ddr_mn_window = window;
605 qla82xx_wr_32(ha,
606 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
607 win_read = qla82xx_rd_32(ha,
608 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
609 temp1 = ((window & 0x1FF) << 7) |
610 ((window & 0x0FFFE0000) >> 17);
611 if (win_read != temp1) {
612 ql_log(ql_log_warn, vha, 0xb005,
613 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
614 __func__, temp1, win_read);
615 }
616 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
617
618 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
619 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
620 /* QDR network side */
621 window = MS_WIN(addr);
622 ha->qdr_sn_window = window;
623 qla82xx_wr_32(ha,
624 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
625 win_read = qla82xx_rd_32(ha,
626 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
627 if (win_read != window) {
628 ql_log(ql_log_warn, vha, 0xb006,
629 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
630 __func__, window, win_read);
631 }
632 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
633 } else {
634 /*
635 * peg gdb frequently accesses memory that doesn't exist,
636 * this limits the chit chat so debugging isn't slowed down.
637 */
638 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
639 (qla82xx_pci_set_window_warning_count%64 == 0)) {
640 ql_log(ql_log_warn, vha, 0xb007,
641 "%s: Warning:%s Unknown address range!.\n",
642 __func__, QLA2XXX_DRIVER_NAME);
643 }
644 addr = -1UL;
645 }
646 return addr;
647 }
648
649 /* check if address is in the same windows as the previous access */
650 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
651 unsigned long long addr)
652 {
653 int window;
654 unsigned long long qdr_max;
655
656 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
657
658 /* DDR network side */
659 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
660 QLA82XX_ADDR_DDR_NET_MAX))
661 BUG();
662 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
663 QLA82XX_ADDR_OCM0_MAX))
664 return 1;
665 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
666 QLA82XX_ADDR_OCM1_MAX))
667 return 1;
668 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
669 /* QDR network side */
670 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
671 if (ha->qdr_sn_window == window)
672 return 1;
673 }
674 return 0;
675 }
676
677 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
678 u64 off, void *data, int size)
679 {
680 unsigned long flags;
681 void __iomem *addr = NULL;
682 int ret = 0;
683 u64 start;
684 uint8_t __iomem *mem_ptr = NULL;
685 unsigned long mem_base;
686 unsigned long mem_page;
687 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
688
689 write_lock_irqsave(&ha->hw_lock, flags);
690
691 /*
692 * If attempting to access unknown address or straddle hw windows,
693 * do not access.
694 */
695 start = qla82xx_pci_set_window(ha, off);
696 if ((start == -1UL) ||
697 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
698 write_unlock_irqrestore(&ha->hw_lock, flags);
699 ql_log(ql_log_fatal, vha, 0xb008,
700 "%s out of bound pci memory "
701 "access, offset is 0x%llx.\n",
702 QLA2XXX_DRIVER_NAME, off);
703 return -1;
704 }
705
706 write_unlock_irqrestore(&ha->hw_lock, flags);
707 mem_base = pci_resource_start(ha->pdev, 0);
708 mem_page = start & PAGE_MASK;
709 /* Map two pages whenever user tries to access addresses in two
710 * consecutive pages.
711 */
712 if (mem_page != ((start + size - 1) & PAGE_MASK))
713 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
714 else
715 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
716 if (mem_ptr == NULL) {
717 *(u8 *)data = 0;
718 return -1;
719 }
720 addr = mem_ptr;
721 addr += start & (PAGE_SIZE - 1);
722 write_lock_irqsave(&ha->hw_lock, flags);
723
724 switch (size) {
725 case 1:
726 *(u8 *)data = readb(addr);
727 break;
728 case 2:
729 *(u16 *)data = readw(addr);
730 break;
731 case 4:
732 *(u32 *)data = readl(addr);
733 break;
734 case 8:
735 *(u64 *)data = readq(addr);
736 break;
737 default:
738 ret = -1;
739 break;
740 }
741 write_unlock_irqrestore(&ha->hw_lock, flags);
742
743 if (mem_ptr)
744 iounmap(mem_ptr);
745 return ret;
746 }
747
748 static int
749 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
750 u64 off, void *data, int size)
751 {
752 unsigned long flags;
753 void __iomem *addr = NULL;
754 int ret = 0;
755 u64 start;
756 uint8_t __iomem *mem_ptr = NULL;
757 unsigned long mem_base;
758 unsigned long mem_page;
759 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
760
761 write_lock_irqsave(&ha->hw_lock, flags);
762
763 /*
764 * If attempting to access unknown address or straddle hw windows,
765 * do not access.
766 */
767 start = qla82xx_pci_set_window(ha, off);
768 if ((start == -1UL) ||
769 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
770 write_unlock_irqrestore(&ha->hw_lock, flags);
771 ql_log(ql_log_fatal, vha, 0xb009,
772 "%s out of bount memory "
773 "access, offset is 0x%llx.\n",
774 QLA2XXX_DRIVER_NAME, off);
775 return -1;
776 }
777
778 write_unlock_irqrestore(&ha->hw_lock, flags);
779 mem_base = pci_resource_start(ha->pdev, 0);
780 mem_page = start & PAGE_MASK;
781 /* Map two pages whenever user tries to access addresses in two
782 * consecutive pages.
783 */
784 if (mem_page != ((start + size - 1) & PAGE_MASK))
785 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
786 else
787 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
788 if (mem_ptr == NULL)
789 return -1;
790
791 addr = mem_ptr;
792 addr += start & (PAGE_SIZE - 1);
793 write_lock_irqsave(&ha->hw_lock, flags);
794
795 switch (size) {
796 case 1:
797 writeb(*(u8 *)data, addr);
798 break;
799 case 2:
800 writew(*(u16 *)data, addr);
801 break;
802 case 4:
803 writel(*(u32 *)data, addr);
804 break;
805 case 8:
806 writeq(*(u64 *)data, addr);
807 break;
808 default:
809 ret = -1;
810 break;
811 }
812 write_unlock_irqrestore(&ha->hw_lock, flags);
813 if (mem_ptr)
814 iounmap(mem_ptr);
815 return ret;
816 }
817
818 #define MTU_FUDGE_FACTOR 100
819 static unsigned long
820 qla82xx_decode_crb_addr(unsigned long addr)
821 {
822 int i;
823 unsigned long base_addr, offset, pci_base;
824
825 if (!qla82xx_crb_table_initialized)
826 qla82xx_crb_addr_transform_setup();
827
828 pci_base = ADDR_ERROR;
829 base_addr = addr & 0xfff00000;
830 offset = addr & 0x000fffff;
831
832 for (i = 0; i < MAX_CRB_XFORM; i++) {
833 if (crb_addr_xform[i] == base_addr) {
834 pci_base = i << 20;
835 break;
836 }
837 }
838 if (pci_base == ADDR_ERROR)
839 return pci_base;
840 return pci_base + offset;
841 }
842
843 static long rom_max_timeout = 100;
844 static long qla82xx_rom_lock_timeout = 100;
845
846 static int
847 qla82xx_rom_lock(struct qla_hw_data *ha)
848 {
849 int done = 0, timeout = 0;
850 uint32_t lock_owner = 0;
851 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
852
853 while (!done) {
854 /* acquire semaphore2 from PCI HW block */
855 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
856 if (done == 1)
857 break;
858 if (timeout >= qla82xx_rom_lock_timeout) {
859 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
860 ql_dbg(ql_dbg_p3p, vha, 0xb157,
861 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
862 __func__, ha->portnum, lock_owner);
863 return -1;
864 }
865 timeout++;
866 }
867 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
868 return 0;
869 }
870
871 static void
872 qla82xx_rom_unlock(struct qla_hw_data *ha)
873 {
874 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
875 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
876 }
877
878 static int
879 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
880 {
881 long timeout = 0;
882 long done = 0 ;
883 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
884
885 while (done == 0) {
886 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
887 done &= 4;
888 timeout++;
889 if (timeout >= rom_max_timeout) {
890 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
891 "%s: Timeout reached waiting for rom busy.\n",
892 QLA2XXX_DRIVER_NAME);
893 return -1;
894 }
895 }
896 return 0;
897 }
898
899 static int
900 qla82xx_wait_rom_done(struct qla_hw_data *ha)
901 {
902 long timeout = 0;
903 long done = 0 ;
904 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
905
906 while (done == 0) {
907 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
908 done &= 2;
909 timeout++;
910 if (timeout >= rom_max_timeout) {
911 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
912 "%s: Timeout reached waiting for rom done.\n",
913 QLA2XXX_DRIVER_NAME);
914 return -1;
915 }
916 }
917 return 0;
918 }
919
920 static int
921 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
922 {
923 uint32_t off_value, rval = 0;
924
925 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase),
926 (off & 0xFFFF0000));
927
928 /* Read back value to make sure write has gone through */
929 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
930 off_value = (off & 0x0000FFFF);
931
932 if (flag)
933 WRT_REG_DWORD((void __iomem *)
934 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
935 data);
936 else
937 rval = RD_REG_DWORD((void __iomem *)
938 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
939
940 return rval;
941 }
942
943 static int
944 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
945 {
946 /* Dword reads to flash. */
947 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
948 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
949 (addr & 0x0000FFFF), 0, 0);
950
951 return 0;
952 }
953
954 static int
955 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
956 {
957 int ret, loops = 0;
958 uint32_t lock_owner = 0;
959 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
960
961 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
962 udelay(100);
963 schedule();
964 loops++;
965 }
966 if (loops >= 50000) {
967 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
968 ql_log(ql_log_fatal, vha, 0x00b9,
969 "Failed to acquire SEM2 lock, Lock Owner %u.\n",
970 lock_owner);
971 return -1;
972 }
973 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
974 qla82xx_rom_unlock(ha);
975 return ret;
976 }
977
978 static int
979 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
980 {
981 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
982 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
983 qla82xx_wait_rom_busy(ha);
984 if (qla82xx_wait_rom_done(ha)) {
985 ql_log(ql_log_warn, vha, 0xb00c,
986 "Error waiting for rom done.\n");
987 return -1;
988 }
989 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
990 return 0;
991 }
992
993 static int
994 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
995 {
996 long timeout = 0;
997 uint32_t done = 1 ;
998 uint32_t val;
999 int ret = 0;
1000 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1001
1002 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1003 while ((done != 0) && (ret == 0)) {
1004 ret = qla82xx_read_status_reg(ha, &val);
1005 done = val & 1;
1006 timeout++;
1007 udelay(10);
1008 cond_resched();
1009 if (timeout >= 50000) {
1010 ql_log(ql_log_warn, vha, 0xb00d,
1011 "Timeout reached waiting for write finish.\n");
1012 return -1;
1013 }
1014 }
1015 return ret;
1016 }
1017
1018 static int
1019 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1020 {
1021 uint32_t val;
1022 qla82xx_wait_rom_busy(ha);
1023 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1024 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1025 qla82xx_wait_rom_busy(ha);
1026 if (qla82xx_wait_rom_done(ha))
1027 return -1;
1028 if (qla82xx_read_status_reg(ha, &val) != 0)
1029 return -1;
1030 if ((val & 2) != 2)
1031 return -1;
1032 return 0;
1033 }
1034
1035 static int
1036 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1037 {
1038 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1039 if (qla82xx_flash_set_write_enable(ha))
1040 return -1;
1041 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1042 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1043 if (qla82xx_wait_rom_done(ha)) {
1044 ql_log(ql_log_warn, vha, 0xb00e,
1045 "Error waiting for rom done.\n");
1046 return -1;
1047 }
1048 return qla82xx_flash_wait_write_finish(ha);
1049 }
1050
1051 static int
1052 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1053 {
1054 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1055 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1056 if (qla82xx_wait_rom_done(ha)) {
1057 ql_log(ql_log_warn, vha, 0xb00f,
1058 "Error waiting for rom done.\n");
1059 return -1;
1060 }
1061 return 0;
1062 }
1063
1064 static int
1065 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1066 {
1067 int loops = 0;
1068 uint32_t lock_owner = 0;
1069 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1070
1071 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1072 udelay(100);
1073 cond_resched();
1074 loops++;
1075 }
1076 if (loops >= 50000) {
1077 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1078 ql_log(ql_log_warn, vha, 0xb010,
1079 "ROM lock failed, Lock Owner %u.\n", lock_owner);
1080 return -1;
1081 }
1082 return 0;
1083 }
1084
1085 static int
1086 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1087 uint32_t data)
1088 {
1089 int ret = 0;
1090 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1091
1092 ret = ql82xx_rom_lock_d(ha);
1093 if (ret < 0) {
1094 ql_log(ql_log_warn, vha, 0xb011,
1095 "ROM lock failed.\n");
1096 return ret;
1097 }
1098
1099 if (qla82xx_flash_set_write_enable(ha))
1100 goto done_write;
1101
1102 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1103 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1104 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1105 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1106 qla82xx_wait_rom_busy(ha);
1107 if (qla82xx_wait_rom_done(ha)) {
1108 ql_log(ql_log_warn, vha, 0xb012,
1109 "Error waiting for rom done.\n");
1110 ret = -1;
1111 goto done_write;
1112 }
1113
1114 ret = qla82xx_flash_wait_write_finish(ha);
1115
1116 done_write:
1117 qla82xx_rom_unlock(ha);
1118 return ret;
1119 }
1120
1121 /* This routine does CRB initialize sequence
1122 * to put the ISP into operational state
1123 */
1124 static int
1125 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1126 {
1127 int addr, val;
1128 int i ;
1129 struct crb_addr_pair *buf;
1130 unsigned long off;
1131 unsigned offset, n;
1132 struct qla_hw_data *ha = vha->hw;
1133
1134 struct crb_addr_pair {
1135 long addr;
1136 long data;
1137 };
1138
1139 /* Halt all the individual PEGs and other blocks of the ISP */
1140 qla82xx_rom_lock(ha);
1141
1142 /* disable all I2Q */
1143 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1144 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1145 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1146 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1147 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1148 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1149
1150 /* disable all niu interrupts */
1151 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1152 /* disable xge rx/tx */
1153 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1154 /* disable xg1 rx/tx */
1155 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1156 /* disable sideband mac */
1157 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1158 /* disable ap0 mac */
1159 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1160 /* disable ap1 mac */
1161 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1162
1163 /* halt sre */
1164 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1165 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1166
1167 /* halt epg */
1168 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1169
1170 /* halt timers */
1171 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1172 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1173 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1174 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1175 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1176 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1177
1178 /* halt pegs */
1179 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1180 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1181 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1182 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1183 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1184 msleep(20);
1185
1186 /* big hammer */
1187 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1188 /* don't reset CAM block on reset */
1189 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1190 else
1191 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1192 qla82xx_rom_unlock(ha);
1193
1194 /* Read the signature value from the flash.
1195 * Offset 0: Contain signature (0xcafecafe)
1196 * Offset 4: Offset and number of addr/value pairs
1197 * that present in CRB initialize sequence
1198 */
1199 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1200 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1201 ql_log(ql_log_fatal, vha, 0x006e,
1202 "Error Reading crb_init area: n: %08x.\n", n);
1203 return -1;
1204 }
1205
1206 /* Offset in flash = lower 16 bits
1207 * Number of entries = upper 16 bits
1208 */
1209 offset = n & 0xffffU;
1210 n = (n >> 16) & 0xffffU;
1211
1212 /* number of addr/value pair should not exceed 1024 entries */
1213 if (n >= 1024) {
1214 ql_log(ql_log_fatal, vha, 0x0071,
1215 "Card flash not initialized:n=0x%x.\n", n);
1216 return -1;
1217 }
1218
1219 ql_log(ql_log_info, vha, 0x0072,
1220 "%d CRB init values found in ROM.\n", n);
1221
1222 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1223 if (buf == NULL) {
1224 ql_log(ql_log_fatal, vha, 0x010c,
1225 "Unable to allocate memory.\n");
1226 return -1;
1227 }
1228
1229 for (i = 0; i < n; i++) {
1230 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1231 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1232 kfree(buf);
1233 return -1;
1234 }
1235
1236 buf[i].addr = addr;
1237 buf[i].data = val;
1238 }
1239
1240 for (i = 0; i < n; i++) {
1241 /* Translate internal CRB initialization
1242 * address to PCI bus address
1243 */
1244 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1245 QLA82XX_PCI_CRBSPACE;
1246 /* Not all CRB addr/value pair to be written,
1247 * some of them are skipped
1248 */
1249
1250 /* skipping cold reboot MAGIC */
1251 if (off == QLA82XX_CAM_RAM(0x1fc))
1252 continue;
1253
1254 /* do not reset PCI */
1255 if (off == (ROMUSB_GLB + 0xbc))
1256 continue;
1257
1258 /* skip core clock, so that firmware can increase the clock */
1259 if (off == (ROMUSB_GLB + 0xc8))
1260 continue;
1261
1262 /* skip the function enable register */
1263 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1264 continue;
1265
1266 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1267 continue;
1268
1269 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1270 continue;
1271
1272 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1273 continue;
1274
1275 if (off == ADDR_ERROR) {
1276 ql_log(ql_log_fatal, vha, 0x0116,
1277 "Unknow addr: 0x%08lx.\n", buf[i].addr);
1278 continue;
1279 }
1280
1281 qla82xx_wr_32(ha, off, buf[i].data);
1282
1283 /* ISP requires much bigger delay to settle down,
1284 * else crb_window returns 0xffffffff
1285 */
1286 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1287 msleep(1000);
1288
1289 /* ISP requires millisec delay between
1290 * successive CRB register updation
1291 */
1292 msleep(1);
1293 }
1294
1295 kfree(buf);
1296
1297 /* Resetting the data and instruction cache */
1298 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1299 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1300 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1301
1302 /* Clear all protocol processing engines */
1303 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1304 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1305 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1306 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1307 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1308 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1309 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1310 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1311 return 0;
1312 }
1313
1314 static int
1315 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1316 u64 off, void *data, int size)
1317 {
1318 int i, j, ret = 0, loop, sz[2], off0;
1319 int scale, shift_amount, startword;
1320 uint32_t temp;
1321 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1322
1323 /*
1324 * If not MN, go check for MS or invalid.
1325 */
1326 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1327 mem_crb = QLA82XX_CRB_QDR_NET;
1328 else {
1329 mem_crb = QLA82XX_CRB_DDR_NET;
1330 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1331 return qla82xx_pci_mem_write_direct(ha,
1332 off, data, size);
1333 }
1334
1335 off0 = off & 0x7;
1336 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1337 sz[1] = size - sz[0];
1338
1339 off8 = off & 0xfffffff0;
1340 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1341 shift_amount = 4;
1342 scale = 2;
1343 startword = (off & 0xf)/8;
1344
1345 for (i = 0; i < loop; i++) {
1346 if (qla82xx_pci_mem_read_2M(ha, off8 +
1347 (i << shift_amount), &word[i * scale], 8))
1348 return -1;
1349 }
1350
1351 switch (size) {
1352 case 1:
1353 tmpw = *((uint8_t *)data);
1354 break;
1355 case 2:
1356 tmpw = *((uint16_t *)data);
1357 break;
1358 case 4:
1359 tmpw = *((uint32_t *)data);
1360 break;
1361 case 8:
1362 default:
1363 tmpw = *((uint64_t *)data);
1364 break;
1365 }
1366
1367 if (sz[0] == 8) {
1368 word[startword] = tmpw;
1369 } else {
1370 word[startword] &=
1371 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1372 word[startword] |= tmpw << (off0 * 8);
1373 }
1374 if (sz[1] != 0) {
1375 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1376 word[startword+1] |= tmpw >> (sz[0] * 8);
1377 }
1378
1379 for (i = 0; i < loop; i++) {
1380 temp = off8 + (i << shift_amount);
1381 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1382 temp = 0;
1383 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1384 temp = word[i * scale] & 0xffffffff;
1385 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1386 temp = (word[i * scale] >> 32) & 0xffffffff;
1387 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1388 temp = word[i*scale + 1] & 0xffffffff;
1389 qla82xx_wr_32(ha, mem_crb +
1390 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1391 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1392 qla82xx_wr_32(ha, mem_crb +
1393 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1394
1395 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1396 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1397 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1398 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1399
1400 for (j = 0; j < MAX_CTL_CHECK; j++) {
1401 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1402 if ((temp & MIU_TA_CTL_BUSY) == 0)
1403 break;
1404 }
1405
1406 if (j >= MAX_CTL_CHECK) {
1407 if (printk_ratelimit())
1408 dev_err(&ha->pdev->dev,
1409 "failed to write through agent.\n");
1410 ret = -1;
1411 break;
1412 }
1413 }
1414
1415 return ret;
1416 }
1417
1418 static int
1419 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1420 {
1421 int i;
1422 long size = 0;
1423 long flashaddr = ha->flt_region_bootload << 2;
1424 long memaddr = BOOTLD_START;
1425 u64 data;
1426 u32 high, low;
1427 size = (IMAGE_START - BOOTLD_START) / 8;
1428
1429 for (i = 0; i < size; i++) {
1430 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1431 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1432 return -1;
1433 }
1434 data = ((u64)high << 32) | low ;
1435 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1436 flashaddr += 8;
1437 memaddr += 8;
1438
1439 if (i % 0x1000 == 0)
1440 msleep(1);
1441 }
1442 udelay(100);
1443 read_lock(&ha->hw_lock);
1444 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1445 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1446 read_unlock(&ha->hw_lock);
1447 return 0;
1448 }
1449
1450 int
1451 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1452 u64 off, void *data, int size)
1453 {
1454 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1455 int shift_amount;
1456 uint32_t temp;
1457 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1458
1459 /*
1460 * If not MN, go check for MS or invalid.
1461 */
1462
1463 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1464 mem_crb = QLA82XX_CRB_QDR_NET;
1465 else {
1466 mem_crb = QLA82XX_CRB_DDR_NET;
1467 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1468 return qla82xx_pci_mem_read_direct(ha,
1469 off, data, size);
1470 }
1471
1472 off8 = off & 0xfffffff0;
1473 off0[0] = off & 0xf;
1474 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1475 shift_amount = 4;
1476 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1477 off0[1] = 0;
1478 sz[1] = size - sz[0];
1479
1480 for (i = 0; i < loop; i++) {
1481 temp = off8 + (i << shift_amount);
1482 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1483 temp = 0;
1484 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1485 temp = MIU_TA_CTL_ENABLE;
1486 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1487 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1488 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1489
1490 for (j = 0; j < MAX_CTL_CHECK; j++) {
1491 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1492 if ((temp & MIU_TA_CTL_BUSY) == 0)
1493 break;
1494 }
1495
1496 if (j >= MAX_CTL_CHECK) {
1497 if (printk_ratelimit())
1498 dev_err(&ha->pdev->dev,
1499 "failed to read through agent.\n");
1500 break;
1501 }
1502
1503 start = off0[i] >> 2;
1504 end = (off0[i] + sz[i] - 1) >> 2;
1505 for (k = start; k <= end; k++) {
1506 temp = qla82xx_rd_32(ha,
1507 mem_crb + MIU_TEST_AGT_RDDATA(k));
1508 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1509 }
1510 }
1511
1512 if (j >= MAX_CTL_CHECK)
1513 return -1;
1514
1515 if ((off0[0] & 7) == 0) {
1516 val = word[0];
1517 } else {
1518 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1519 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1520 }
1521
1522 switch (size) {
1523 case 1:
1524 *(uint8_t *)data = val;
1525 break;
1526 case 2:
1527 *(uint16_t *)data = val;
1528 break;
1529 case 4:
1530 *(uint32_t *)data = val;
1531 break;
1532 case 8:
1533 *(uint64_t *)data = val;
1534 break;
1535 }
1536 return 0;
1537 }
1538
1539
1540 static struct qla82xx_uri_table_desc *
1541 qla82xx_get_table_desc(const u8 *unirom, int section)
1542 {
1543 uint32_t i;
1544 struct qla82xx_uri_table_desc *directory =
1545 (struct qla82xx_uri_table_desc *)&unirom[0];
1546 __le32 offset;
1547 __le32 tab_type;
1548 __le32 entries = cpu_to_le32(directory->num_entries);
1549
1550 for (i = 0; i < entries; i++) {
1551 offset = cpu_to_le32(directory->findex) +
1552 (i * cpu_to_le32(directory->entry_size));
1553 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1554
1555 if (tab_type == section)
1556 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1557 }
1558
1559 return NULL;
1560 }
1561
1562 static struct qla82xx_uri_data_desc *
1563 qla82xx_get_data_desc(struct qla_hw_data *ha,
1564 u32 section, u32 idx_offset)
1565 {
1566 const u8 *unirom = ha->hablob->fw->data;
1567 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1568 struct qla82xx_uri_table_desc *tab_desc = NULL;
1569 __le32 offset;
1570
1571 tab_desc = qla82xx_get_table_desc(unirom, section);
1572 if (!tab_desc)
1573 return NULL;
1574
1575 offset = cpu_to_le32(tab_desc->findex) +
1576 (cpu_to_le32(tab_desc->entry_size) * idx);
1577
1578 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1579 }
1580
1581 static u8 *
1582 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1583 {
1584 u32 offset = BOOTLD_START;
1585 struct qla82xx_uri_data_desc *uri_desc = NULL;
1586
1587 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1588 uri_desc = qla82xx_get_data_desc(ha,
1589 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1590 if (uri_desc)
1591 offset = cpu_to_le32(uri_desc->findex);
1592 }
1593
1594 return (u8 *)&ha->hablob->fw->data[offset];
1595 }
1596
1597 static __le32
1598 qla82xx_get_fw_size(struct qla_hw_data *ha)
1599 {
1600 struct qla82xx_uri_data_desc *uri_desc = NULL;
1601
1602 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1603 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1604 QLA82XX_URI_FIRMWARE_IDX_OFF);
1605 if (uri_desc)
1606 return cpu_to_le32(uri_desc->size);
1607 }
1608
1609 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1610 }
1611
1612 static u8 *
1613 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1614 {
1615 u32 offset = IMAGE_START;
1616 struct qla82xx_uri_data_desc *uri_desc = NULL;
1617
1618 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1619 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1620 QLA82XX_URI_FIRMWARE_IDX_OFF);
1621 if (uri_desc)
1622 offset = cpu_to_le32(uri_desc->findex);
1623 }
1624
1625 return (u8 *)&ha->hablob->fw->data[offset];
1626 }
1627
1628 /* PCI related functions */
1629 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1630 {
1631 unsigned long val = 0;
1632 u32 control;
1633
1634 switch (region) {
1635 case 0:
1636 val = 0;
1637 break;
1638 case 1:
1639 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1640 val = control + QLA82XX_MSIX_TBL_SPACE;
1641 break;
1642 }
1643 return val;
1644 }
1645
1646
1647 int
1648 qla82xx_iospace_config(struct qla_hw_data *ha)
1649 {
1650 uint32_t len = 0;
1651
1652 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1653 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1654 "Failed to reserver selected regions.\n");
1655 goto iospace_error_exit;
1656 }
1657
1658 /* Use MMIO operations for all accesses. */
1659 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1660 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1661 "Region #0 not an MMIO resource, aborting.\n");
1662 goto iospace_error_exit;
1663 }
1664
1665 len = pci_resource_len(ha->pdev, 0);
1666 ha->nx_pcibase =
1667 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1668 if (!ha->nx_pcibase) {
1669 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1670 "Cannot remap pcibase MMIO, aborting.\n");
1671 goto iospace_error_exit;
1672 }
1673
1674 /* Mapping of IO base pointer */
1675 if (IS_QLA8044(ha)) {
1676 ha->iobase =
1677 (device_reg_t *)((uint8_t *)ha->nx_pcibase);
1678 } else if (IS_QLA82XX(ha)) {
1679 ha->iobase =
1680 (device_reg_t *)((uint8_t *)ha->nx_pcibase +
1681 0xbc000 + (ha->pdev->devfn << 11));
1682 }
1683
1684 if (!ql2xdbwr) {
1685 ha->nxdb_wr_ptr =
1686 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1687 (ha->pdev->devfn << 12)), 4);
1688 if (!ha->nxdb_wr_ptr) {
1689 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1690 "Cannot remap MMIO, aborting.\n");
1691 goto iospace_error_exit;
1692 }
1693
1694 /* Mapping of IO base pointer,
1695 * door bell read and write pointer
1696 */
1697 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
1698 (ha->pdev->devfn * 8);
1699 } else {
1700 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
1701 QLA82XX_CAMRAM_DB1 :
1702 QLA82XX_CAMRAM_DB2);
1703 }
1704
1705 ha->max_req_queues = ha->max_rsp_queues = 1;
1706 ha->msix_count = ha->max_rsp_queues + 1;
1707 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1708 "nx_pci_base=%p iobase=%p "
1709 "max_req_queues=%d msix_count=%d.\n",
1710 (void *)ha->nx_pcibase, ha->iobase,
1711 ha->max_req_queues, ha->msix_count);
1712 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1713 "nx_pci_base=%p iobase=%p "
1714 "max_req_queues=%d msix_count=%d.\n",
1715 (void *)ha->nx_pcibase, ha->iobase,
1716 ha->max_req_queues, ha->msix_count);
1717 return 0;
1718
1719 iospace_error_exit:
1720 return -ENOMEM;
1721 }
1722
1723 /* GS related functions */
1724
1725 /* Initialization related functions */
1726
1727 /**
1728 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1729 * @ha: HA context
1730 *
1731 * Returns 0 on success.
1732 */
1733 int
1734 qla82xx_pci_config(scsi_qla_host_t *vha)
1735 {
1736 struct qla_hw_data *ha = vha->hw;
1737 int ret;
1738
1739 pci_set_master(ha->pdev);
1740 ret = pci_set_mwi(ha->pdev);
1741 ha->chip_revision = ha->pdev->revision;
1742 ql_dbg(ql_dbg_init, vha, 0x0043,
1743 "Chip revision:%d.\n",
1744 ha->chip_revision);
1745 return 0;
1746 }
1747
1748 /**
1749 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1750 * @ha: HA context
1751 *
1752 * Returns 0 on success.
1753 */
1754 void
1755 qla82xx_reset_chip(scsi_qla_host_t *vha)
1756 {
1757 struct qla_hw_data *ha = vha->hw;
1758 ha->isp_ops->disable_intrs(ha);
1759 }
1760
1761 void qla82xx_config_rings(struct scsi_qla_host *vha)
1762 {
1763 struct qla_hw_data *ha = vha->hw;
1764 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1765 struct init_cb_81xx *icb;
1766 struct req_que *req = ha->req_q_map[0];
1767 struct rsp_que *rsp = ha->rsp_q_map[0];
1768
1769 /* Setup ring parameters in initialization control block. */
1770 icb = (struct init_cb_81xx *)ha->init_cb;
1771 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1772 icb->response_q_inpointer = __constant_cpu_to_le16(0);
1773 icb->request_q_length = cpu_to_le16(req->length);
1774 icb->response_q_length = cpu_to_le16(rsp->length);
1775 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1776 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1777 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1778 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1779
1780 WRT_REG_DWORD((unsigned long __iomem *)&reg->req_q_out[0], 0);
1781 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_in[0], 0);
1782 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_out[0], 0);
1783 }
1784
1785 static int
1786 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1787 {
1788 u64 *ptr64;
1789 u32 i, flashaddr, size;
1790 __le64 data;
1791
1792 size = (IMAGE_START - BOOTLD_START) / 8;
1793
1794 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1795 flashaddr = BOOTLD_START;
1796
1797 for (i = 0; i < size; i++) {
1798 data = cpu_to_le64(ptr64[i]);
1799 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1800 return -EIO;
1801 flashaddr += 8;
1802 }
1803
1804 flashaddr = FLASH_ADDR_START;
1805 size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1806 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1807
1808 for (i = 0; i < size; i++) {
1809 data = cpu_to_le64(ptr64[i]);
1810
1811 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1812 return -EIO;
1813 flashaddr += 8;
1814 }
1815 udelay(100);
1816
1817 /* Write a magic value to CAMRAM register
1818 * at a specified offset to indicate
1819 * that all data is written and
1820 * ready for firmware to initialize.
1821 */
1822 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1823
1824 read_lock(&ha->hw_lock);
1825 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1826 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1827 read_unlock(&ha->hw_lock);
1828 return 0;
1829 }
1830
1831 static int
1832 qla82xx_set_product_offset(struct qla_hw_data *ha)
1833 {
1834 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1835 const uint8_t *unirom = ha->hablob->fw->data;
1836 uint32_t i;
1837 __le32 entries;
1838 __le32 flags, file_chiprev, offset;
1839 uint8_t chiprev = ha->chip_revision;
1840 /* Hardcoding mn_present flag for P3P */
1841 int mn_present = 0;
1842 uint32_t flagbit;
1843
1844 ptab_desc = qla82xx_get_table_desc(unirom,
1845 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1846 if (!ptab_desc)
1847 return -1;
1848
1849 entries = cpu_to_le32(ptab_desc->num_entries);
1850
1851 for (i = 0; i < entries; i++) {
1852 offset = cpu_to_le32(ptab_desc->findex) +
1853 (i * cpu_to_le32(ptab_desc->entry_size));
1854 flags = cpu_to_le32(*((int *)&unirom[offset] +
1855 QLA82XX_URI_FLAGS_OFF));
1856 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1857 QLA82XX_URI_CHIP_REV_OFF));
1858
1859 flagbit = mn_present ? 1 : 2;
1860
1861 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1862 ha->file_prd_off = offset;
1863 return 0;
1864 }
1865 }
1866 return -1;
1867 }
1868
1869 static int
1870 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1871 {
1872 __le32 val;
1873 uint32_t min_size;
1874 struct qla_hw_data *ha = vha->hw;
1875 const struct firmware *fw = ha->hablob->fw;
1876
1877 ha->fw_type = fw_type;
1878
1879 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1880 if (qla82xx_set_product_offset(ha))
1881 return -EINVAL;
1882
1883 min_size = QLA82XX_URI_FW_MIN_SIZE;
1884 } else {
1885 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1886 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1887 return -EINVAL;
1888
1889 min_size = QLA82XX_FW_MIN_SIZE;
1890 }
1891
1892 if (fw->size < min_size)
1893 return -EINVAL;
1894 return 0;
1895 }
1896
1897 static int
1898 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1899 {
1900 u32 val = 0;
1901 int retries = 60;
1902 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1903
1904 do {
1905 read_lock(&ha->hw_lock);
1906 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1907 read_unlock(&ha->hw_lock);
1908
1909 switch (val) {
1910 case PHAN_INITIALIZE_COMPLETE:
1911 case PHAN_INITIALIZE_ACK:
1912 return QLA_SUCCESS;
1913 case PHAN_INITIALIZE_FAILED:
1914 break;
1915 default:
1916 break;
1917 }
1918 ql_log(ql_log_info, vha, 0x00a8,
1919 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1920 val, retries);
1921
1922 msleep(500);
1923
1924 } while (--retries);
1925
1926 ql_log(ql_log_fatal, vha, 0x00a9,
1927 "Cmd Peg initialization failed: 0x%x.\n", val);
1928
1929 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1930 read_lock(&ha->hw_lock);
1931 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1932 read_unlock(&ha->hw_lock);
1933 return QLA_FUNCTION_FAILED;
1934 }
1935
1936 static int
1937 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1938 {
1939 u32 val = 0;
1940 int retries = 60;
1941 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1942
1943 do {
1944 read_lock(&ha->hw_lock);
1945 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1946 read_unlock(&ha->hw_lock);
1947
1948 switch (val) {
1949 case PHAN_INITIALIZE_COMPLETE:
1950 case PHAN_INITIALIZE_ACK:
1951 return QLA_SUCCESS;
1952 case PHAN_INITIALIZE_FAILED:
1953 break;
1954 default:
1955 break;
1956 }
1957 ql_log(ql_log_info, vha, 0x00ab,
1958 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1959 val, retries);
1960
1961 msleep(500);
1962
1963 } while (--retries);
1964
1965 ql_log(ql_log_fatal, vha, 0x00ac,
1966 "Rcv Peg initializatin failed: 0x%x.\n", val);
1967 read_lock(&ha->hw_lock);
1968 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1969 read_unlock(&ha->hw_lock);
1970 return QLA_FUNCTION_FAILED;
1971 }
1972
1973 /* ISR related functions */
1974 static struct qla82xx_legacy_intr_set legacy_intr[] = \
1975 QLA82XX_LEGACY_INTR_CONFIG;
1976
1977 /*
1978 * qla82xx_mbx_completion() - Process mailbox command completions.
1979 * @ha: SCSI driver HA context
1980 * @mb0: Mailbox0 register
1981 */
1982 void
1983 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1984 {
1985 uint16_t cnt;
1986 uint16_t __iomem *wptr;
1987 struct qla_hw_data *ha = vha->hw;
1988 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1989 wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
1990
1991 /* Load return mailbox registers. */
1992 ha->flags.mbox_int = 1;
1993 ha->mailbox_out[0] = mb0;
1994
1995 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1996 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
1997 wptr++;
1998 }
1999
2000 if (!ha->mcp)
2001 ql_dbg(ql_dbg_async, vha, 0x5053,
2002 "MBX pointer ERROR.\n");
2003 }
2004
2005 /*
2006 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2007 * @irq:
2008 * @dev_id: SCSI driver HA context
2009 * @regs:
2010 *
2011 * Called by system whenever the host adapter generates an interrupt.
2012 *
2013 * Returns handled flag.
2014 */
2015 irqreturn_t
2016 qla82xx_intr_handler(int irq, void *dev_id)
2017 {
2018 scsi_qla_host_t *vha;
2019 struct qla_hw_data *ha;
2020 struct rsp_que *rsp;
2021 struct device_reg_82xx __iomem *reg;
2022 int status = 0, status1 = 0;
2023 unsigned long flags;
2024 unsigned long iter;
2025 uint32_t stat = 0;
2026 uint16_t mb[4];
2027
2028 rsp = (struct rsp_que *) dev_id;
2029 if (!rsp) {
2030 ql_log(ql_log_info, NULL, 0xb053,
2031 "%s: NULL response queue pointer.\n", __func__);
2032 return IRQ_NONE;
2033 }
2034 ha = rsp->hw;
2035
2036 if (!ha->flags.msi_enabled) {
2037 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2038 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2039 return IRQ_NONE;
2040
2041 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2042 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2043 return IRQ_NONE;
2044 }
2045
2046 /* clear the interrupt */
2047 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2048
2049 /* read twice to ensure write is flushed */
2050 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2051 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2052
2053 reg = &ha->iobase->isp82;
2054
2055 spin_lock_irqsave(&ha->hardware_lock, flags);
2056 vha = pci_get_drvdata(ha->pdev);
2057 for (iter = 1; iter--; ) {
2058
2059 if (RD_REG_DWORD(&reg->host_int)) {
2060 stat = RD_REG_DWORD(&reg->host_status);
2061
2062 switch (stat & 0xff) {
2063 case 0x1:
2064 case 0x2:
2065 case 0x10:
2066 case 0x11:
2067 qla82xx_mbx_completion(vha, MSW(stat));
2068 status |= MBX_INTERRUPT;
2069 break;
2070 case 0x12:
2071 mb[0] = MSW(stat);
2072 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2073 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2074 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2075 qla2x00_async_event(vha, rsp, mb);
2076 break;
2077 case 0x13:
2078 qla24xx_process_response_queue(vha, rsp);
2079 break;
2080 default:
2081 ql_dbg(ql_dbg_async, vha, 0x5054,
2082 "Unrecognized interrupt type (%d).\n",
2083 stat & 0xff);
2084 break;
2085 }
2086 }
2087 WRT_REG_DWORD(&reg->host_int, 0);
2088 }
2089
2090 qla2x00_handle_mbx_completion(ha, status);
2091 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2092
2093 if (!ha->flags.msi_enabled)
2094 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2095
2096 return IRQ_HANDLED;
2097 }
2098
2099 irqreturn_t
2100 qla82xx_msix_default(int irq, void *dev_id)
2101 {
2102 scsi_qla_host_t *vha;
2103 struct qla_hw_data *ha;
2104 struct rsp_que *rsp;
2105 struct device_reg_82xx __iomem *reg;
2106 int status = 0;
2107 unsigned long flags;
2108 uint32_t stat = 0;
2109 uint32_t host_int = 0;
2110 uint16_t mb[4];
2111
2112 rsp = (struct rsp_que *) dev_id;
2113 if (!rsp) {
2114 printk(KERN_INFO
2115 "%s(): NULL response queue pointer.\n", __func__);
2116 return IRQ_NONE;
2117 }
2118 ha = rsp->hw;
2119
2120 reg = &ha->iobase->isp82;
2121
2122 spin_lock_irqsave(&ha->hardware_lock, flags);
2123 vha = pci_get_drvdata(ha->pdev);
2124 do {
2125 host_int = RD_REG_DWORD(&reg->host_int);
2126 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2127 break;
2128 if (host_int) {
2129 stat = RD_REG_DWORD(&reg->host_status);
2130
2131 switch (stat & 0xff) {
2132 case 0x1:
2133 case 0x2:
2134 case 0x10:
2135 case 0x11:
2136 qla82xx_mbx_completion(vha, MSW(stat));
2137 status |= MBX_INTERRUPT;
2138 break;
2139 case 0x12:
2140 mb[0] = MSW(stat);
2141 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2142 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2143 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2144 qla2x00_async_event(vha, rsp, mb);
2145 break;
2146 case 0x13:
2147 qla24xx_process_response_queue(vha, rsp);
2148 break;
2149 default:
2150 ql_dbg(ql_dbg_async, vha, 0x5041,
2151 "Unrecognized interrupt type (%d).\n",
2152 stat & 0xff);
2153 break;
2154 }
2155 }
2156 WRT_REG_DWORD(&reg->host_int, 0);
2157 } while (0);
2158
2159 qla2x00_handle_mbx_completion(ha, status);
2160 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2161
2162 return IRQ_HANDLED;
2163 }
2164
2165 irqreturn_t
2166 qla82xx_msix_rsp_q(int irq, void *dev_id)
2167 {
2168 scsi_qla_host_t *vha;
2169 struct qla_hw_data *ha;
2170 struct rsp_que *rsp;
2171 struct device_reg_82xx __iomem *reg;
2172 unsigned long flags;
2173 uint32_t host_int = 0;
2174
2175 rsp = (struct rsp_que *) dev_id;
2176 if (!rsp) {
2177 printk(KERN_INFO
2178 "%s(): NULL response queue pointer.\n", __func__);
2179 return IRQ_NONE;
2180 }
2181
2182 ha = rsp->hw;
2183 reg = &ha->iobase->isp82;
2184 spin_lock_irqsave(&ha->hardware_lock, flags);
2185 vha = pci_get_drvdata(ha->pdev);
2186 host_int = RD_REG_DWORD(&reg->host_int);
2187 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2188 goto out;
2189 qla24xx_process_response_queue(vha, rsp);
2190 WRT_REG_DWORD(&reg->host_int, 0);
2191 out:
2192 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2193 return IRQ_HANDLED;
2194 }
2195
2196 void
2197 qla82xx_poll(int irq, void *dev_id)
2198 {
2199 scsi_qla_host_t *vha;
2200 struct qla_hw_data *ha;
2201 struct rsp_que *rsp;
2202 struct device_reg_82xx __iomem *reg;
2203 int status = 0;
2204 uint32_t stat;
2205 uint32_t host_int = 0;
2206 uint16_t mb[4];
2207 unsigned long flags;
2208
2209 rsp = (struct rsp_que *) dev_id;
2210 if (!rsp) {
2211 printk(KERN_INFO
2212 "%s(): NULL response queue pointer.\n", __func__);
2213 return;
2214 }
2215 ha = rsp->hw;
2216
2217 reg = &ha->iobase->isp82;
2218 spin_lock_irqsave(&ha->hardware_lock, flags);
2219 vha = pci_get_drvdata(ha->pdev);
2220
2221 host_int = RD_REG_DWORD(&reg->host_int);
2222 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2223 goto out;
2224 if (host_int) {
2225 stat = RD_REG_DWORD(&reg->host_status);
2226 switch (stat & 0xff) {
2227 case 0x1:
2228 case 0x2:
2229 case 0x10:
2230 case 0x11:
2231 qla82xx_mbx_completion(vha, MSW(stat));
2232 status |= MBX_INTERRUPT;
2233 break;
2234 case 0x12:
2235 mb[0] = MSW(stat);
2236 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2237 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2238 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2239 qla2x00_async_event(vha, rsp, mb);
2240 break;
2241 case 0x13:
2242 qla24xx_process_response_queue(vha, rsp);
2243 break;
2244 default:
2245 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2246 "Unrecognized interrupt type (%d).\n",
2247 stat * 0xff);
2248 break;
2249 }
2250 WRT_REG_DWORD(&reg->host_int, 0);
2251 }
2252 out:
2253 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2254 }
2255
2256 void
2257 qla82xx_enable_intrs(struct qla_hw_data *ha)
2258 {
2259 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2260 qla82xx_mbx_intr_enable(vha);
2261 spin_lock_irq(&ha->hardware_lock);
2262 if (IS_QLA8044(ha))
2263 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2264 else
2265 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2266 spin_unlock_irq(&ha->hardware_lock);
2267 ha->interrupts_on = 1;
2268 }
2269
2270 void
2271 qla82xx_disable_intrs(struct qla_hw_data *ha)
2272 {
2273 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2274 qla82xx_mbx_intr_disable(vha);
2275 spin_lock_irq(&ha->hardware_lock);
2276 if (IS_QLA8044(ha))
2277 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2278 else
2279 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2280 spin_unlock_irq(&ha->hardware_lock);
2281 ha->interrupts_on = 0;
2282 }
2283
2284 void qla82xx_init_flags(struct qla_hw_data *ha)
2285 {
2286 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2287
2288 /* ISP 8021 initializations */
2289 rwlock_init(&ha->hw_lock);
2290 ha->qdr_sn_window = -1;
2291 ha->ddr_mn_window = -1;
2292 ha->curr_window = 255;
2293 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2294 nx_legacy_intr = &legacy_intr[ha->portnum];
2295 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2296 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2297 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2298 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2299 }
2300
2301 inline void
2302 qla82xx_set_idc_version(scsi_qla_host_t *vha)
2303 {
2304 int idc_ver;
2305 uint32_t drv_active;
2306 struct qla_hw_data *ha = vha->hw;
2307
2308 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2309 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2310 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2311 QLA82XX_IDC_VERSION);
2312 ql_log(ql_log_info, vha, 0xb082,
2313 "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2314 } else {
2315 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2316 if (idc_ver != QLA82XX_IDC_VERSION)
2317 ql_log(ql_log_info, vha, 0xb083,
2318 "qla2xxx driver IDC version %d is not compatible "
2319 "with IDC version %d of the other drivers\n",
2320 QLA82XX_IDC_VERSION, idc_ver);
2321 }
2322 }
2323
2324 inline void
2325 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2326 {
2327 uint32_t drv_active;
2328 struct qla_hw_data *ha = vha->hw;
2329
2330 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2331
2332 /* If reset value is all FF's, initialize DRV_ACTIVE */
2333 if (drv_active == 0xffffffff) {
2334 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2335 QLA82XX_DRV_NOT_ACTIVE);
2336 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2337 }
2338 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2339 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2340 }
2341
2342 inline void
2343 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2344 {
2345 uint32_t drv_active;
2346
2347 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2348 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2349 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2350 }
2351
2352 static inline int
2353 qla82xx_need_reset(struct qla_hw_data *ha)
2354 {
2355 uint32_t drv_state;
2356 int rval;
2357
2358 if (ha->flags.nic_core_reset_owner)
2359 return 1;
2360 else {
2361 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2362 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2363 return rval;
2364 }
2365 }
2366
2367 static inline void
2368 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2369 {
2370 uint32_t drv_state;
2371 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2372
2373 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2374
2375 /* If reset value is all FF's, initialize DRV_STATE */
2376 if (drv_state == 0xffffffff) {
2377 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2378 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2379 }
2380 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2381 ql_dbg(ql_dbg_init, vha, 0x00bb,
2382 "drv_state = 0x%08x.\n", drv_state);
2383 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2384 }
2385
2386 static inline void
2387 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2388 {
2389 uint32_t drv_state;
2390
2391 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2392 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2393 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2394 }
2395
2396 static inline void
2397 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2398 {
2399 uint32_t qsnt_state;
2400
2401 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2402 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2403 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2404 }
2405
2406 void
2407 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2408 {
2409 struct qla_hw_data *ha = vha->hw;
2410 uint32_t qsnt_state;
2411
2412 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2413 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2414 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2415 }
2416
2417 static int
2418 qla82xx_load_fw(scsi_qla_host_t *vha)
2419 {
2420 int rst;
2421 struct fw_blob *blob;
2422 struct qla_hw_data *ha = vha->hw;
2423
2424 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2425 ql_log(ql_log_fatal, vha, 0x009f,
2426 "Error during CRB initialization.\n");
2427 return QLA_FUNCTION_FAILED;
2428 }
2429 udelay(500);
2430
2431 /* Bring QM and CAMRAM out of reset */
2432 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2433 rst &= ~((1 << 28) | (1 << 24));
2434 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2435
2436 /*
2437 * FW Load priority:
2438 * 1) Operational firmware residing in flash.
2439 * 2) Firmware via request-firmware interface (.bin file).
2440 */
2441 if (ql2xfwloadbin == 2)
2442 goto try_blob_fw;
2443
2444 ql_log(ql_log_info, vha, 0x00a0,
2445 "Attempting to load firmware from flash.\n");
2446
2447 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2448 ql_log(ql_log_info, vha, 0x00a1,
2449 "Firmware loaded successfully from flash.\n");
2450 return QLA_SUCCESS;
2451 } else {
2452 ql_log(ql_log_warn, vha, 0x0108,
2453 "Firmware load from flash failed.\n");
2454 }
2455
2456 try_blob_fw:
2457 ql_log(ql_log_info, vha, 0x00a2,
2458 "Attempting to load firmware from blob.\n");
2459
2460 /* Load firmware blob. */
2461 blob = ha->hablob = qla2x00_request_firmware(vha);
2462 if (!blob) {
2463 ql_log(ql_log_fatal, vha, 0x00a3,
2464 "Firmware image not present.\n");
2465 goto fw_load_failed;
2466 }
2467
2468 /* Validating firmware blob */
2469 if (qla82xx_validate_firmware_blob(vha,
2470 QLA82XX_FLASH_ROMIMAGE)) {
2471 /* Fallback to URI format */
2472 if (qla82xx_validate_firmware_blob(vha,
2473 QLA82XX_UNIFIED_ROMIMAGE)) {
2474 ql_log(ql_log_fatal, vha, 0x00a4,
2475 "No valid firmware image found.\n");
2476 return QLA_FUNCTION_FAILED;
2477 }
2478 }
2479
2480 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2481 ql_log(ql_log_info, vha, 0x00a5,
2482 "Firmware loaded successfully from binary blob.\n");
2483 return QLA_SUCCESS;
2484 } else {
2485 ql_log(ql_log_fatal, vha, 0x00a6,
2486 "Firmware load failed for binary blob.\n");
2487 blob->fw = NULL;
2488 blob = NULL;
2489 goto fw_load_failed;
2490 }
2491 return QLA_SUCCESS;
2492
2493 fw_load_failed:
2494 return QLA_FUNCTION_FAILED;
2495 }
2496
2497 int
2498 qla82xx_start_firmware(scsi_qla_host_t *vha)
2499 {
2500 uint16_t lnk;
2501 struct qla_hw_data *ha = vha->hw;
2502
2503 /* scrub dma mask expansion register */
2504 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2505
2506 /* Put both the PEG CMD and RCV PEG to default state
2507 * of 0 before resetting the hardware
2508 */
2509 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2510 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2511
2512 /* Overwrite stale initialization register values */
2513 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2514 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2515
2516 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2517 ql_log(ql_log_fatal, vha, 0x00a7,
2518 "Error trying to start fw.\n");
2519 return QLA_FUNCTION_FAILED;
2520 }
2521
2522 /* Handshake with the card before we register the devices. */
2523 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2524 ql_log(ql_log_fatal, vha, 0x00aa,
2525 "Error during card handshake.\n");
2526 return QLA_FUNCTION_FAILED;
2527 }
2528
2529 /* Negotiated Link width */
2530 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2531 ha->link_width = (lnk >> 4) & 0x3f;
2532
2533 /* Synchronize with Receive peg */
2534 return qla82xx_check_rcvpeg_state(ha);
2535 }
2536
2537 static uint32_t *
2538 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2539 uint32_t length)
2540 {
2541 uint32_t i;
2542 uint32_t val;
2543 struct qla_hw_data *ha = vha->hw;
2544
2545 /* Dword reads to flash. */
2546 for (i = 0; i < length/4; i++, faddr += 4) {
2547 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2548 ql_log(ql_log_warn, vha, 0x0106,
2549 "Do ROM fast read failed.\n");
2550 goto done_read;
2551 }
2552 dwptr[i] = __constant_cpu_to_le32(val);
2553 }
2554 done_read:
2555 return dwptr;
2556 }
2557
2558 static int
2559 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2560 {
2561 int ret;
2562 uint32_t val;
2563 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2564
2565 ret = ql82xx_rom_lock_d(ha);
2566 if (ret < 0) {
2567 ql_log(ql_log_warn, vha, 0xb014,
2568 "ROM Lock failed.\n");
2569 return ret;
2570 }
2571
2572 ret = qla82xx_read_status_reg(ha, &val);
2573 if (ret < 0)
2574 goto done_unprotect;
2575
2576 val &= ~(BLOCK_PROTECT_BITS << 2);
2577 ret = qla82xx_write_status_reg(ha, val);
2578 if (ret < 0) {
2579 val |= (BLOCK_PROTECT_BITS << 2);
2580 qla82xx_write_status_reg(ha, val);
2581 }
2582
2583 if (qla82xx_write_disable_flash(ha) != 0)
2584 ql_log(ql_log_warn, vha, 0xb015,
2585 "Write disable failed.\n");
2586
2587 done_unprotect:
2588 qla82xx_rom_unlock(ha);
2589 return ret;
2590 }
2591
2592 static int
2593 qla82xx_protect_flash(struct qla_hw_data *ha)
2594 {
2595 int ret;
2596 uint32_t val;
2597 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2598
2599 ret = ql82xx_rom_lock_d(ha);
2600 if (ret < 0) {
2601 ql_log(ql_log_warn, vha, 0xb016,
2602 "ROM Lock failed.\n");
2603 return ret;
2604 }
2605
2606 ret = qla82xx_read_status_reg(ha, &val);
2607 if (ret < 0)
2608 goto done_protect;
2609
2610 val |= (BLOCK_PROTECT_BITS << 2);
2611 /* LOCK all sectors */
2612 ret = qla82xx_write_status_reg(ha, val);
2613 if (ret < 0)
2614 ql_log(ql_log_warn, vha, 0xb017,
2615 "Write status register failed.\n");
2616
2617 if (qla82xx_write_disable_flash(ha) != 0)
2618 ql_log(ql_log_warn, vha, 0xb018,
2619 "Write disable failed.\n");
2620 done_protect:
2621 qla82xx_rom_unlock(ha);
2622 return ret;
2623 }
2624
2625 static int
2626 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2627 {
2628 int ret = 0;
2629 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2630
2631 ret = ql82xx_rom_lock_d(ha);
2632 if (ret < 0) {
2633 ql_log(ql_log_warn, vha, 0xb019,
2634 "ROM Lock failed.\n");
2635 return ret;
2636 }
2637
2638 qla82xx_flash_set_write_enable(ha);
2639 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2640 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2641 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2642
2643 if (qla82xx_wait_rom_done(ha)) {
2644 ql_log(ql_log_warn, vha, 0xb01a,
2645 "Error waiting for rom done.\n");
2646 ret = -1;
2647 goto done;
2648 }
2649 ret = qla82xx_flash_wait_write_finish(ha);
2650 done:
2651 qla82xx_rom_unlock(ha);
2652 return ret;
2653 }
2654
2655 /*
2656 * Address and length are byte address
2657 */
2658 uint8_t *
2659 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2660 uint32_t offset, uint32_t length)
2661 {
2662 scsi_block_requests(vha->host);
2663 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2664 scsi_unblock_requests(vha->host);
2665 return buf;
2666 }
2667
2668 static int
2669 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2670 uint32_t faddr, uint32_t dwords)
2671 {
2672 int ret;
2673 uint32_t liter;
2674 uint32_t sec_mask, rest_addr;
2675 dma_addr_t optrom_dma;
2676 void *optrom = NULL;
2677 int page_mode = 0;
2678 struct qla_hw_data *ha = vha->hw;
2679
2680 ret = -1;
2681
2682 /* Prepare burst-capable write on supported ISPs. */
2683 if (page_mode && !(faddr & 0xfff) &&
2684 dwords > OPTROM_BURST_DWORDS) {
2685 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2686 &optrom_dma, GFP_KERNEL);
2687 if (!optrom) {
2688 ql_log(ql_log_warn, vha, 0xb01b,
2689 "Unable to allocate memory "
2690 "for optrom burst write (%x KB).\n",
2691 OPTROM_BURST_SIZE / 1024);
2692 }
2693 }
2694
2695 rest_addr = ha->fdt_block_size - 1;
2696 sec_mask = ~rest_addr;
2697
2698 ret = qla82xx_unprotect_flash(ha);
2699 if (ret) {
2700 ql_log(ql_log_warn, vha, 0xb01c,
2701 "Unable to unprotect flash for update.\n");
2702 goto write_done;
2703 }
2704
2705 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2706 /* Are we at the beginning of a sector? */
2707 if ((faddr & rest_addr) == 0) {
2708
2709 ret = qla82xx_erase_sector(ha, faddr);
2710 if (ret) {
2711 ql_log(ql_log_warn, vha, 0xb01d,
2712 "Unable to erase sector: address=%x.\n",
2713 faddr);
2714 break;
2715 }
2716 }
2717
2718 /* Go with burst-write. */
2719 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2720 /* Copy data to DMA'ble buffer. */
2721 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2722
2723 ret = qla2x00_load_ram(vha, optrom_dma,
2724 (ha->flash_data_off | faddr),
2725 OPTROM_BURST_DWORDS);
2726 if (ret != QLA_SUCCESS) {
2727 ql_log(ql_log_warn, vha, 0xb01e,
2728 "Unable to burst-write optrom segment "
2729 "(%x/%x/%llx).\n", ret,
2730 (ha->flash_data_off | faddr),
2731 (unsigned long long)optrom_dma);
2732 ql_log(ql_log_warn, vha, 0xb01f,
2733 "Reverting to slow-write.\n");
2734
2735 dma_free_coherent(&ha->pdev->dev,
2736 OPTROM_BURST_SIZE, optrom, optrom_dma);
2737 optrom = NULL;
2738 } else {
2739 liter += OPTROM_BURST_DWORDS - 1;
2740 faddr += OPTROM_BURST_DWORDS - 1;
2741 dwptr += OPTROM_BURST_DWORDS - 1;
2742 continue;
2743 }
2744 }
2745
2746 ret = qla82xx_write_flash_dword(ha, faddr,
2747 cpu_to_le32(*dwptr));
2748 if (ret) {
2749 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2750 "Unable to program flash address=%x data=%x.\n",
2751 faddr, *dwptr);
2752 break;
2753 }
2754 }
2755
2756 ret = qla82xx_protect_flash(ha);
2757 if (ret)
2758 ql_log(ql_log_warn, vha, 0xb021,
2759 "Unable to protect flash after update.\n");
2760 write_done:
2761 if (optrom)
2762 dma_free_coherent(&ha->pdev->dev,
2763 OPTROM_BURST_SIZE, optrom, optrom_dma);
2764 return ret;
2765 }
2766
2767 int
2768 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2769 uint32_t offset, uint32_t length)
2770 {
2771 int rval;
2772
2773 /* Suspend HBA. */
2774 scsi_block_requests(vha->host);
2775 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2776 length >> 2);
2777 scsi_unblock_requests(vha->host);
2778
2779 /* Convert return ISP82xx to generic */
2780 if (rval)
2781 rval = QLA_FUNCTION_FAILED;
2782 else
2783 rval = QLA_SUCCESS;
2784 return rval;
2785 }
2786
2787 void
2788 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2789 {
2790 struct qla_hw_data *ha = vha->hw;
2791 struct req_que *req = ha->req_q_map[0];
2792 struct device_reg_82xx __iomem *reg;
2793 uint32_t dbval;
2794
2795 /* Adjust ring index. */
2796 req->ring_index++;
2797 if (req->ring_index == req->length) {
2798 req->ring_index = 0;
2799 req->ring_ptr = req->ring;
2800 } else
2801 req->ring_ptr++;
2802
2803 reg = &ha->iobase->isp82;
2804 dbval = 0x04 | (ha->portnum << 5);
2805
2806 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2807 if (ql2xdbwr)
2808 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
2809 else {
2810 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
2811 wmb();
2812 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) {
2813 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr,
2814 dbval);
2815 wmb();
2816 }
2817 }
2818 }
2819
2820 static void
2821 qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2822 {
2823 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2824 uint32_t lock_owner = 0;
2825
2826 if (qla82xx_rom_lock(ha)) {
2827 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
2828 /* Someone else is holding the lock. */
2829 ql_log(ql_log_info, vha, 0xb022,
2830 "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2831 }
2832 /*
2833 * Either we got the lock, or someone
2834 * else died while holding it.
2835 * In either case, unlock.
2836 */
2837 qla82xx_rom_unlock(ha);
2838 }
2839
2840 /*
2841 * qla82xx_device_bootstrap
2842 * Initialize device, set DEV_READY, start fw
2843 *
2844 * Note:
2845 * IDC lock must be held upon entry
2846 *
2847 * Return:
2848 * Success : 0
2849 * Failed : 1
2850 */
2851 static int
2852 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2853 {
2854 int rval = QLA_SUCCESS;
2855 int i;
2856 uint32_t old_count, count;
2857 struct qla_hw_data *ha = vha->hw;
2858 int need_reset = 0;
2859
2860 need_reset = qla82xx_need_reset(ha);
2861
2862 if (need_reset) {
2863 /* We are trying to perform a recovery here. */
2864 if (ha->flags.isp82xx_fw_hung)
2865 qla82xx_rom_lock_recovery(ha);
2866 } else {
2867 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2868 for (i = 0; i < 10; i++) {
2869 msleep(200);
2870 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2871 if (count != old_count) {
2872 rval = QLA_SUCCESS;
2873 goto dev_ready;
2874 }
2875 }
2876 qla82xx_rom_lock_recovery(ha);
2877 }
2878
2879 /* set to DEV_INITIALIZING */
2880 ql_log(ql_log_info, vha, 0x009e,
2881 "HW State: INITIALIZING.\n");
2882 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2883
2884 qla82xx_idc_unlock(ha);
2885 rval = qla82xx_start_firmware(vha);
2886 qla82xx_idc_lock(ha);
2887
2888 if (rval != QLA_SUCCESS) {
2889 ql_log(ql_log_fatal, vha, 0x00ad,
2890 "HW State: FAILED.\n");
2891 qla82xx_clear_drv_active(ha);
2892 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2893 return rval;
2894 }
2895
2896 dev_ready:
2897 ql_log(ql_log_info, vha, 0x00ae,
2898 "HW State: READY.\n");
2899 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2900
2901 return QLA_SUCCESS;
2902 }
2903
2904 /*
2905 * qla82xx_need_qsnt_handler
2906 * Code to start quiescence sequence
2907 *
2908 * Note:
2909 * IDC lock must be held upon entry
2910 *
2911 * Return: void
2912 */
2913
2914 static void
2915 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2916 {
2917 struct qla_hw_data *ha = vha->hw;
2918 uint32_t dev_state, drv_state, drv_active;
2919 unsigned long reset_timeout;
2920
2921 if (vha->flags.online) {
2922 /*Block any further I/O and wait for pending cmnds to complete*/
2923 qla2x00_quiesce_io(vha);
2924 }
2925
2926 /* Set the quiescence ready bit */
2927 qla82xx_set_qsnt_ready(ha);
2928
2929 /*wait for 30 secs for other functions to ack */
2930 reset_timeout = jiffies + (30 * HZ);
2931
2932 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2933 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2934 /* Its 2 that is written when qsnt is acked, moving one bit */
2935 drv_active = drv_active << 0x01;
2936
2937 while (drv_state != drv_active) {
2938
2939 if (time_after_eq(jiffies, reset_timeout)) {
2940 /* quiescence timeout, other functions didn't ack
2941 * changing the state to DEV_READY
2942 */
2943 ql_log(ql_log_info, vha, 0xb023,
2944 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2945 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2946 drv_active, drv_state);
2947 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2948 QLA8XXX_DEV_READY);
2949 ql_log(ql_log_info, vha, 0xb025,
2950 "HW State: DEV_READY.\n");
2951 qla82xx_idc_unlock(ha);
2952 qla2x00_perform_loop_resync(vha);
2953 qla82xx_idc_lock(ha);
2954
2955 qla82xx_clear_qsnt_ready(vha);
2956 return;
2957 }
2958
2959 qla82xx_idc_unlock(ha);
2960 msleep(1000);
2961 qla82xx_idc_lock(ha);
2962
2963 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2964 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2965 drv_active = drv_active << 0x01;
2966 }
2967 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2968 /* everyone acked so set the state to DEV_QUIESCENCE */
2969 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2970 ql_log(ql_log_info, vha, 0xb026,
2971 "HW State: DEV_QUIESCENT.\n");
2972 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2973 }
2974 }
2975
2976 /*
2977 * qla82xx_wait_for_state_change
2978 * Wait for device state to change from given current state
2979 *
2980 * Note:
2981 * IDC lock must not be held upon entry
2982 *
2983 * Return:
2984 * Changed device state.
2985 */
2986 uint32_t
2987 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2988 {
2989 struct qla_hw_data *ha = vha->hw;
2990 uint32_t dev_state;
2991
2992 do {
2993 msleep(1000);
2994 qla82xx_idc_lock(ha);
2995 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2996 qla82xx_idc_unlock(ha);
2997 } while (dev_state == curr_state);
2998
2999 return dev_state;
3000 }
3001
3002 void
3003 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
3004 {
3005 struct qla_hw_data *ha = vha->hw;
3006
3007 /* Disable the board */
3008 ql_log(ql_log_fatal, vha, 0x00b8,
3009 "Disabling the board.\n");
3010
3011 if (IS_QLA82XX(ha)) {
3012 qla82xx_clear_drv_active(ha);
3013 qla82xx_idc_unlock(ha);
3014 } else if (IS_QLA8044(ha)) {
3015 qla8044_clear_drv_active(ha);
3016 qla8044_idc_unlock(ha);
3017 }
3018
3019 /* Set DEV_FAILED flag to disable timer */
3020 vha->device_flags |= DFLG_DEV_FAILED;
3021 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3022 qla2x00_mark_all_devices_lost(vha, 0);
3023 vha->flags.online = 0;
3024 vha->flags.init_done = 0;
3025 }
3026
3027 /*
3028 * qla82xx_need_reset_handler
3029 * Code to start reset sequence
3030 *
3031 * Note:
3032 * IDC lock must be held upon entry
3033 *
3034 * Return:
3035 * Success : 0
3036 * Failed : 1
3037 */
3038 static void
3039 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3040 {
3041 uint32_t dev_state, drv_state, drv_active;
3042 uint32_t active_mask = 0;
3043 unsigned long reset_timeout;
3044 struct qla_hw_data *ha = vha->hw;
3045 struct req_que *req = ha->req_q_map[0];
3046
3047 if (vha->flags.online) {
3048 qla82xx_idc_unlock(ha);
3049 qla2x00_abort_isp_cleanup(vha);
3050 ha->isp_ops->get_flash_version(vha, req->ring);
3051 ha->isp_ops->nvram_config(vha);
3052 qla82xx_idc_lock(ha);
3053 }
3054
3055 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3056 if (!ha->flags.nic_core_reset_owner) {
3057 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3058 "reset_acknowledged by 0x%x\n", ha->portnum);
3059 qla82xx_set_rst_ready(ha);
3060 } else {
3061 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3062 drv_active &= active_mask;
3063 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3064 "active_mask: 0x%08x\n", active_mask);
3065 }
3066
3067 /* wait for 10 seconds for reset ack from all functions */
3068 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
3069
3070 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3071 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3072 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3073
3074 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3075 "drv_state: 0x%08x, drv_active: 0x%08x, "
3076 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3077 drv_state, drv_active, dev_state, active_mask);
3078
3079 while (drv_state != drv_active &&
3080 dev_state != QLA8XXX_DEV_INITIALIZING) {
3081 if (time_after_eq(jiffies, reset_timeout)) {
3082 ql_log(ql_log_warn, vha, 0x00b5,
3083 "Reset timeout.\n");
3084 break;
3085 }
3086 qla82xx_idc_unlock(ha);
3087 msleep(1000);
3088 qla82xx_idc_lock(ha);
3089 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3090 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3091 if (ha->flags.nic_core_reset_owner)
3092 drv_active &= active_mask;
3093 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3094 }
3095
3096 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3097 "drv_state: 0x%08x, drv_active: 0x%08x, "
3098 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3099 drv_state, drv_active, dev_state, active_mask);
3100
3101 ql_log(ql_log_info, vha, 0x00b6,
3102 "Device state is 0x%x = %s.\n",
3103 dev_state,
3104 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3105
3106 /* Force to DEV_COLD unless someone else is starting a reset */
3107 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3108 dev_state != QLA8XXX_DEV_COLD) {
3109 ql_log(ql_log_info, vha, 0x00b7,
3110 "HW State: COLD/RE-INIT.\n");
3111 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3112 qla82xx_set_rst_ready(ha);
3113 if (ql2xmdenable) {
3114 if (qla82xx_md_collect(vha))
3115 ql_log(ql_log_warn, vha, 0xb02c,
3116 "Minidump not collected.\n");
3117 } else
3118 ql_log(ql_log_warn, vha, 0xb04f,
3119 "Minidump disabled.\n");
3120 }
3121 }
3122
3123 int
3124 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3125 {
3126 struct qla_hw_data *ha = vha->hw;
3127 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3128 int rval = QLA_SUCCESS;
3129
3130 fw_major_version = ha->fw_major_version;
3131 fw_minor_version = ha->fw_minor_version;
3132 fw_subminor_version = ha->fw_subminor_version;
3133
3134 rval = qla2x00_get_fw_version(vha);
3135 if (rval != QLA_SUCCESS)
3136 return rval;
3137
3138 if (ql2xmdenable) {
3139 if (!ha->fw_dumped) {
3140 if ((fw_major_version != ha->fw_major_version ||
3141 fw_minor_version != ha->fw_minor_version ||
3142 fw_subminor_version != ha->fw_subminor_version) ||
3143 (ha->prev_minidump_failed)) {
3144 ql_dbg(ql_dbg_p3p, vha, 0xb02d,
3145 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
3146 fw_major_version, fw_minor_version,
3147 fw_subminor_version,
3148 ha->fw_major_version,
3149 ha->fw_minor_version,
3150 ha->fw_subminor_version,
3151 ha->prev_minidump_failed);
3152 /* Release MiniDump resources */
3153 qla82xx_md_free(vha);
3154 /* ALlocate MiniDump resources */
3155 qla82xx_md_prep(vha);
3156 }
3157 } else
3158 ql_log(ql_log_info, vha, 0xb02e,
3159 "Firmware dump available to retrieve\n");
3160 }
3161 return rval;
3162 }
3163
3164
3165 static int
3166 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3167 {
3168 uint32_t fw_heartbeat_counter;
3169 int status = 0;
3170
3171 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3172 QLA82XX_PEG_ALIVE_COUNTER);
3173 /* all 0xff, assume AER/EEH in progress, ignore */
3174 if (fw_heartbeat_counter == 0xffffffff) {
3175 ql_dbg(ql_dbg_timer, vha, 0x6003,
3176 "FW heartbeat counter is 0xffffffff, "
3177 "returning status=%d.\n", status);
3178 return status;
3179 }
3180 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3181 vha->seconds_since_last_heartbeat++;
3182 /* FW not alive after 2 seconds */
3183 if (vha->seconds_since_last_heartbeat == 2) {
3184 vha->seconds_since_last_heartbeat = 0;
3185 status = 1;
3186 }
3187 } else
3188 vha->seconds_since_last_heartbeat = 0;
3189 vha->fw_heartbeat_counter = fw_heartbeat_counter;
3190 if (status)
3191 ql_dbg(ql_dbg_timer, vha, 0x6004,
3192 "Returning status=%d.\n", status);
3193 return status;
3194 }
3195
3196 /*
3197 * qla82xx_device_state_handler
3198 * Main state handler
3199 *
3200 * Note:
3201 * IDC lock must be held upon entry
3202 *
3203 * Return:
3204 * Success : 0
3205 * Failed : 1
3206 */
3207 int
3208 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3209 {
3210 uint32_t dev_state;
3211 uint32_t old_dev_state;
3212 int rval = QLA_SUCCESS;
3213 unsigned long dev_init_timeout;
3214 struct qla_hw_data *ha = vha->hw;
3215 int loopcount = 0;
3216
3217 qla82xx_idc_lock(ha);
3218 if (!vha->flags.init_done) {
3219 qla82xx_set_drv_active(vha);
3220 qla82xx_set_idc_version(vha);
3221 }
3222
3223 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3224 old_dev_state = dev_state;
3225 ql_log(ql_log_info, vha, 0x009b,
3226 "Device state is 0x%x = %s.\n",
3227 dev_state,
3228 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3229
3230 /* wait for 30 seconds for device to go ready */
3231 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3232
3233 while (1) {
3234
3235 if (time_after_eq(jiffies, dev_init_timeout)) {
3236 ql_log(ql_log_fatal, vha, 0x009c,
3237 "Device init failed.\n");
3238 rval = QLA_FUNCTION_FAILED;
3239 break;
3240 }
3241 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3242 if (old_dev_state != dev_state) {
3243 loopcount = 0;
3244 old_dev_state = dev_state;
3245 }
3246 if (loopcount < 5) {
3247 ql_log(ql_log_info, vha, 0x009d,
3248 "Device state is 0x%x = %s.\n",
3249 dev_state,
3250 dev_state < MAX_STATES ? qdev_state(dev_state) :
3251 "Unknown");
3252 }
3253
3254 switch (dev_state) {
3255 case QLA8XXX_DEV_READY:
3256 ha->flags.nic_core_reset_owner = 0;
3257 goto rel_lock;
3258 case QLA8XXX_DEV_COLD:
3259 rval = qla82xx_device_bootstrap(vha);
3260 break;
3261 case QLA8XXX_DEV_INITIALIZING:
3262 qla82xx_idc_unlock(ha);
3263 msleep(1000);
3264 qla82xx_idc_lock(ha);
3265 break;
3266 case QLA8XXX_DEV_NEED_RESET:
3267 if (!ql2xdontresethba)
3268 qla82xx_need_reset_handler(vha);
3269 else {
3270 qla82xx_idc_unlock(ha);
3271 msleep(1000);
3272 qla82xx_idc_lock(ha);
3273 }
3274 dev_init_timeout = jiffies +
3275 (ha->fcoe_dev_init_timeout * HZ);
3276 break;
3277 case QLA8XXX_DEV_NEED_QUIESCENT:
3278 qla82xx_need_qsnt_handler(vha);
3279 /* Reset timeout value after quiescence handler */
3280 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3281 * HZ);
3282 break;
3283 case QLA8XXX_DEV_QUIESCENT:
3284 /* Owner will exit and other will wait for the state
3285 * to get changed
3286 */
3287 if (ha->flags.quiesce_owner)
3288 goto rel_lock;
3289
3290 qla82xx_idc_unlock(ha);
3291 msleep(1000);
3292 qla82xx_idc_lock(ha);
3293
3294 /* Reset timeout value after quiescence handler */
3295 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3296 * HZ);
3297 break;
3298 case QLA8XXX_DEV_FAILED:
3299 qla8xxx_dev_failed_handler(vha);
3300 rval = QLA_FUNCTION_FAILED;
3301 goto exit;
3302 default:
3303 qla82xx_idc_unlock(ha);
3304 msleep(1000);
3305 qla82xx_idc_lock(ha);
3306 }
3307 loopcount++;
3308 }
3309 rel_lock:
3310 qla82xx_idc_unlock(ha);
3311 exit:
3312 return rval;
3313 }
3314
3315 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3316 {
3317 uint32_t temp, temp_state, temp_val;
3318 struct qla_hw_data *ha = vha->hw;
3319
3320 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3321 temp_state = qla82xx_get_temp_state(temp);
3322 temp_val = qla82xx_get_temp_val(temp);
3323
3324 if (temp_state == QLA82XX_TEMP_PANIC) {
3325 ql_log(ql_log_warn, vha, 0x600e,
3326 "Device temperature %d degrees C exceeds "
3327 " maximum allowed. Hardware has been shut down.\n",
3328 temp_val);
3329 return 1;
3330 } else if (temp_state == QLA82XX_TEMP_WARN) {
3331 ql_log(ql_log_warn, vha, 0x600f,
3332 "Device temperature %d degrees C exceeds "
3333 "operating range. Immediate action needed.\n",
3334 temp_val);
3335 }
3336 return 0;
3337 }
3338
3339 int qla82xx_read_temperature(scsi_qla_host_t *vha)
3340 {
3341 uint32_t temp;
3342
3343 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3344 return qla82xx_get_temp_val(temp);
3345 }
3346
3347 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3348 {
3349 struct qla_hw_data *ha = vha->hw;
3350
3351 if (ha->flags.mbox_busy) {
3352 ha->flags.mbox_int = 1;
3353 ha->flags.mbox_busy = 0;
3354 ql_log(ql_log_warn, vha, 0x6010,
3355 "Doing premature completion of mbx command.\n");
3356 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3357 complete(&ha->mbx_intr_comp);
3358 }
3359 }
3360
3361 void qla82xx_watchdog(scsi_qla_host_t *vha)
3362 {
3363 uint32_t dev_state, halt_status;
3364 struct qla_hw_data *ha = vha->hw;
3365
3366 /* don't poll if reset is going on */
3367 if (!ha->flags.nic_core_reset_hdlr_active) {
3368 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3369 if (qla82xx_check_temp(vha)) {
3370 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3371 ha->flags.isp82xx_fw_hung = 1;
3372 qla82xx_clear_pending_mbx(vha);
3373 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3374 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3375 ql_log(ql_log_warn, vha, 0x6001,
3376 "Adapter reset needed.\n");
3377 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3378 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3379 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3380 ql_log(ql_log_warn, vha, 0x6002,
3381 "Quiescent needed.\n");
3382 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3383 } else if (dev_state == QLA8XXX_DEV_FAILED &&
3384 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3385 vha->flags.online == 1) {
3386 ql_log(ql_log_warn, vha, 0xb055,
3387 "Adapter state is failed. Offlining.\n");
3388 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3389 ha->flags.isp82xx_fw_hung = 1;
3390 qla82xx_clear_pending_mbx(vha);
3391 } else {
3392 if (qla82xx_check_fw_alive(vha)) {
3393 ql_dbg(ql_dbg_timer, vha, 0x6011,
3394 "disabling pause transmit on port 0 & 1.\n");
3395 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3396 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3397 halt_status = qla82xx_rd_32(ha,
3398 QLA82XX_PEG_HALT_STATUS1);
3399 ql_log(ql_log_info, vha, 0x6005,
3400 "dumping hw/fw registers:.\n "
3401 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3402 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3403 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3404 " PEG_NET_4_PC: 0x%x.\n", halt_status,
3405 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3406 qla82xx_rd_32(ha,
3407 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3408 qla82xx_rd_32(ha,
3409 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3410 qla82xx_rd_32(ha,
3411 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3412 qla82xx_rd_32(ha,
3413 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3414 qla82xx_rd_32(ha,
3415 QLA82XX_CRB_PEG_NET_4 + 0x3c));
3416 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3417 ql_log(ql_log_warn, vha, 0xb052,
3418 "Firmware aborted with "
3419 "error code 0x00006700. Device is "
3420 "being reset.\n");
3421 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3422 set_bit(ISP_UNRECOVERABLE,
3423 &vha->dpc_flags);
3424 } else {
3425 ql_log(ql_log_info, vha, 0x6006,
3426 "Detect abort needed.\n");
3427 set_bit(ISP_ABORT_NEEDED,
3428 &vha->dpc_flags);
3429 }
3430 ha->flags.isp82xx_fw_hung = 1;
3431 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3432 qla82xx_clear_pending_mbx(vha);
3433 }
3434 }
3435 }
3436 }
3437
3438 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3439 {
3440 int rval = -1;
3441 struct qla_hw_data *ha = vha->hw;
3442
3443 if (IS_QLA82XX(ha))
3444 rval = qla82xx_device_state_handler(vha);
3445 else if (IS_QLA8044(ha)) {
3446 qla8044_idc_lock(ha);
3447 /* Decide the reset ownership */
3448 qla83xx_reset_ownership(vha);
3449 qla8044_idc_unlock(ha);
3450 rval = qla8044_device_state_handler(vha);
3451 }
3452 return rval;
3453 }
3454
3455 void
3456 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3457 {
3458 struct qla_hw_data *ha = vha->hw;
3459 uint32_t dev_state = 0;
3460
3461 if (IS_QLA82XX(ha))
3462 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3463 else if (IS_QLA8044(ha))
3464 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3465
3466 if (dev_state == QLA8XXX_DEV_READY) {
3467 ql_log(ql_log_info, vha, 0xb02f,
3468 "HW State: NEED RESET\n");
3469 if (IS_QLA82XX(ha)) {
3470 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3471 QLA8XXX_DEV_NEED_RESET);
3472 ha->flags.nic_core_reset_owner = 1;
3473 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3474 "reset_owner is 0x%x\n", ha->portnum);
3475 } else if (IS_QLA8044(ha))
3476 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3477 QLA8XXX_DEV_NEED_RESET);
3478 } else
3479 ql_log(ql_log_info, vha, 0xb031,
3480 "Device state is 0x%x = %s.\n",
3481 dev_state,
3482 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3483 }
3484
3485 /*
3486 * qla82xx_abort_isp
3487 * Resets ISP and aborts all outstanding commands.
3488 *
3489 * Input:
3490 * ha = adapter block pointer.
3491 *
3492 * Returns:
3493 * 0 = success
3494 */
3495 int
3496 qla82xx_abort_isp(scsi_qla_host_t *vha)
3497 {
3498 int rval = -1;
3499 struct qla_hw_data *ha = vha->hw;
3500
3501 if (vha->device_flags & DFLG_DEV_FAILED) {
3502 ql_log(ql_log_warn, vha, 0x8024,
3503 "Device in failed state, exiting.\n");
3504 return QLA_SUCCESS;
3505 }
3506 ha->flags.nic_core_reset_hdlr_active = 1;
3507
3508 qla82xx_idc_lock(ha);
3509 qla82xx_set_reset_owner(vha);
3510 qla82xx_idc_unlock(ha);
3511
3512 if (IS_QLA82XX(ha))
3513 rval = qla82xx_device_state_handler(vha);
3514 else if (IS_QLA8044(ha)) {
3515 qla8044_idc_lock(ha);
3516 /* Decide the reset ownership */
3517 qla83xx_reset_ownership(vha);
3518 qla8044_idc_unlock(ha);
3519 rval = qla8044_device_state_handler(vha);
3520 }
3521
3522 qla82xx_idc_lock(ha);
3523 qla82xx_clear_rst_ready(ha);
3524 qla82xx_idc_unlock(ha);
3525
3526 if (rval == QLA_SUCCESS) {
3527 ha->flags.isp82xx_fw_hung = 0;
3528 ha->flags.nic_core_reset_hdlr_active = 0;
3529 qla82xx_restart_isp(vha);
3530 }
3531
3532 if (rval) {
3533 vha->flags.online = 1;
3534 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3535 if (ha->isp_abort_cnt == 0) {
3536 ql_log(ql_log_warn, vha, 0x8027,
3537 "ISP error recover failed - board "
3538 "disabled.\n");
3539 /*
3540 * The next call disables the board
3541 * completely.
3542 */
3543 ha->isp_ops->reset_adapter(vha);
3544 vha->flags.online = 0;
3545 clear_bit(ISP_ABORT_RETRY,
3546 &vha->dpc_flags);
3547 rval = QLA_SUCCESS;
3548 } else { /* schedule another ISP abort */
3549 ha->isp_abort_cnt--;
3550 ql_log(ql_log_warn, vha, 0x8036,
3551 "ISP abort - retry remaining %d.\n",
3552 ha->isp_abort_cnt);
3553 rval = QLA_FUNCTION_FAILED;
3554 }
3555 } else {
3556 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3557 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3558 "ISP error recovery - retrying (%d) more times.\n",
3559 ha->isp_abort_cnt);
3560 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3561 rval = QLA_FUNCTION_FAILED;
3562 }
3563 }
3564 return rval;
3565 }
3566
3567 /*
3568 * qla82xx_fcoe_ctx_reset
3569 * Perform a quick reset and aborts all outstanding commands.
3570 * This will only perform an FCoE context reset and avoids a full blown
3571 * chip reset.
3572 *
3573 * Input:
3574 * ha = adapter block pointer.
3575 * is_reset_path = flag for identifying the reset path.
3576 *
3577 * Returns:
3578 * 0 = success
3579 */
3580 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3581 {
3582 int rval = QLA_FUNCTION_FAILED;
3583
3584 if (vha->flags.online) {
3585 /* Abort all outstanding commands, so as to be requeued later */
3586 qla2x00_abort_isp_cleanup(vha);
3587 }
3588
3589 /* Stop currently executing firmware.
3590 * This will destroy existing FCoE context at the F/W end.
3591 */
3592 qla2x00_try_to_stop_firmware(vha);
3593
3594 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3595 rval = qla82xx_restart_isp(vha);
3596
3597 return rval;
3598 }
3599
3600 /*
3601 * qla2x00_wait_for_fcoe_ctx_reset
3602 * Wait till the FCoE context is reset.
3603 *
3604 * Note:
3605 * Does context switching here.
3606 * Release SPIN_LOCK (if any) before calling this routine.
3607 *
3608 * Return:
3609 * Success (fcoe_ctx reset is done) : 0
3610 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3611 */
3612 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3613 {
3614 int status = QLA_FUNCTION_FAILED;
3615 unsigned long wait_reset;
3616
3617 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3618 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3619 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3620 && time_before(jiffies, wait_reset)) {
3621
3622 set_current_state(TASK_UNINTERRUPTIBLE);
3623 schedule_timeout(HZ);
3624
3625 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3626 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3627 status = QLA_SUCCESS;
3628 break;
3629 }
3630 }
3631 ql_dbg(ql_dbg_p3p, vha, 0xb027,
3632 "%s: status=%d.\n", __func__, status);
3633
3634 return status;
3635 }
3636
3637 void
3638 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3639 {
3640 int i, fw_state = 0;
3641 unsigned long flags;
3642 struct qla_hw_data *ha = vha->hw;
3643
3644 /* Check if 82XX firmware is alive or not
3645 * We may have arrived here from NEED_RESET
3646 * detection only
3647 */
3648 if (!ha->flags.isp82xx_fw_hung) {
3649 for (i = 0; i < 2; i++) {
3650 msleep(1000);
3651 if (IS_QLA82XX(ha))
3652 fw_state = qla82xx_check_fw_alive(vha);
3653 else if (IS_QLA8044(ha))
3654 fw_state = qla8044_check_fw_alive(vha);
3655 if (fw_state) {
3656 ha->flags.isp82xx_fw_hung = 1;
3657 qla82xx_clear_pending_mbx(vha);
3658 break;
3659 }
3660 }
3661 }
3662 ql_dbg(ql_dbg_init, vha, 0x00b0,
3663 "Entered %s fw_hung=%d.\n",
3664 __func__, ha->flags.isp82xx_fw_hung);
3665
3666 /* Abort all commands gracefully if fw NOT hung */
3667 if (!ha->flags.isp82xx_fw_hung) {
3668 int cnt, que;
3669 srb_t *sp;
3670 struct req_que *req;
3671
3672 spin_lock_irqsave(&ha->hardware_lock, flags);
3673 for (que = 0; que < ha->max_req_queues; que++) {
3674 req = ha->req_q_map[que];
3675 if (!req)
3676 continue;
3677 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3678 sp = req->outstanding_cmds[cnt];
3679 if (sp) {
3680 if ((!sp->u.scmd.ctx ||
3681 (sp->flags &
3682 SRB_FCP_CMND_DMA_VALID)) &&
3683 !ha->flags.isp82xx_fw_hung) {
3684 spin_unlock_irqrestore(
3685 &ha->hardware_lock, flags);
3686 if (ha->isp_ops->abort_command(sp)) {
3687 ql_log(ql_log_info, vha,
3688 0x00b1,
3689 "mbx abort failed.\n");
3690 } else {
3691 ql_log(ql_log_info, vha,
3692 0x00b2,
3693 "mbx abort success.\n");
3694 }
3695 spin_lock_irqsave(&ha->hardware_lock, flags);
3696 }
3697 }
3698 }
3699 }
3700 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3701
3702 /* Wait for pending cmds (physical and virtual) to complete */
3703 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3704 WAIT_HOST) == QLA_SUCCESS) {
3705 ql_dbg(ql_dbg_init, vha, 0x00b3,
3706 "Done wait for "
3707 "pending commands.\n");
3708 }
3709 }
3710 }
3711
3712 /* Minidump related functions */
3713 static int
3714 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3715 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3716 {
3717 struct qla_hw_data *ha = vha->hw;
3718 struct qla82xx_md_entry_crb *crb_entry;
3719 uint32_t read_value, opcode, poll_time;
3720 uint32_t addr, index, crb_addr;
3721 unsigned long wtime;
3722 struct qla82xx_md_template_hdr *tmplt_hdr;
3723 uint32_t rval = QLA_SUCCESS;
3724 int i;
3725
3726 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3727 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3728 crb_addr = crb_entry->addr;
3729
3730 for (i = 0; i < crb_entry->op_count; i++) {
3731 opcode = crb_entry->crb_ctrl.opcode;
3732 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3733 qla82xx_md_rw_32(ha, crb_addr,
3734 crb_entry->value_1, 1);
3735 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3736 }
3737
3738 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3739 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3740 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3741 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3742 }
3743
3744 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3745 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3746 read_value &= crb_entry->value_2;
3747 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3748 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3749 read_value |= crb_entry->value_3;
3750 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3751 }
3752 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3753 }
3754
3755 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3756 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3757 read_value |= crb_entry->value_3;
3758 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3759 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3760 }
3761
3762 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3763 poll_time = crb_entry->crb_strd.poll_timeout;
3764 wtime = jiffies + poll_time;
3765 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3766
3767 do {
3768 if ((read_value & crb_entry->value_2)
3769 == crb_entry->value_1)
3770 break;
3771 else if (time_after_eq(jiffies, wtime)) {
3772 /* capturing dump failed */
3773 rval = QLA_FUNCTION_FAILED;
3774 break;
3775 } else
3776 read_value = qla82xx_md_rw_32(ha,
3777 crb_addr, 0, 0);
3778 } while (1);
3779 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3780 }
3781
3782 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3783 if (crb_entry->crb_strd.state_index_a) {
3784 index = crb_entry->crb_strd.state_index_a;
3785 addr = tmplt_hdr->saved_state_array[index];
3786 } else
3787 addr = crb_addr;
3788
3789 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3790 index = crb_entry->crb_ctrl.state_index_v;
3791 tmplt_hdr->saved_state_array[index] = read_value;
3792 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3793 }
3794
3795 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3796 if (crb_entry->crb_strd.state_index_a) {
3797 index = crb_entry->crb_strd.state_index_a;
3798 addr = tmplt_hdr->saved_state_array[index];
3799 } else
3800 addr = crb_addr;
3801
3802 if (crb_entry->crb_ctrl.state_index_v) {
3803 index = crb_entry->crb_ctrl.state_index_v;
3804 read_value =
3805 tmplt_hdr->saved_state_array[index];
3806 } else
3807 read_value = crb_entry->value_1;
3808
3809 qla82xx_md_rw_32(ha, addr, read_value, 1);
3810 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3811 }
3812
3813 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3814 index = crb_entry->crb_ctrl.state_index_v;
3815 read_value = tmplt_hdr->saved_state_array[index];
3816 read_value <<= crb_entry->crb_ctrl.shl;
3817 read_value >>= crb_entry->crb_ctrl.shr;
3818 if (crb_entry->value_2)
3819 read_value &= crb_entry->value_2;
3820 read_value |= crb_entry->value_3;
3821 read_value += crb_entry->value_1;
3822 tmplt_hdr->saved_state_array[index] = read_value;
3823 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3824 }
3825 crb_addr += crb_entry->crb_strd.addr_stride;
3826 }
3827 return rval;
3828 }
3829
3830 static void
3831 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3832 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3833 {
3834 struct qla_hw_data *ha = vha->hw;
3835 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3836 struct qla82xx_md_entry_rdocm *ocm_hdr;
3837 uint32_t *data_ptr = *d_ptr;
3838
3839 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3840 r_addr = ocm_hdr->read_addr;
3841 r_stride = ocm_hdr->read_addr_stride;
3842 loop_cnt = ocm_hdr->op_count;
3843
3844 for (i = 0; i < loop_cnt; i++) {
3845 r_value = RD_REG_DWORD((void __iomem *)
3846 (r_addr + ha->nx_pcibase));
3847 *data_ptr++ = cpu_to_le32(r_value);
3848 r_addr += r_stride;
3849 }
3850 *d_ptr = data_ptr;
3851 }
3852
3853 static void
3854 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3855 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3856 {
3857 struct qla_hw_data *ha = vha->hw;
3858 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3859 struct qla82xx_md_entry_mux *mux_hdr;
3860 uint32_t *data_ptr = *d_ptr;
3861
3862 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3863 r_addr = mux_hdr->read_addr;
3864 s_addr = mux_hdr->select_addr;
3865 s_stride = mux_hdr->select_value_stride;
3866 s_value = mux_hdr->select_value;
3867 loop_cnt = mux_hdr->op_count;
3868
3869 for (i = 0; i < loop_cnt; i++) {
3870 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3871 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3872 *data_ptr++ = cpu_to_le32(s_value);
3873 *data_ptr++ = cpu_to_le32(r_value);
3874 s_value += s_stride;
3875 }
3876 *d_ptr = data_ptr;
3877 }
3878
3879 static void
3880 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3881 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3882 {
3883 struct qla_hw_data *ha = vha->hw;
3884 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3885 struct qla82xx_md_entry_crb *crb_hdr;
3886 uint32_t *data_ptr = *d_ptr;
3887
3888 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3889 r_addr = crb_hdr->addr;
3890 r_stride = crb_hdr->crb_strd.addr_stride;
3891 loop_cnt = crb_hdr->op_count;
3892
3893 for (i = 0; i < loop_cnt; i++) {
3894 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3895 *data_ptr++ = cpu_to_le32(r_addr);
3896 *data_ptr++ = cpu_to_le32(r_value);
3897 r_addr += r_stride;
3898 }
3899 *d_ptr = data_ptr;
3900 }
3901
3902 static int
3903 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3904 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3905 {
3906 struct qla_hw_data *ha = vha->hw;
3907 uint32_t addr, r_addr, c_addr, t_r_addr;
3908 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3909 unsigned long p_wait, w_time, p_mask;
3910 uint32_t c_value_w, c_value_r;
3911 struct qla82xx_md_entry_cache *cache_hdr;
3912 int rval = QLA_FUNCTION_FAILED;
3913 uint32_t *data_ptr = *d_ptr;
3914
3915 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3916 loop_count = cache_hdr->op_count;
3917 r_addr = cache_hdr->read_addr;
3918 c_addr = cache_hdr->control_addr;
3919 c_value_w = cache_hdr->cache_ctrl.write_value;
3920
3921 t_r_addr = cache_hdr->tag_reg_addr;
3922 t_value = cache_hdr->addr_ctrl.init_tag_value;
3923 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3924 p_wait = cache_hdr->cache_ctrl.poll_wait;
3925 p_mask = cache_hdr->cache_ctrl.poll_mask;
3926
3927 for (i = 0; i < loop_count; i++) {
3928 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3929 if (c_value_w)
3930 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3931
3932 if (p_mask) {
3933 w_time = jiffies + p_wait;
3934 do {
3935 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3936 if ((c_value_r & p_mask) == 0)
3937 break;
3938 else if (time_after_eq(jiffies, w_time)) {
3939 /* capturing dump failed */
3940 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3941 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3942 "w_time: 0x%lx\n",
3943 c_value_r, p_mask, w_time);
3944 return rval;
3945 }
3946 } while (1);
3947 }
3948
3949 addr = r_addr;
3950 for (k = 0; k < r_cnt; k++) {
3951 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3952 *data_ptr++ = cpu_to_le32(r_value);
3953 addr += cache_hdr->read_ctrl.read_addr_stride;
3954 }
3955 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3956 }
3957 *d_ptr = data_ptr;
3958 return QLA_SUCCESS;
3959 }
3960
3961 static void
3962 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3963 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3964 {
3965 struct qla_hw_data *ha = vha->hw;
3966 uint32_t addr, r_addr, c_addr, t_r_addr;
3967 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3968 uint32_t c_value_w;
3969 struct qla82xx_md_entry_cache *cache_hdr;
3970 uint32_t *data_ptr = *d_ptr;
3971
3972 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3973 loop_count = cache_hdr->op_count;
3974 r_addr = cache_hdr->read_addr;
3975 c_addr = cache_hdr->control_addr;
3976 c_value_w = cache_hdr->cache_ctrl.write_value;
3977
3978 t_r_addr = cache_hdr->tag_reg_addr;
3979 t_value = cache_hdr->addr_ctrl.init_tag_value;
3980 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3981
3982 for (i = 0; i < loop_count; i++) {
3983 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3984 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3985 addr = r_addr;
3986 for (k = 0; k < r_cnt; k++) {
3987 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3988 *data_ptr++ = cpu_to_le32(r_value);
3989 addr += cache_hdr->read_ctrl.read_addr_stride;
3990 }
3991 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3992 }
3993 *d_ptr = data_ptr;
3994 }
3995
3996 static void
3997 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3998 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3999 {
4000 struct qla_hw_data *ha = vha->hw;
4001 uint32_t s_addr, r_addr;
4002 uint32_t r_stride, r_value, r_cnt, qid = 0;
4003 uint32_t i, k, loop_cnt;
4004 struct qla82xx_md_entry_queue *q_hdr;
4005 uint32_t *data_ptr = *d_ptr;
4006
4007 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
4008 s_addr = q_hdr->select_addr;
4009 r_cnt = q_hdr->rd_strd.read_addr_cnt;
4010 r_stride = q_hdr->rd_strd.read_addr_stride;
4011 loop_cnt = q_hdr->op_count;
4012
4013 for (i = 0; i < loop_cnt; i++) {
4014 qla82xx_md_rw_32(ha, s_addr, qid, 1);
4015 r_addr = q_hdr->read_addr;
4016 for (k = 0; k < r_cnt; k++) {
4017 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
4018 *data_ptr++ = cpu_to_le32(r_value);
4019 r_addr += r_stride;
4020 }
4021 qid += q_hdr->q_strd.queue_id_stride;
4022 }
4023 *d_ptr = data_ptr;
4024 }
4025
4026 static void
4027 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
4028 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4029 {
4030 struct qla_hw_data *ha = vha->hw;
4031 uint32_t r_addr, r_value;
4032 uint32_t i, loop_cnt;
4033 struct qla82xx_md_entry_rdrom *rom_hdr;
4034 uint32_t *data_ptr = *d_ptr;
4035
4036 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
4037 r_addr = rom_hdr->read_addr;
4038 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
4039
4040 for (i = 0; i < loop_cnt; i++) {
4041 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4042 (r_addr & 0xFFFF0000), 1);
4043 r_value = qla82xx_md_rw_32(ha,
4044 MD_DIRECT_ROM_READ_BASE +
4045 (r_addr & 0x0000FFFF), 0, 0);
4046 *data_ptr++ = cpu_to_le32(r_value);
4047 r_addr += sizeof(uint32_t);
4048 }
4049 *d_ptr = data_ptr;
4050 }
4051
4052 static int
4053 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4054 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4055 {
4056 struct qla_hw_data *ha = vha->hw;
4057 uint32_t r_addr, r_value, r_data;
4058 uint32_t i, j, loop_cnt;
4059 struct qla82xx_md_entry_rdmem *m_hdr;
4060 unsigned long flags;
4061 int rval = QLA_FUNCTION_FAILED;
4062 uint32_t *data_ptr = *d_ptr;
4063
4064 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4065 r_addr = m_hdr->read_addr;
4066 loop_cnt = m_hdr->read_data_size/16;
4067
4068 if (r_addr & 0xf) {
4069 ql_log(ql_log_warn, vha, 0xb033,
4070 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4071 return rval;
4072 }
4073
4074 if (m_hdr->read_data_size % 16) {
4075 ql_log(ql_log_warn, vha, 0xb034,
4076 "Read data[0x%x] not multiple of 16 bytes\n",
4077 m_hdr->read_data_size);
4078 return rval;
4079 }
4080
4081 ql_dbg(ql_dbg_p3p, vha, 0xb035,
4082 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4083 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4084
4085 write_lock_irqsave(&ha->hw_lock, flags);
4086 for (i = 0; i < loop_cnt; i++) {
4087 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4088 r_value = 0;
4089 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4090 r_value = MIU_TA_CTL_ENABLE;
4091 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4092 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4093 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4094
4095 for (j = 0; j < MAX_CTL_CHECK; j++) {
4096 r_value = qla82xx_md_rw_32(ha,
4097 MD_MIU_TEST_AGT_CTRL, 0, 0);
4098 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4099 break;
4100 }
4101
4102 if (j >= MAX_CTL_CHECK) {
4103 printk_ratelimited(KERN_ERR
4104 "failed to read through agent\n");
4105 write_unlock_irqrestore(&ha->hw_lock, flags);
4106 return rval;
4107 }
4108
4109 for (j = 0; j < 4; j++) {
4110 r_data = qla82xx_md_rw_32(ha,
4111 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4112 *data_ptr++ = cpu_to_le32(r_data);
4113 }
4114 r_addr += 16;
4115 }
4116 write_unlock_irqrestore(&ha->hw_lock, flags);
4117 *d_ptr = data_ptr;
4118 return QLA_SUCCESS;
4119 }
4120
4121 int
4122 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4123 {
4124 struct qla_hw_data *ha = vha->hw;
4125 uint64_t chksum = 0;
4126 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4127 int count = ha->md_template_size/sizeof(uint32_t);
4128
4129 while (count-- > 0)
4130 chksum += *d_ptr++;
4131 while (chksum >> 32)
4132 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4133 return ~chksum;
4134 }
4135
4136 static void
4137 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4138 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4139 {
4140 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4141 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4142 "Skipping entry[%d]: "
4143 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4144 index, entry_hdr->entry_type,
4145 entry_hdr->d_ctrl.entry_capture_mask);
4146 }
4147
4148 int
4149 qla82xx_md_collect(scsi_qla_host_t *vha)
4150 {
4151 struct qla_hw_data *ha = vha->hw;
4152 int no_entry_hdr = 0;
4153 qla82xx_md_entry_hdr_t *entry_hdr;
4154 struct qla82xx_md_template_hdr *tmplt_hdr;
4155 uint32_t *data_ptr;
4156 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4157 int i = 0, rval = QLA_FUNCTION_FAILED;
4158
4159 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4160 data_ptr = (uint32_t *)ha->md_dump;
4161
4162 if (ha->fw_dumped) {
4163 ql_log(ql_log_warn, vha, 0xb037,
4164 "Firmware has been previously dumped (%p) "
4165 "-- ignoring request.\n", ha->fw_dump);
4166 goto md_failed;
4167 }
4168
4169 ha->fw_dumped = 0;
4170
4171 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4172 ql_log(ql_log_warn, vha, 0xb038,
4173 "Memory not allocated for minidump capture\n");
4174 goto md_failed;
4175 }
4176
4177 if (ha->flags.isp82xx_no_md_cap) {
4178 ql_log(ql_log_warn, vha, 0xb054,
4179 "Forced reset from application, "
4180 "ignore minidump capture\n");
4181 ha->flags.isp82xx_no_md_cap = 0;
4182 goto md_failed;
4183 }
4184
4185 if (qla82xx_validate_template_chksum(vha)) {
4186 ql_log(ql_log_info, vha, 0xb039,
4187 "Template checksum validation error\n");
4188 goto md_failed;
4189 }
4190
4191 no_entry_hdr = tmplt_hdr->num_of_entries;
4192 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4193 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4194
4195 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4196 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4197
4198 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4199
4200 /* Validate whether required debug level is set */
4201 if ((f_capture_mask & 0x3) != 0x3) {
4202 ql_log(ql_log_warn, vha, 0xb03c,
4203 "Minimum required capture mask[0x%x] level not set\n",
4204 f_capture_mask);
4205 goto md_failed;
4206 }
4207 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4208
4209 tmplt_hdr->driver_info[0] = vha->host_no;
4210 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4211 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4212 QLA_DRIVER_BETA_VER;
4213
4214 total_data_size = ha->md_dump_size;
4215
4216 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4217 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4218
4219 /* Check whether template obtained is valid */
4220 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4221 ql_log(ql_log_warn, vha, 0xb04e,
4222 "Bad template header entry type: 0x%x obtained\n",
4223 tmplt_hdr->entry_type);
4224 goto md_failed;
4225 }
4226
4227 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4228 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4229
4230 /* Walk through the entry headers */
4231 for (i = 0; i < no_entry_hdr; i++) {
4232
4233 if (data_collected > total_data_size) {
4234 ql_log(ql_log_warn, vha, 0xb03e,
4235 "More MiniDump data collected: [0x%x]\n",
4236 data_collected);
4237 goto md_failed;
4238 }
4239
4240 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4241 ql2xmdcapmask)) {
4242 entry_hdr->d_ctrl.driver_flags |=
4243 QLA82XX_DBG_SKIPPED_FLAG;
4244 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4245 "Skipping entry[%d]: "
4246 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4247 i, entry_hdr->entry_type,
4248 entry_hdr->d_ctrl.entry_capture_mask);
4249 goto skip_nxt_entry;
4250 }
4251
4252 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4253 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4254 "entry_type: 0x%x, captrue_mask: 0x%x\n",
4255 __func__, i, data_ptr, entry_hdr,
4256 entry_hdr->entry_type,
4257 entry_hdr->d_ctrl.entry_capture_mask);
4258
4259 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4260 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4261 data_collected, (ha->md_dump_size - data_collected));
4262
4263 /* Decode the entry type and take
4264 * required action to capture debug data */
4265 switch (entry_hdr->entry_type) {
4266 case QLA82XX_RDEND:
4267 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4268 break;
4269 case QLA82XX_CNTRL:
4270 rval = qla82xx_minidump_process_control(vha,
4271 entry_hdr, &data_ptr);
4272 if (rval != QLA_SUCCESS) {
4273 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4274 goto md_failed;
4275 }
4276 break;
4277 case QLA82XX_RDCRB:
4278 qla82xx_minidump_process_rdcrb(vha,
4279 entry_hdr, &data_ptr);
4280 break;
4281 case QLA82XX_RDMEM:
4282 rval = qla82xx_minidump_process_rdmem(vha,
4283 entry_hdr, &data_ptr);
4284 if (rval != QLA_SUCCESS) {
4285 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4286 goto md_failed;
4287 }
4288 break;
4289 case QLA82XX_BOARD:
4290 case QLA82XX_RDROM:
4291 qla82xx_minidump_process_rdrom(vha,
4292 entry_hdr, &data_ptr);
4293 break;
4294 case QLA82XX_L2DTG:
4295 case QLA82XX_L2ITG:
4296 case QLA82XX_L2DAT:
4297 case QLA82XX_L2INS:
4298 rval = qla82xx_minidump_process_l2tag(vha,
4299 entry_hdr, &data_ptr);
4300 if (rval != QLA_SUCCESS) {
4301 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4302 goto md_failed;
4303 }
4304 break;
4305 case QLA82XX_L1DAT:
4306 case QLA82XX_L1INS:
4307 qla82xx_minidump_process_l1cache(vha,
4308 entry_hdr, &data_ptr);
4309 break;
4310 case QLA82XX_RDOCM:
4311 qla82xx_minidump_process_rdocm(vha,
4312 entry_hdr, &data_ptr);
4313 break;
4314 case QLA82XX_RDMUX:
4315 qla82xx_minidump_process_rdmux(vha,
4316 entry_hdr, &data_ptr);
4317 break;
4318 case QLA82XX_QUEUE:
4319 qla82xx_minidump_process_queue(vha,
4320 entry_hdr, &data_ptr);
4321 break;
4322 case QLA82XX_RDNOP:
4323 default:
4324 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4325 break;
4326 }
4327
4328 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4329 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4330
4331 data_collected = (uint8_t *)data_ptr -
4332 (uint8_t *)ha->md_dump;
4333 skip_nxt_entry:
4334 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4335 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4336 }
4337
4338 if (data_collected != total_data_size) {
4339 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4340 "MiniDump data mismatch: Data collected: [0x%x],"
4341 "total_data_size:[0x%x]\n",
4342 data_collected, total_data_size);
4343 goto md_failed;
4344 }
4345
4346 ql_log(ql_log_info, vha, 0xb044,
4347 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4348 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4349 ha->fw_dumped = 1;
4350 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4351
4352 md_failed:
4353 return rval;
4354 }
4355
4356 int
4357 qla82xx_md_alloc(scsi_qla_host_t *vha)
4358 {
4359 struct qla_hw_data *ha = vha->hw;
4360 int i, k;
4361 struct qla82xx_md_template_hdr *tmplt_hdr;
4362
4363 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4364
4365 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4366 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4367 ql_log(ql_log_info, vha, 0xb045,
4368 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4369 ql2xmdcapmask);
4370 }
4371
4372 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4373 if (i & ql2xmdcapmask)
4374 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4375 }
4376
4377 if (ha->md_dump) {
4378 ql_log(ql_log_warn, vha, 0xb046,
4379 "Firmware dump previously allocated.\n");
4380 return 1;
4381 }
4382
4383 ha->md_dump = vmalloc(ha->md_dump_size);
4384 if (ha->md_dump == NULL) {
4385 ql_log(ql_log_warn, vha, 0xb047,
4386 "Unable to allocate memory for Minidump size "
4387 "(0x%x).\n", ha->md_dump_size);
4388 return 1;
4389 }
4390 return 0;
4391 }
4392
4393 void
4394 qla82xx_md_free(scsi_qla_host_t *vha)
4395 {
4396 struct qla_hw_data *ha = vha->hw;
4397
4398 /* Release the template header allocated */
4399 if (ha->md_tmplt_hdr) {
4400 ql_log(ql_log_info, vha, 0xb048,
4401 "Free MiniDump template: %p, size (%d KB)\n",
4402 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4403 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4404 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4405 ha->md_tmplt_hdr = NULL;
4406 }
4407
4408 /* Release the template data buffer allocated */
4409 if (ha->md_dump) {
4410 ql_log(ql_log_info, vha, 0xb049,
4411 "Free MiniDump memory: %p, size (%d KB)\n",
4412 ha->md_dump, ha->md_dump_size / 1024);
4413 vfree(ha->md_dump);
4414 ha->md_dump_size = 0;
4415 ha->md_dump = NULL;
4416 }
4417 }
4418
4419 void
4420 qla82xx_md_prep(scsi_qla_host_t *vha)
4421 {
4422 struct qla_hw_data *ha = vha->hw;
4423 int rval;
4424
4425 /* Get Minidump template size */
4426 rval = qla82xx_md_get_template_size(vha);
4427 if (rval == QLA_SUCCESS) {
4428 ql_log(ql_log_info, vha, 0xb04a,
4429 "MiniDump Template size obtained (%d KB)\n",
4430 ha->md_template_size / 1024);
4431
4432 /* Get Minidump template */
4433 if (IS_QLA8044(ha))
4434 rval = qla8044_md_get_template(vha);
4435 else
4436 rval = qla82xx_md_get_template(vha);
4437
4438 if (rval == QLA_SUCCESS) {
4439 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4440 "MiniDump Template obtained\n");
4441
4442 /* Allocate memory for minidump */
4443 rval = qla82xx_md_alloc(vha);
4444 if (rval == QLA_SUCCESS)
4445 ql_log(ql_log_info, vha, 0xb04c,
4446 "MiniDump memory allocated (%d KB)\n",
4447 ha->md_dump_size / 1024);
4448 else {
4449 ql_log(ql_log_info, vha, 0xb04d,
4450 "Free MiniDump template: %p, size: (%d KB)\n",
4451 ha->md_tmplt_hdr,
4452 ha->md_template_size / 1024);
4453 dma_free_coherent(&ha->pdev->dev,
4454 ha->md_template_size,
4455 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4456 ha->md_tmplt_hdr = NULL;
4457 }
4458
4459 }
4460 }
4461 }
4462
4463 int
4464 qla82xx_beacon_on(struct scsi_qla_host *vha)
4465 {
4466
4467 int rval;
4468 struct qla_hw_data *ha = vha->hw;
4469 qla82xx_idc_lock(ha);
4470 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4471
4472 if (rval) {
4473 ql_log(ql_log_warn, vha, 0xb050,
4474 "mbx set led config failed in %s\n", __func__);
4475 goto exit;
4476 }
4477 ha->beacon_blink_led = 1;
4478 exit:
4479 qla82xx_idc_unlock(ha);
4480 return rval;
4481 }
4482
4483 int
4484 qla82xx_beacon_off(struct scsi_qla_host *vha)
4485 {
4486
4487 int rval;
4488 struct qla_hw_data *ha = vha->hw;
4489 qla82xx_idc_lock(ha);
4490 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4491
4492 if (rval) {
4493 ql_log(ql_log_warn, vha, 0xb051,
4494 "mbx set led config failed in %s\n", __func__);
4495 goto exit;
4496 }
4497 ha->beacon_blink_led = 0;
4498 exit:
4499 qla82xx_idc_unlock(ha);
4500 return rval;
4501 }
4502
4503 void
4504 qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4505 {
4506 struct qla_hw_data *ha = vha->hw;
4507
4508 if (!ha->allow_cna_fw_dump)
4509 return;
4510
4511 scsi_block_requests(vha->host);
4512 ha->flags.isp82xx_no_md_cap = 1;
4513 qla82xx_idc_lock(ha);
4514 qla82xx_set_reset_owner(vha);
4515 qla82xx_idc_unlock(ha);
4516 qla2x00_wait_for_chip_reset(vha);
4517 scsi_unblock_requests(vha->host);
4518 }
Linux with added FPC-III support