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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / tty / serial / sirfsoc_uart.c
blobb269f6bd16d69f67126d444e79ef154dabbe573e
1 /*
2 * Driver for CSR SiRFprimaII onboard UARTs.
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9 #include <linux/module.h>
10 #include <linux/ioport.h>
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/sysrq.h>
14 #include <linux/console.h>
15 #include <linux/tty.h>
16 #include <linux/tty_flip.h>
17 #include <linux/serial_core.h>
18 #include <linux/serial.h>
19 #include <linux/clk.h>
20 #include <linux/of.h>
21 #include <linux/slab.h>
22 #include <linux/io.h>
23 #include <linux/of_gpio.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-direction.h>
26 #include <linux/dma-mapping.h>
27 #include <asm/irq.h>
28 #include <asm/mach/irq.h>
29
30 #include "sirfsoc_uart.h"
31
32 static unsigned int
33 sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
34 static unsigned int
35 sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
36 static struct uart_driver sirfsoc_uart_drv;
37
38 static void sirfsoc_uart_tx_dma_complete_callback(void *param);
39 static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port);
40 static void sirfsoc_uart_rx_dma_complete_callback(void *param);
41 static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
42 {4000000, 2359296},
43 {3500000, 1310721},
44 {3000000, 1572865},
45 {2500000, 1245186},
46 {2000000, 1572866},
47 {1500000, 1245188},
48 {1152000, 1638404},
49 {1000000, 1572869},
50 {921600, 1114120},
51 {576000, 1245196},
52 {500000, 1245198},
53 {460800, 1572876},
54 {230400, 1310750},
55 {115200, 1310781},
56 {57600, 1310843},
57 {38400, 1114328},
58 {19200, 1114545},
59 {9600, 1114979},
60 };
61
62 static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
63 [0] = {
64 .port = {
65 .iotype = UPIO_MEM,
66 .flags = UPF_BOOT_AUTOCONF,
67 .line = 0,
68 },
69 },
70 [1] = {
71 .port = {
72 .iotype = UPIO_MEM,
73 .flags = UPF_BOOT_AUTOCONF,
74 .line = 1,
75 },
76 },
77 [2] = {
78 .port = {
79 .iotype = UPIO_MEM,
80 .flags = UPF_BOOT_AUTOCONF,
81 .line = 2,
82 },
83 },
84 [3] = {
85 .port = {
86 .iotype = UPIO_MEM,
87 .flags = UPF_BOOT_AUTOCONF,
88 .line = 3,
89 },
90 },
91 [4] = {
92 .port = {
93 .iotype = UPIO_MEM,
94 .flags = UPF_BOOT_AUTOCONF,
95 .line = 4,
96 },
97 },
98 [5] = {
99 .port = {
100 .iotype = UPIO_MEM,
101 .flags = UPF_BOOT_AUTOCONF,
102 .line = 5,
103 },
104 },
105 };
106
107 static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
108 {
109 return container_of(port, struct sirfsoc_uart_port, port);
110 }
111
112 static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
113 {
114 unsigned long reg;
115 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
116 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
117 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
118 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);
119
120 return (reg & ufifo_st->ff_empty(port->line)) ? TIOCSER_TEMT : 0;
121 }
122
123 static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
124 {
125 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
126 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
127 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
128 goto cts_asserted;
129 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
130 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &
131 SIRFUART_AFC_CTS_STATUS))
132 goto cts_asserted;
133 else
134 goto cts_deasserted;
135 } else {
136 if (!gpio_get_value(sirfport->cts_gpio))
137 goto cts_asserted;
138 else
139 goto cts_deasserted;
140 }
141 cts_deasserted:
142 return TIOCM_CAR | TIOCM_DSR;
143 cts_asserted:
144 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
145 }
146
147 static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
148 {
149 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
150 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
151 unsigned int assert = mctrl & TIOCM_RTS;
152 unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
153 unsigned int current_val;
154
155 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
156 return;
157 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
158 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;
159 val |= current_val;
160 wr_regl(port, ureg->sirfsoc_afc_ctrl, val);
161 } else {
162 if (!val)
163 gpio_set_value(sirfport->rts_gpio, 1);
164 else
165 gpio_set_value(sirfport->rts_gpio, 0);
166 }
167 }
168
169 static void sirfsoc_uart_stop_tx(struct uart_port *port)
170 {
171 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
172 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
173 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
174
175 if (sirfport->tx_dma_chan) {
176 if (sirfport->tx_dma_state == TX_DMA_RUNNING) {
177 dmaengine_pause(sirfport->tx_dma_chan);
178 sirfport->tx_dma_state = TX_DMA_PAUSE;
179 } else {
180 if (!sirfport->is_marco)
181 wr_regl(port, ureg->sirfsoc_int_en_reg,
182 rd_regl(port, ureg->sirfsoc_int_en_reg) &
183 ~uint_en->sirfsoc_txfifo_empty_en);
184 else
185 wr_regl(port, SIRFUART_INT_EN_CLR,
186 uint_en->sirfsoc_txfifo_empty_en);
187 }
188 } else {
189 if (!sirfport->is_marco)
190 wr_regl(port, ureg->sirfsoc_int_en_reg,
191 rd_regl(port, ureg->sirfsoc_int_en_reg) &
192 ~uint_en->sirfsoc_txfifo_empty_en);
193 else
194 wr_regl(port, SIRFUART_INT_EN_CLR,
195 uint_en->sirfsoc_txfifo_empty_en);
196 }
197 }
198
199 static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport)
200 {
201 struct uart_port *port = &sirfport->port;
202 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
203 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
204 struct circ_buf *xmit = &port->state->xmit;
205 unsigned long tran_size;
206 unsigned long tran_start;
207 unsigned long pio_tx_size;
208
209 tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
210 tran_start = (unsigned long)(xmit->buf + xmit->tail);
211 if (uart_circ_empty(xmit) || uart_tx_stopped(port) ||
212 !tran_size)
213 return;
214 if (sirfport->tx_dma_state == TX_DMA_PAUSE) {
215 dmaengine_resume(sirfport->tx_dma_chan);
216 return;
217 }
218 if (sirfport->tx_dma_state == TX_DMA_RUNNING)
219 return;
220 if (!sirfport->is_marco)
221 wr_regl(port, ureg->sirfsoc_int_en_reg,
222 rd_regl(port, ureg->sirfsoc_int_en_reg)&
223 ~(uint_en->sirfsoc_txfifo_empty_en));
224 else
225 wr_regl(port, SIRFUART_INT_EN_CLR,
226 uint_en->sirfsoc_txfifo_empty_en);
227 /*
228 * DMA requires buffer address and buffer length are both aligned with
229 * 4 bytes, so we use PIO for
230 * 1. if address is not aligned with 4bytes, use PIO for the first 1~3
231 * bytes, and move to DMA for the left part aligned with 4bytes
232 * 2. if buffer length is not aligned with 4bytes, use DMA for aligned
233 * part first, move to PIO for the left 1~3 bytes
234 */
235 if (tran_size < 4 || BYTES_TO_ALIGN(tran_start)) {
236 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
237 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
238 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)|
239 SIRFUART_IO_MODE);
240 if (BYTES_TO_ALIGN(tran_start)) {
241 pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport,
242 BYTES_TO_ALIGN(tran_start));
243 tran_size -= pio_tx_size;
244 }
245 if (tran_size < 4)
246 sirfsoc_uart_pio_tx_chars(sirfport, tran_size);
247 if (!sirfport->is_marco)
248 wr_regl(port, ureg->sirfsoc_int_en_reg,
249 rd_regl(port, ureg->sirfsoc_int_en_reg)|
250 uint_en->sirfsoc_txfifo_empty_en);
251 else
252 wr_regl(port, ureg->sirfsoc_int_en_reg,
253 uint_en->sirfsoc_txfifo_empty_en);
254 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
255 } else {
256 /* tx transfer mode switch into dma mode */
257 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
258 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
259 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)&
260 ~SIRFUART_IO_MODE);
261 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
262 tran_size &= ~(0x3);
263
264 sirfport->tx_dma_addr = dma_map_single(port->dev,
265 xmit->buf + xmit->tail,
266 tran_size, DMA_TO_DEVICE);
267 sirfport->tx_dma_desc = dmaengine_prep_slave_single(
268 sirfport->tx_dma_chan, sirfport->tx_dma_addr,
269 tran_size, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
270 if (!sirfport->tx_dma_desc) {
271 dev_err(port->dev, "DMA prep slave single fail\n");
272 return;
273 }
274 sirfport->tx_dma_desc->callback =
275 sirfsoc_uart_tx_dma_complete_callback;
276 sirfport->tx_dma_desc->callback_param = (void *)sirfport;
277 sirfport->transfer_size = tran_size;
278
279 dmaengine_submit(sirfport->tx_dma_desc);
280 dma_async_issue_pending(sirfport->tx_dma_chan);
281 sirfport->tx_dma_state = TX_DMA_RUNNING;
282 }
283 }
284
285 static void sirfsoc_uart_start_tx(struct uart_port *port)
286 {
287 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
288 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
289 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
290 if (sirfport->tx_dma_chan)
291 sirfsoc_uart_tx_with_dma(sirfport);
292 else {
293 sirfsoc_uart_pio_tx_chars(sirfport,
294 SIRFSOC_UART_IO_TX_REASONABLE_CNT);
295 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
296 if (!sirfport->is_marco)
297 wr_regl(port, ureg->sirfsoc_int_en_reg,
298 rd_regl(port, ureg->sirfsoc_int_en_reg)|
299 uint_en->sirfsoc_txfifo_empty_en);
300 else
301 wr_regl(port, ureg->sirfsoc_int_en_reg,
302 uint_en->sirfsoc_txfifo_empty_en);
303 }
304 }
305
306 static void sirfsoc_uart_stop_rx(struct uart_port *port)
307 {
308 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
309 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
310 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
311
312 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
313 if (sirfport->rx_dma_chan) {
314 if (!sirfport->is_marco)
315 wr_regl(port, ureg->sirfsoc_int_en_reg,
316 rd_regl(port, ureg->sirfsoc_int_en_reg) &
317 ~(SIRFUART_RX_DMA_INT_EN(port, uint_en) |
318 uint_en->sirfsoc_rx_done_en));
319 else
320 wr_regl(port, SIRFUART_INT_EN_CLR,
321 SIRFUART_RX_DMA_INT_EN(port, uint_en)|
322 uint_en->sirfsoc_rx_done_en);
323 dmaengine_terminate_all(sirfport->rx_dma_chan);
324 } else {
325 if (!sirfport->is_marco)
326 wr_regl(port, ureg->sirfsoc_int_en_reg,
327 rd_regl(port, ureg->sirfsoc_int_en_reg)&
328 ~(SIRFUART_RX_IO_INT_EN(port, uint_en)));
329 else
330 wr_regl(port, SIRFUART_INT_EN_CLR,
331 SIRFUART_RX_IO_INT_EN(port, uint_en));
332 }
333 }
334
335 static void sirfsoc_uart_disable_ms(struct uart_port *port)
336 {
337 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
338 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
339 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
340
341 if (!sirfport->hw_flow_ctrl)
342 return;
343 sirfport->ms_enabled = false;
344 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
345 wr_regl(port, ureg->sirfsoc_afc_ctrl,
346 rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);
347 if (!sirfport->is_marco)
348 wr_regl(port, ureg->sirfsoc_int_en_reg,
349 rd_regl(port, ureg->sirfsoc_int_en_reg)&
350 ~uint_en->sirfsoc_cts_en);
351 else
352 wr_regl(port, SIRFUART_INT_EN_CLR,
353 uint_en->sirfsoc_cts_en);
354 } else
355 disable_irq(gpio_to_irq(sirfport->cts_gpio));
356 }
357
358 static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id)
359 {
360 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
361 struct uart_port *port = &sirfport->port;
362 spin_lock(&port->lock);
363 if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled)
364 uart_handle_cts_change(port,
365 !gpio_get_value(sirfport->cts_gpio));
366 spin_unlock(&port->lock);
367 return IRQ_HANDLED;
368 }
369
370 static void sirfsoc_uart_enable_ms(struct uart_port *port)
371 {
372 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
373 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
374 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
375
376 if (!sirfport->hw_flow_ctrl)
377 return;
378 sirfport->ms_enabled = true;
379 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
380 wr_regl(port, ureg->sirfsoc_afc_ctrl,
381 rd_regl(port, ureg->sirfsoc_afc_ctrl) |
382 SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN);
383 if (!sirfport->is_marco)
384 wr_regl(port, ureg->sirfsoc_int_en_reg,
385 rd_regl(port, ureg->sirfsoc_int_en_reg)
386 | uint_en->sirfsoc_cts_en);
387 else
388 wr_regl(port, ureg->sirfsoc_int_en_reg,
389 uint_en->sirfsoc_cts_en);
390 } else
391 enable_irq(gpio_to_irq(sirfport->cts_gpio));
392 }
393
394 static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
395 {
396 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
397 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
398 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
399 unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);
400 if (break_state)
401 ulcon |= SIRFUART_SET_BREAK;
402 else
403 ulcon &= ~SIRFUART_SET_BREAK;
404 wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon);
405 }
406 }
407
408 static unsigned int
409 sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
410 {
411 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
412 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
413 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
414 unsigned int ch, rx_count = 0;
415 struct tty_struct *tty;
416 tty = tty_port_tty_get(&port->state->port);
417 if (!tty)
418 return -ENODEV;
419 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
420 ufifo_st->ff_empty(port->line))) {
421 ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |
422 SIRFUART_DUMMY_READ;
423 if (unlikely(uart_handle_sysrq_char(port, ch)))
424 continue;
425 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
426 rx_count++;
427 if (rx_count >= max_rx_count)
428 break;
429 }
430
431 sirfport->rx_io_count += rx_count;
432 port->icount.rx += rx_count;
433
434 return rx_count;
435 }
436
437 static unsigned int
438 sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
439 {
440 struct uart_port *port = &sirfport->port;
441 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
442 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
443 struct circ_buf *xmit = &port->state->xmit;
444 unsigned int num_tx = 0;
445 while (!uart_circ_empty(xmit) &&
446 !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
447 ufifo_st->ff_full(port->line)) &&
448 count--) {
449 wr_regl(port, ureg->sirfsoc_tx_fifo_data,
450 xmit->buf[xmit->tail]);
451 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
452 port->icount.tx++;
453 num_tx++;
454 }
455 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
456 uart_write_wakeup(port);
457 return num_tx;
458 }
459
460 static void sirfsoc_uart_tx_dma_complete_callback(void *param)
461 {
462 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
463 struct uart_port *port = &sirfport->port;
464 struct circ_buf *xmit = &port->state->xmit;
465 unsigned long flags;
466
467 spin_lock_irqsave(&port->lock, flags);
468 xmit->tail = (xmit->tail + sirfport->transfer_size) &
469 (UART_XMIT_SIZE - 1);
470 port->icount.tx += sirfport->transfer_size;
471 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
472 uart_write_wakeup(port);
473 if (sirfport->tx_dma_addr)
474 dma_unmap_single(port->dev, sirfport->tx_dma_addr,
475 sirfport->transfer_size, DMA_TO_DEVICE);
476 sirfport->tx_dma_state = TX_DMA_IDLE;
477 sirfsoc_uart_tx_with_dma(sirfport);
478 spin_unlock_irqrestore(&port->lock, flags);
479 }
480
481 static void sirfsoc_uart_insert_rx_buf_to_tty(
482 struct sirfsoc_uart_port *sirfport, int count)
483 {
484 struct uart_port *port = &sirfport->port;
485 struct tty_port *tport = &port->state->port;
486 int inserted;
487
488 inserted = tty_insert_flip_string(tport,
489 sirfport->rx_dma_items[sirfport->rx_completed].xmit.buf, count);
490 port->icount.rx += inserted;
491 }
492
493 static void sirfsoc_rx_submit_one_dma_desc(struct uart_port *port, int index)
494 {
495 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
496
497 sirfport->rx_dma_items[index].xmit.tail =
498 sirfport->rx_dma_items[index].xmit.head = 0;
499 sirfport->rx_dma_items[index].desc =
500 dmaengine_prep_slave_single(sirfport->rx_dma_chan,
501 sirfport->rx_dma_items[index].dma_addr, SIRFSOC_RX_DMA_BUF_SIZE,
502 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
503 if (!sirfport->rx_dma_items[index].desc) {
504 dev_err(port->dev, "DMA slave single fail\n");
505 return;
506 }
507 sirfport->rx_dma_items[index].desc->callback =
508 sirfsoc_uart_rx_dma_complete_callback;
509 sirfport->rx_dma_items[index].desc->callback_param = sirfport;
510 sirfport->rx_dma_items[index].cookie =
511 dmaengine_submit(sirfport->rx_dma_items[index].desc);
512 dma_async_issue_pending(sirfport->rx_dma_chan);
513 }
514
515 static void sirfsoc_rx_tmo_process_tl(unsigned long param)
516 {
517 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
518 struct uart_port *port = &sirfport->port;
519 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
520 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
521 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
522 unsigned int count;
523 unsigned long flags;
524 struct dma_tx_state tx_state;
525
526 spin_lock_irqsave(&port->lock, flags);
527 while (DMA_COMPLETE == dmaengine_tx_status(sirfport->rx_dma_chan,
528 sirfport->rx_dma_items[sirfport->rx_completed].cookie, &tx_state)) {
529 sirfsoc_uart_insert_rx_buf_to_tty(sirfport,
530 SIRFSOC_RX_DMA_BUF_SIZE);
531 sirfport->rx_completed++;
532 sirfport->rx_completed %= SIRFSOC_RX_LOOP_BUF_CNT;
533 }
534 count = CIRC_CNT(sirfport->rx_dma_items[sirfport->rx_issued].xmit.head,
535 sirfport->rx_dma_items[sirfport->rx_issued].xmit.tail,
536 SIRFSOC_RX_DMA_BUF_SIZE);
537 if (count > 0)
538 sirfsoc_uart_insert_rx_buf_to_tty(sirfport, count);
539 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
540 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
541 SIRFUART_IO_MODE);
542 sirfsoc_uart_pio_rx_chars(port, 4 - sirfport->rx_io_count);
543 if (sirfport->rx_io_count == 4) {
544 sirfport->rx_io_count = 0;
545 wr_regl(port, ureg->sirfsoc_int_st_reg,
546 uint_st->sirfsoc_rx_done);
547 if (!sirfport->is_marco)
548 wr_regl(port, ureg->sirfsoc_int_en_reg,
549 rd_regl(port, ureg->sirfsoc_int_en_reg) &
550 ~(uint_en->sirfsoc_rx_done_en));
551 else
552 wr_regl(port, SIRFUART_INT_EN_CLR,
553 uint_en->sirfsoc_rx_done_en);
554 sirfsoc_uart_start_next_rx_dma(port);
555 } else {
556 wr_regl(port, ureg->sirfsoc_int_st_reg,
557 uint_st->sirfsoc_rx_done);
558 if (!sirfport->is_marco)
559 wr_regl(port, ureg->sirfsoc_int_en_reg,
560 rd_regl(port, ureg->sirfsoc_int_en_reg) |
561 (uint_en->sirfsoc_rx_done_en));
562 else
563 wr_regl(port, ureg->sirfsoc_int_en_reg,
564 uint_en->sirfsoc_rx_done_en);
565 }
566 spin_unlock_irqrestore(&port->lock, flags);
567 tty_flip_buffer_push(&port->state->port);
568 }
569
570 static void sirfsoc_uart_handle_rx_tmo(struct sirfsoc_uart_port *sirfport)
571 {
572 struct uart_port *port = &sirfport->port;
573 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
574 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
575 struct dma_tx_state tx_state;
576 dmaengine_tx_status(sirfport->rx_dma_chan,
577 sirfport->rx_dma_items[sirfport->rx_issued].cookie, &tx_state);
578 dmaengine_terminate_all(sirfport->rx_dma_chan);
579 sirfport->rx_dma_items[sirfport->rx_issued].xmit.head =
580 SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue;
581 if (!sirfport->is_marco)
582 wr_regl(port, ureg->sirfsoc_int_en_reg,
583 rd_regl(port, ureg->sirfsoc_int_en_reg) &
584 ~(uint_en->sirfsoc_rx_timeout_en));
585 else
586 wr_regl(port, SIRFUART_INT_EN_CLR,
587 uint_en->sirfsoc_rx_timeout_en);
588 tasklet_schedule(&sirfport->rx_tmo_process_tasklet);
589 }
590
591 static void sirfsoc_uart_handle_rx_done(struct sirfsoc_uart_port *sirfport)
592 {
593 struct uart_port *port = &sirfport->port;
594 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
595 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
596 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
597
598 sirfsoc_uart_pio_rx_chars(port, 4 - sirfport->rx_io_count);
599 if (sirfport->rx_io_count == 4) {
600 sirfport->rx_io_count = 0;
601 if (!sirfport->is_marco)
602 wr_regl(port, ureg->sirfsoc_int_en_reg,
603 rd_regl(port, ureg->sirfsoc_int_en_reg) &
604 ~(uint_en->sirfsoc_rx_done_en));
605 else
606 wr_regl(port, SIRFUART_INT_EN_CLR,
607 uint_en->sirfsoc_rx_done_en);
608 wr_regl(port, ureg->sirfsoc_int_st_reg,
609 uint_st->sirfsoc_rx_timeout);
610 sirfsoc_uart_start_next_rx_dma(port);
611 }
612 }
613
614 static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
615 {
616 unsigned long intr_status;
617 unsigned long cts_status;
618 unsigned long flag = TTY_NORMAL;
619 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
620 struct uart_port *port = &sirfport->port;
621 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
622 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
623 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
624 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
625 struct uart_state *state = port->state;
626 struct circ_buf *xmit = &port->state->xmit;
627 spin_lock(&port->lock);
628 intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
629 wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
630 intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);
631 if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(port, uint_st)))) {
632 if (intr_status & uint_st->sirfsoc_rxd_brk) {
633 port->icount.brk++;
634 if (uart_handle_break(port))
635 goto recv_char;
636 }
637 if (intr_status & uint_st->sirfsoc_rx_oflow)
638 port->icount.overrun++;
639 if (intr_status & uint_st->sirfsoc_frm_err) {
640 port->icount.frame++;
641 flag = TTY_FRAME;
642 }
643 if (intr_status & uint_st->sirfsoc_parity_err)
644 flag = TTY_PARITY;
645 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
646 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
647 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
648 intr_status &= port->read_status_mask;
649 uart_insert_char(port, intr_status,
650 uint_en->sirfsoc_rx_oflow_en, 0, flag);
651 }
652 recv_char:
653 if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
654 (intr_status & SIRFUART_CTS_INT_ST(uint_st)) &&
655 !sirfport->tx_dma_state) {
656 cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
657 SIRFUART_AFC_CTS_STATUS;
658 if (cts_status != 0)
659 cts_status = 0;
660 else
661 cts_status = 1;
662 uart_handle_cts_change(port, cts_status);
663 wake_up_interruptible(&state->port.delta_msr_wait);
664 }
665 if (sirfport->rx_dma_chan) {
666 if (intr_status & uint_st->sirfsoc_rx_timeout)
667 sirfsoc_uart_handle_rx_tmo(sirfport);
668 if (intr_status & uint_st->sirfsoc_rx_done)
669 sirfsoc_uart_handle_rx_done(sirfport);
670 } else {
671 if (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))
672 sirfsoc_uart_pio_rx_chars(port,
673 SIRFSOC_UART_IO_RX_MAX_CNT);
674 }
675 spin_unlock(&port->lock);
676 tty_flip_buffer_push(&state->port);
677 spin_lock(&port->lock);
678 if (intr_status & uint_st->sirfsoc_txfifo_empty) {
679 if (sirfport->tx_dma_chan)
680 sirfsoc_uart_tx_with_dma(sirfport);
681 else {
682 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
683 spin_unlock(&port->lock);
684 return IRQ_HANDLED;
685 } else {
686 sirfsoc_uart_pio_tx_chars(sirfport,
687 SIRFSOC_UART_IO_TX_REASONABLE_CNT);
688 if ((uart_circ_empty(xmit)) &&
689 (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
690 ufifo_st->ff_empty(port->line)))
691 sirfsoc_uart_stop_tx(port);
692 }
693 }
694 }
695 spin_unlock(&port->lock);
696
697 return IRQ_HANDLED;
698 }
699
700 static void sirfsoc_uart_rx_dma_complete_tl(unsigned long param)
701 {
702 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
703 struct uart_port *port = &sirfport->port;
704 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
705 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
706 unsigned long flags;
707 struct dma_tx_state tx_state;
708 spin_lock_irqsave(&port->lock, flags);
709 while (DMA_COMPLETE == dmaengine_tx_status(sirfport->rx_dma_chan,
710 sirfport->rx_dma_items[sirfport->rx_completed].cookie, &tx_state)) {
711 sirfsoc_uart_insert_rx_buf_to_tty(sirfport,
712 SIRFSOC_RX_DMA_BUF_SIZE);
713 if (rd_regl(port, ureg->sirfsoc_int_en_reg) &
714 uint_en->sirfsoc_rx_timeout_en)
715 sirfsoc_rx_submit_one_dma_desc(port,
716 sirfport->rx_completed++);
717 else
718 sirfport->rx_completed++;
719 sirfport->rx_completed %= SIRFSOC_RX_LOOP_BUF_CNT;
720 }
721 spin_unlock_irqrestore(&port->lock, flags);
722 tty_flip_buffer_push(&port->state->port);
723 }
724
725 static void sirfsoc_uart_rx_dma_complete_callback(void *param)
726 {
727 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
728 unsigned long flags;
729
730 spin_lock_irqsave(&sirfport->port.lock, flags);
731 sirfport->rx_issued++;
732 sirfport->rx_issued %= SIRFSOC_RX_LOOP_BUF_CNT;
733 tasklet_schedule(&sirfport->rx_dma_complete_tasklet);
734 spin_unlock_irqrestore(&sirfport->port.lock, flags);
735 }
736
737 /* submit rx dma task into dmaengine */
738 static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port)
739 {
740 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
741 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
742 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
743 int i;
744 sirfport->rx_io_count = 0;
745 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
746 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
747 ~SIRFUART_IO_MODE);
748 for (i = 0; i < SIRFSOC_RX_LOOP_BUF_CNT; i++)
749 sirfsoc_rx_submit_one_dma_desc(port, i);
750 sirfport->rx_completed = sirfport->rx_issued = 0;
751 if (!sirfport->is_marco)
752 wr_regl(port, ureg->sirfsoc_int_en_reg,
753 rd_regl(port, ureg->sirfsoc_int_en_reg) |
754 SIRFUART_RX_DMA_INT_EN(port, uint_en));
755 else
756 wr_regl(port, ureg->sirfsoc_int_en_reg,
757 SIRFUART_RX_DMA_INT_EN(port, uint_en));
758 }
759
760 static void sirfsoc_uart_start_rx(struct uart_port *port)
761 {
762 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
763 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
764 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
765
766 sirfport->rx_io_count = 0;
767 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
768 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
769 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
770 if (sirfport->rx_dma_chan)
771 sirfsoc_uart_start_next_rx_dma(port);
772 else {
773 if (!sirfport->is_marco)
774 wr_regl(port, ureg->sirfsoc_int_en_reg,
775 rd_regl(port, ureg->sirfsoc_int_en_reg) |
776 SIRFUART_RX_IO_INT_EN(port, uint_en));
777 else
778 wr_regl(port, ureg->sirfsoc_int_en_reg,
779 SIRFUART_RX_IO_INT_EN(port, uint_en));
780 }
781 }
782
783 static unsigned int
784 sirfsoc_usp_calc_sample_div(unsigned long set_rate,
785 unsigned long ioclk_rate, unsigned long *sample_reg)
786 {
787 unsigned long min_delta = ~0UL;
788 unsigned short sample_div;
789 unsigned long ioclk_div = 0;
790 unsigned long temp_delta;
791
792 for (sample_div = SIRF_MIN_SAMPLE_DIV;
793 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
794 temp_delta = ioclk_rate -
795 (ioclk_rate + (set_rate * sample_div) / 2)
796 / (set_rate * sample_div) * set_rate * sample_div;
797
798 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
799 if (temp_delta < min_delta) {
800 ioclk_div = (2 * ioclk_rate /
801 (set_rate * sample_div) + 1) / 2 - 1;
802 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
803 continue;
804 min_delta = temp_delta;
805 *sample_reg = sample_div;
806 if (!temp_delta)
807 break;
808 }
809 }
810 return ioclk_div;
811 }
812
813 static unsigned int
814 sirfsoc_uart_calc_sample_div(unsigned long baud_rate,
815 unsigned long ioclk_rate, unsigned long *set_baud)
816 {
817 unsigned long min_delta = ~0UL;
818 unsigned short sample_div;
819 unsigned int regv = 0;
820 unsigned long ioclk_div;
821 unsigned long baud_tmp;
822 int temp_delta;
823
824 for (sample_div = SIRF_MIN_SAMPLE_DIV;
825 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
826 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
827 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
828 continue;
829 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
830 temp_delta = baud_tmp - baud_rate;
831 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
832 if (temp_delta < min_delta) {
833 regv = regv & (~SIRF_IOCLK_DIV_MASK);
834 regv = regv | ioclk_div;
835 regv = regv & (~SIRF_SAMPLE_DIV_MASK);
836 regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
837 min_delta = temp_delta;
838 *set_baud = baud_tmp;
839 }
840 }
841 return regv;
842 }
843
844 static void sirfsoc_uart_set_termios(struct uart_port *port,
845 struct ktermios *termios,
846 struct ktermios *old)
847 {
848 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
849 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
850 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
851 unsigned long config_reg = 0;
852 unsigned long baud_rate;
853 unsigned long set_baud;
854 unsigned long flags;
855 unsigned long ic;
856 unsigned int clk_div_reg = 0;
857 unsigned long txfifo_op_reg, ioclk_rate;
858 unsigned long rx_time_out;
859 int threshold_div;
860 u32 data_bit_len, stop_bit_len, len_val;
861 unsigned long sample_div_reg = 0xf;
862 ioclk_rate = port->uartclk;
863
864 switch (termios->c_cflag & CSIZE) {
865 default:
866 case CS8:
867 data_bit_len = 8;
868 config_reg |= SIRFUART_DATA_BIT_LEN_8;
869 break;
870 case CS7:
871 data_bit_len = 7;
872 config_reg |= SIRFUART_DATA_BIT_LEN_7;
873 break;
874 case CS6:
875 data_bit_len = 6;
876 config_reg |= SIRFUART_DATA_BIT_LEN_6;
877 break;
878 case CS5:
879 data_bit_len = 5;
880 config_reg |= SIRFUART_DATA_BIT_LEN_5;
881 break;
882 }
883 if (termios->c_cflag & CSTOPB) {
884 config_reg |= SIRFUART_STOP_BIT_LEN_2;
885 stop_bit_len = 2;
886 } else
887 stop_bit_len = 1;
888
889 spin_lock_irqsave(&port->lock, flags);
890 port->read_status_mask = uint_en->sirfsoc_rx_oflow_en;
891 port->ignore_status_mask = 0;
892 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
893 if (termios->c_iflag & INPCK)
894 port->read_status_mask |= uint_en->sirfsoc_frm_err_en |
895 uint_en->sirfsoc_parity_err_en;
896 } else {
897 if (termios->c_iflag & INPCK)
898 port->read_status_mask |= uint_en->sirfsoc_frm_err_en;
899 }
900 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
901 port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en;
902 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
903 if (termios->c_iflag & IGNPAR)
904 port->ignore_status_mask |=
905 uint_en->sirfsoc_frm_err_en |
906 uint_en->sirfsoc_parity_err_en;
907 if (termios->c_cflag & PARENB) {
908 if (termios->c_cflag & CMSPAR) {
909 if (termios->c_cflag & PARODD)
910 config_reg |= SIRFUART_STICK_BIT_MARK;
911 else
912 config_reg |= SIRFUART_STICK_BIT_SPACE;
913 } else if (termios->c_cflag & PARODD) {
914 config_reg |= SIRFUART_STICK_BIT_ODD;
915 } else {
916 config_reg |= SIRFUART_STICK_BIT_EVEN;
917 }
918 }
919 } else {
920 if (termios->c_iflag & IGNPAR)
921 port->ignore_status_mask |=
922 uint_en->sirfsoc_frm_err_en;
923 if (termios->c_cflag & PARENB)
924 dev_warn(port->dev,
925 "USP-UART not support parity err\n");
926 }
927 if (termios->c_iflag & IGNBRK) {
928 port->ignore_status_mask |=
929 uint_en->sirfsoc_rxd_brk_en;
930 if (termios->c_iflag & IGNPAR)
931 port->ignore_status_mask |=
932 uint_en->sirfsoc_rx_oflow_en;
933 }
934 if ((termios->c_cflag & CREAD) == 0)
935 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
936 /* Hardware Flow Control Settings */
937 if (UART_ENABLE_MS(port, termios->c_cflag)) {
938 if (!sirfport->ms_enabled)
939 sirfsoc_uart_enable_ms(port);
940 } else {
941 if (sirfport->ms_enabled)
942 sirfsoc_uart_disable_ms(port);
943 }
944 baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
945 if (ioclk_rate == 150000000) {
946 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
947 if (baud_rate == baudrate_to_regv[ic].baud_rate)
948 clk_div_reg = baudrate_to_regv[ic].reg_val;
949 }
950 set_baud = baud_rate;
951 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
952 if (unlikely(clk_div_reg == 0))
953 clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate,
954 ioclk_rate, &set_baud);
955 wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg);
956 } else {
957 clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate,
958 ioclk_rate, &sample_div_reg);
959 sample_div_reg--;
960 set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) /
961 (sample_div_reg + 1));
962 /* setting usp mode 2 */
963 len_val = ((1 << SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET) |
964 (1 << SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET));
965 len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK)
966 << SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET);
967 wr_regl(port, ureg->sirfsoc_mode2, len_val);
968 }
969 if (tty_termios_baud_rate(termios))
970 tty_termios_encode_baud_rate(termios, set_baud, set_baud);
971 /* set receive timeout && data bits len */
972 rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000);
973 rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out);
974 txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op);
975 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_STOP);
976 wr_regl(port, ureg->sirfsoc_tx_fifo_op,
977 (txfifo_op_reg & ~SIRFUART_FIFO_START));
978 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
979 config_reg |= SIRFUART_RECV_TIMEOUT(port, rx_time_out);
980 wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg);
981 } else {
982 /*tx frame ctrl*/
983 len_val = (data_bit_len - 1) << SIRFSOC_USP_TX_DATA_LEN_OFFSET;
984 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
985 SIRFSOC_USP_TX_FRAME_LEN_OFFSET;
986 len_val |= ((data_bit_len - 1) <<
987 SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET);
988 len_val |= (((clk_div_reg & 0xc00) >> 10) <<
989 SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET);
990 wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val);
991 /*rx frame ctrl*/
992 len_val = (data_bit_len - 1) << SIRFSOC_USP_RX_DATA_LEN_OFFSET;
993 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
994 SIRFSOC_USP_RX_FRAME_LEN_OFFSET;
995 len_val |= (data_bit_len - 1) <<
996 SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET;
997 len_val |= (((clk_div_reg & 0xf000) >> 12) <<
998 SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET);
999 wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val);
1000 /*async param*/
1001 wr_regl(port, ureg->sirfsoc_async_param_reg,
1002 (SIRFUART_RECV_TIMEOUT(port, rx_time_out)) |
1003 (sample_div_reg & SIRFSOC_USP_ASYNC_DIV2_MASK) <<
1004 SIRFSOC_USP_ASYNC_DIV2_OFFSET);
1005 }
1006 if (sirfport->tx_dma_chan)
1007 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_DMA_MODE);
1008 else
1009 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE);
1010 if (sirfport->rx_dma_chan)
1011 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, SIRFUART_DMA_MODE);
1012 else
1013 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, SIRFUART_IO_MODE);
1014 /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
1015 if (set_baud < 1000000)
1016 threshold_div = 1;
1017 else
1018 threshold_div = 2;
1019 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl,
1020 SIRFUART_FIFO_THD(port) / threshold_div);
1021 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl,
1022 SIRFUART_FIFO_THD(port) / threshold_div);
1023 txfifo_op_reg |= SIRFUART_FIFO_START;
1024 wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg);
1025 uart_update_timeout(port, termios->c_cflag, set_baud);
1026 sirfsoc_uart_start_rx(port);
1027 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN);
1028 spin_unlock_irqrestore(&port->lock, flags);
1029 }
1030
1031 static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state,
1032 unsigned int oldstate)
1033 {
1034 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1035 if (!state) {
1036 if (sirfport->is_bt_uart) {
1037 clk_prepare_enable(sirfport->clk_noc);
1038 clk_prepare_enable(sirfport->clk_general);
1039 }
1040 clk_prepare_enable(sirfport->clk);
1041 } else {
1042 clk_disable_unprepare(sirfport->clk);
1043 if (sirfport->is_bt_uart) {
1044 clk_disable_unprepare(sirfport->clk_general);
1045 clk_disable_unprepare(sirfport->clk_noc);
1046 }
1047 }
1048 }
1049
1050 static int sirfsoc_uart_startup(struct uart_port *port)
1051 {
1052 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1053 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1054 unsigned int index = port->line;
1055 int ret;
1056 set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
1057 ret = request_irq(port->irq,
1058 sirfsoc_uart_isr,
1059 0,
1060 SIRFUART_PORT_NAME,
1061 sirfport);
1062 if (ret != 0) {
1063 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
1064 index, port->irq);
1065 goto irq_err;
1066 }
1067
1068 /* initial hardware settings */
1069 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
1070 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) |
1071 SIRFUART_IO_MODE);
1072 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
1073 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
1074 SIRFUART_IO_MODE);
1075 wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0);
1076 wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0);
1077 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN);
1078 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
1079 wr_regl(port, ureg->sirfsoc_mode1,
1080 SIRFSOC_USP_ENDIAN_CTRL_LSBF |
1081 SIRFSOC_USP_EN);
1082 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET);
1083 wr_regl(port, ureg->sirfsoc_tx_fifo_op, 0);
1084 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
1085 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
1086 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, SIRFUART_FIFO_THD(port));
1087 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, SIRFUART_FIFO_THD(port));
1088 if (sirfport->rx_dma_chan)
1089 wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk,
1090 SIRFUART_RX_FIFO_CHK_SC(port->line, 0x4) |
1091 SIRFUART_RX_FIFO_CHK_LC(port->line, 0xe) |
1092 SIRFUART_RX_FIFO_CHK_HC(port->line, 0x1b));
1093 if (sirfport->tx_dma_chan) {
1094 sirfport->tx_dma_state = TX_DMA_IDLE;
1095 wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk,
1096 SIRFUART_TX_FIFO_CHK_SC(port->line, 0x1b) |
1097 SIRFUART_TX_FIFO_CHK_LC(port->line, 0xe) |
1098 SIRFUART_TX_FIFO_CHK_HC(port->line, 0x4));
1099 }
1100 sirfport->ms_enabled = false;
1101 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
1102 sirfport->hw_flow_ctrl) {
1103 set_irq_flags(gpio_to_irq(sirfport->cts_gpio),
1104 IRQF_VALID | IRQF_NOAUTOEN);
1105 ret = request_irq(gpio_to_irq(sirfport->cts_gpio),
1106 sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING |
1107 IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport);
1108 if (ret != 0) {
1109 dev_err(port->dev, "UART-USP:request gpio irq fail\n");
1110 goto init_rx_err;
1111 }
1112 }
1113
1114 enable_irq(port->irq);
1115
1116 return 0;
1117 init_rx_err:
1118 free_irq(port->irq, sirfport);
1119 irq_err:
1120 return ret;
1121 }
1122
1123 static void sirfsoc_uart_shutdown(struct uart_port *port)
1124 {
1125 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1126 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1127 if (!sirfport->is_marco)
1128 wr_regl(port, ureg->sirfsoc_int_en_reg, 0);
1129 else
1130 wr_regl(port, SIRFUART_INT_EN_CLR, ~0UL);
1131
1132 free_irq(port->irq, sirfport);
1133 if (sirfport->ms_enabled)
1134 sirfsoc_uart_disable_ms(port);
1135 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
1136 sirfport->hw_flow_ctrl) {
1137 gpio_set_value(sirfport->rts_gpio, 1);
1138 free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport);
1139 }
1140 if (sirfport->tx_dma_chan)
1141 sirfport->tx_dma_state = TX_DMA_IDLE;
1142 }
1143
1144 static const char *sirfsoc_uart_type(struct uart_port *port)
1145 {
1146 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
1147 }
1148
1149 static int sirfsoc_uart_request_port(struct uart_port *port)
1150 {
1151 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1152 struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param;
1153 void *ret;
1154 ret = request_mem_region(port->mapbase,
1155 SIRFUART_MAP_SIZE, uart_param->port_name);
1156 return ret ? 0 : -EBUSY;
1157 }
1158
1159 static void sirfsoc_uart_release_port(struct uart_port *port)
1160 {
1161 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
1162 }
1163
1164 static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
1165 {
1166 if (flags & UART_CONFIG_TYPE) {
1167 port->type = SIRFSOC_PORT_TYPE;
1168 sirfsoc_uart_request_port(port);
1169 }
1170 }
1171
1172 static struct uart_ops sirfsoc_uart_ops = {
1173 .tx_empty = sirfsoc_uart_tx_empty,
1174 .get_mctrl = sirfsoc_uart_get_mctrl,
1175 .set_mctrl = sirfsoc_uart_set_mctrl,
1176 .stop_tx = sirfsoc_uart_stop_tx,
1177 .start_tx = sirfsoc_uart_start_tx,
1178 .stop_rx = sirfsoc_uart_stop_rx,
1179 .enable_ms = sirfsoc_uart_enable_ms,
1180 .break_ctl = sirfsoc_uart_break_ctl,
1181 .startup = sirfsoc_uart_startup,
1182 .shutdown = sirfsoc_uart_shutdown,
1183 .set_termios = sirfsoc_uart_set_termios,
1184 .pm = sirfsoc_uart_pm,
1185 .type = sirfsoc_uart_type,
1186 .release_port = sirfsoc_uart_release_port,
1187 .request_port = sirfsoc_uart_request_port,
1188 .config_port = sirfsoc_uart_config_port,
1189 };
1190
1191 #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
1192 static int __init
1193 sirfsoc_uart_console_setup(struct console *co, char *options)
1194 {
1195 unsigned int baud = 115200;
1196 unsigned int bits = 8;
1197 unsigned int parity = 'n';
1198 unsigned int flow = 'n';
1199 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
1200 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1201 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1202 if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
1203 return -EINVAL;
1204
1205 if (!port->mapbase)
1206 return -ENODEV;
1207
1208 /* enable usp in mode1 register */
1209 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
1210 wr_regl(port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN |
1211 SIRFSOC_USP_ENDIAN_CTRL_LSBF);
1212 if (options)
1213 uart_parse_options(options, &baud, &parity, &bits, &flow);
1214 port->cons = co;
1215
1216 /* default console tx/rx transfer using io mode */
1217 sirfport->rx_dma_chan = NULL;
1218 sirfport->tx_dma_chan = NULL;
1219 return uart_set_options(port, co, baud, parity, bits, flow);
1220 }
1221
1222 static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
1223 {
1224 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1225 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1226 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
1227 while (rd_regl(port,
1228 ureg->sirfsoc_tx_fifo_status) & ufifo_st->ff_full(port->line))
1229 cpu_relax();
1230 wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch);
1231 }
1232
1233 static void sirfsoc_uart_console_write(struct console *co, const char *s,
1234 unsigned int count)
1235 {
1236 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
1237 uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
1238 }
1239
1240 static struct console sirfsoc_uart_console = {
1241 .name = SIRFSOC_UART_NAME,
1242 .device = uart_console_device,
1243 .flags = CON_PRINTBUFFER,
1244 .index = -1,
1245 .write = sirfsoc_uart_console_write,
1246 .setup = sirfsoc_uart_console_setup,
1247 .data = &sirfsoc_uart_drv,
1248 };
1249
1250 static int __init sirfsoc_uart_console_init(void)
1251 {
1252 register_console(&sirfsoc_uart_console);
1253 return 0;
1254 }
1255 console_initcall(sirfsoc_uart_console_init);
1256 #endif
1257
1258 static struct uart_driver sirfsoc_uart_drv = {
1259 .owner = THIS_MODULE,
1260 .driver_name = SIRFUART_PORT_NAME,
1261 .nr = SIRFSOC_UART_NR,
1262 .dev_name = SIRFSOC_UART_NAME,
1263 .major = SIRFSOC_UART_MAJOR,
1264 .minor = SIRFSOC_UART_MINOR,
1265 #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
1266 .cons = &sirfsoc_uart_console,
1267 #else
1268 .cons = NULL,
1269 #endif
1270 };
1271
1272 static struct of_device_id sirfsoc_uart_ids[] = {
1273 { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
1274 { .compatible = "sirf,marco-uart", .data = &sirfsoc_uart},
1275 { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
1276 {}
1277 };
1278 MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
1279
1280 static int sirfsoc_uart_probe(struct platform_device *pdev)
1281 {
1282 struct sirfsoc_uart_port *sirfport;
1283 struct uart_port *port;
1284 struct resource *res;
1285 int ret;
1286 int i, j;
1287 struct dma_slave_config slv_cfg = {
1288 .src_maxburst = 2,
1289 };
1290 struct dma_slave_config tx_slv_cfg = {
1291 .dst_maxburst = 2,
1292 };
1293 const struct of_device_id *match;
1294
1295 match = of_match_node(sirfsoc_uart_ids, pdev->dev.of_node);
1296 if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
1297 dev_err(&pdev->dev,
1298 "Unable to find cell-index in uart node.\n");
1299 ret = -EFAULT;
1300 goto err;
1301 }
1302 if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart"))
1303 pdev->id += ((struct sirfsoc_uart_register *)
1304 match->data)->uart_param.register_uart_nr;
1305 sirfport = &sirfsoc_uart_ports[pdev->id];
1306 port = &sirfport->port;
1307 port->dev = &pdev->dev;
1308 port->private_data = sirfport;
1309 sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data;
1310
1311 sirfport->hw_flow_ctrl = of_property_read_bool(pdev->dev.of_node,
1312 "sirf,uart-has-rtscts");
1313 if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-uart"))
1314 sirfport->uart_reg->uart_type = SIRF_REAL_UART;
1315 if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart")) {
1316 sirfport->uart_reg->uart_type = SIRF_USP_UART;
1317 if (!sirfport->hw_flow_ctrl)
1318 goto usp_no_flow_control;
1319 if (of_find_property(pdev->dev.of_node, "cts-gpios", NULL))
1320 sirfport->cts_gpio = of_get_named_gpio(
1321 pdev->dev.of_node, "cts-gpios", 0);
1322 else
1323 sirfport->cts_gpio = -1;
1324 if (of_find_property(pdev->dev.of_node, "rts-gpios", NULL))
1325 sirfport->rts_gpio = of_get_named_gpio(
1326 pdev->dev.of_node, "rts-gpios", 0);
1327 else
1328 sirfport->rts_gpio = -1;
1329
1330 if ((!gpio_is_valid(sirfport->cts_gpio) ||
1331 !gpio_is_valid(sirfport->rts_gpio))) {
1332 ret = -EINVAL;
1333 dev_err(&pdev->dev,
1334 "Usp flow control must have cts and rts gpio");
1335 goto err;
1336 }
1337 ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio,
1338 "usp-cts-gpio");
1339 if (ret) {
1340 dev_err(&pdev->dev, "Unable request cts gpio");
1341 goto err;
1342 }
1343 gpio_direction_input(sirfport->cts_gpio);
1344 ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio,
1345 "usp-rts-gpio");
1346 if (ret) {
1347 dev_err(&pdev->dev, "Unable request rts gpio");
1348 goto err;
1349 }
1350 gpio_direction_output(sirfport->rts_gpio, 1);
1351 }
1352 usp_no_flow_control:
1353 if (of_device_is_compatible(pdev->dev.of_node, "sirf,marco-uart"))
1354 sirfport->is_marco = true;
1355
1356 if (of_property_read_u32(pdev->dev.of_node,
1357 "fifosize",
1358 &port->fifosize)) {
1359 dev_err(&pdev->dev,
1360 "Unable to find fifosize in uart node.\n");
1361 ret = -EFAULT;
1362 goto err;
1363 }
1364
1365 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1366 if (res == NULL) {
1367 dev_err(&pdev->dev, "Insufficient resources.\n");
1368 ret = -EFAULT;
1369 goto err;
1370 }
1371 tasklet_init(&sirfport->rx_dma_complete_tasklet,
1372 sirfsoc_uart_rx_dma_complete_tl, (unsigned long)sirfport);
1373 tasklet_init(&sirfport->rx_tmo_process_tasklet,
1374 sirfsoc_rx_tmo_process_tl, (unsigned long)sirfport);
1375 port->mapbase = res->start;
1376 port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1377 if (!port->membase) {
1378 dev_err(&pdev->dev, "Cannot remap resource.\n");
1379 ret = -ENOMEM;
1380 goto err;
1381 }
1382 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1383 if (res == NULL) {
1384 dev_err(&pdev->dev, "Insufficient resources.\n");
1385 ret = -EFAULT;
1386 goto err;
1387 }
1388 port->irq = res->start;
1389
1390 sirfport->clk = devm_clk_get(&pdev->dev, NULL);
1391 if (IS_ERR(sirfport->clk)) {
1392 ret = PTR_ERR(sirfport->clk);
1393 goto err;
1394 }
1395 port->uartclk = clk_get_rate(sirfport->clk);
1396 if (of_device_is_compatible(pdev->dev.of_node, "sirf,marco-bt-uart")) {
1397 sirfport->clk_general = devm_clk_get(&pdev->dev, "general");
1398 if (IS_ERR(sirfport->clk_general)) {
1399 ret = PTR_ERR(sirfport->clk_general);
1400 goto err;
1401 }
1402 sirfport->clk_noc = devm_clk_get(&pdev->dev, "noc");
1403 if (IS_ERR(sirfport->clk_noc)) {
1404 ret = PTR_ERR(sirfport->clk_noc);
1405 goto err;
1406 }
1407 sirfport->is_bt_uart = true;
1408 } else
1409 sirfport->is_bt_uart = false;
1410
1411 port->ops = &sirfsoc_uart_ops;
1412 spin_lock_init(&port->lock);
1413
1414 platform_set_drvdata(pdev, sirfport);
1415 ret = uart_add_one_port(&sirfsoc_uart_drv, port);
1416 if (ret != 0) {
1417 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
1418 goto err;
1419 }
1420
1421 sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx");
1422 for (i = 0; sirfport->rx_dma_chan && i < SIRFSOC_RX_LOOP_BUF_CNT; i++) {
1423 sirfport->rx_dma_items[i].xmit.buf =
1424 dma_alloc_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1425 &sirfport->rx_dma_items[i].dma_addr, GFP_KERNEL);
1426 if (!sirfport->rx_dma_items[i].xmit.buf) {
1427 dev_err(port->dev, "Uart alloc bufa failed\n");
1428 ret = -ENOMEM;
1429 goto alloc_coherent_err;
1430 }
1431 sirfport->rx_dma_items[i].xmit.head =
1432 sirfport->rx_dma_items[i].xmit.tail = 0;
1433 }
1434 if (sirfport->rx_dma_chan)
1435 dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg);
1436 sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx");
1437 if (sirfport->tx_dma_chan)
1438 dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg);
1439
1440 return 0;
1441 alloc_coherent_err:
1442 for (j = 0; j < i; j++)
1443 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1444 sirfport->rx_dma_items[j].xmit.buf,
1445 sirfport->rx_dma_items[j].dma_addr);
1446 dma_release_channel(sirfport->rx_dma_chan);
1447 err:
1448 return ret;
1449 }
1450
1451 static int sirfsoc_uart_remove(struct platform_device *pdev)
1452 {
1453 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
1454 struct uart_port *port = &sirfport->port;
1455 uart_remove_one_port(&sirfsoc_uart_drv, port);
1456 if (sirfport->rx_dma_chan) {
1457 int i;
1458 dmaengine_terminate_all(sirfport->rx_dma_chan);
1459 dma_release_channel(sirfport->rx_dma_chan);
1460 for (i = 0; i < SIRFSOC_RX_LOOP_BUF_CNT; i++)
1461 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1462 sirfport->rx_dma_items[i].xmit.buf,
1463 sirfport->rx_dma_items[i].dma_addr);
1464 }
1465 if (sirfport->tx_dma_chan) {
1466 dmaengine_terminate_all(sirfport->tx_dma_chan);
1467 dma_release_channel(sirfport->tx_dma_chan);
1468 }
1469 return 0;
1470 }
1471
1472 #ifdef CONFIG_PM_SLEEP
1473 static int
1474 sirfsoc_uart_suspend(struct device *pdev)
1475 {
1476 struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
1477 struct uart_port *port = &sirfport->port;
1478 uart_suspend_port(&sirfsoc_uart_drv, port);
1479 return 0;
1480 }
1481
1482 static int sirfsoc_uart_resume(struct device *pdev)
1483 {
1484 struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
1485 struct uart_port *port = &sirfport->port;
1486 uart_resume_port(&sirfsoc_uart_drv, port);
1487 return 0;
1488 }
1489 #endif
1490
1491 static const struct dev_pm_ops sirfsoc_uart_pm_ops = {
1492 SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_uart_suspend, sirfsoc_uart_resume)
1493 };
1494
1495 static struct platform_driver sirfsoc_uart_driver = {
1496 .probe = sirfsoc_uart_probe,
1497 .remove = sirfsoc_uart_remove,
1498 .driver = {
1499 .name = SIRFUART_PORT_NAME,
1500 .of_match_table = sirfsoc_uart_ids,
1501 .pm = &sirfsoc_uart_pm_ops,
1502 },
1503 };
1504
1505 static int __init sirfsoc_uart_init(void)
1506 {
1507 int ret = 0;
1508
1509 ret = uart_register_driver(&sirfsoc_uart_drv);
1510 if (ret)
1511 goto out;
1512
1513 ret = platform_driver_register(&sirfsoc_uart_driver);
1514 if (ret)
1515 uart_unregister_driver(&sirfsoc_uart_drv);
1516 out:
1517 return ret;
1518 }
1519 module_init(sirfsoc_uart_init);
1520
1521 static void __exit sirfsoc_uart_exit(void)
1522 {
1523 platform_driver_unregister(&sirfsoc_uart_driver);
1524 uart_unregister_driver(&sirfsoc_uart_drv);
1525 }
1526 module_exit(sirfsoc_uart_exit);
1527
1528 MODULE_LICENSE("GPL v2");
1529 MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
1530 MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");
Linux with added FPC-III support