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Linux 4.14.51
[linux/fpc-iii.git] / drivers / edac / skx_edac.c
blob16dea97568a1ede6e8a36aa613f35329e1d9d902
1 /*
2 * EDAC driver for Intel(R) Xeon(R) Skylake processors
3 * Copyright (c) 2016, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/pci.h>
18 #include <linux/pci_ids.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/edac.h>
22 #include <linux/mmzone.h>
23 #include <linux/smp.h>
24 #include <linux/bitmap.h>
25 #include <linux/math64.h>
26 #include <linux/mod_devicetable.h>
27 #include <asm/cpu_device_id.h>
28 #include <asm/intel-family.h>
29 #include <asm/processor.h>
30 #include <asm/mce.h>
31
32 #include "edac_module.h"
33
34 /*
35 * Debug macros
36 */
37 #define skx_printk(level, fmt, arg...) \
38 edac_printk(level, "skx", fmt, ##arg)
39
40 #define skx_mc_printk(mci, level, fmt, arg...) \
41 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
42
43 /*
44 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
45 */
46 #define GET_BITFIELD(v, lo, hi) \
47 (((v) & GENMASK_ULL((hi), (lo))) >> (lo))
48
49 static LIST_HEAD(skx_edac_list);
50
51 static u64 skx_tolm, skx_tohm;
52
53 #define NUM_IMC 2 /* memory controllers per socket */
54 #define NUM_CHANNELS 3 /* channels per memory controller */
55 #define NUM_DIMMS 2 /* Max DIMMS per channel */
56
57 #define MASK26 0x3FFFFFF /* Mask for 2^26 */
58 #define MASK29 0x1FFFFFFF /* Mask for 2^29 */
59
60 /*
61 * Each cpu socket contains some pci devices that provide global
62 * information, and also some that are local to each of the two
63 * memory controllers on the die.
64 */
65 struct skx_dev {
66 struct list_head list;
67 u8 bus[4];
68 struct pci_dev *sad_all;
69 struct pci_dev *util_all;
70 u32 mcroute;
71 struct skx_imc {
72 struct mem_ctl_info *mci;
73 u8 mc; /* system wide mc# */
74 u8 lmc; /* socket relative mc# */
75 u8 src_id, node_id;
76 struct skx_channel {
77 struct pci_dev *cdev;
78 struct skx_dimm {
79 u8 close_pg;
80 u8 bank_xor_enable;
81 u8 fine_grain_bank;
82 u8 rowbits;
83 u8 colbits;
84 } dimms[NUM_DIMMS];
85 } chan[NUM_CHANNELS];
86 } imc[NUM_IMC];
87 };
88 static int skx_num_sockets;
89
90 struct skx_pvt {
91 struct skx_imc *imc;
92 };
93
94 struct decoded_addr {
95 struct skx_dev *dev;
96 u64 addr;
97 int socket;
98 int imc;
99 int channel;
100 u64 chan_addr;
101 int sktways;
102 int chanways;
103 int dimm;
104 int rank;
105 int channel_rank;
106 u64 rank_address;
107 int row;
108 int column;
109 int bank_address;
110 int bank_group;
111 };
112
113 static struct skx_dev *get_skx_dev(u8 bus, u8 idx)
114 {
115 struct skx_dev *d;
116
117 list_for_each_entry(d, &skx_edac_list, list) {
118 if (d->bus[idx] == bus)
119 return d;
120 }
121
122 return NULL;
123 }
124
125 enum munittype {
126 CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD
127 };
128
129 struct munit {
130 u16 did;
131 u16 devfn[NUM_IMC];
132 u8 busidx;
133 u8 per_socket;
134 enum munittype mtype;
135 };
136
137 /*
138 * List of PCI device ids that we need together with some device
139 * number and function numbers to tell which memory controller the
140 * device belongs to.
141 */
142 static const struct munit skx_all_munits[] = {
143 { 0x2054, { }, 1, 1, SAD_ALL },
144 { 0x2055, { }, 1, 1, UTIL_ALL },
145 { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 },
146 { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 },
147 { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 },
148 { 0x208e, { }, 1, 0, SAD },
149 { }
150 };
151
152 /*
153 * We use the per-socket device 0x2016 to count how many sockets are present,
154 * and to detemine which PCI buses are associated with each socket. Allocate
155 * and build the full list of all the skx_dev structures that we need here.
156 */
157 static int get_all_bus_mappings(void)
158 {
159 struct pci_dev *pdev, *prev;
160 struct skx_dev *d;
161 u32 reg;
162 int ndev = 0;
163
164 prev = NULL;
165 for (;;) {
166 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2016, prev);
167 if (!pdev)
168 break;
169 ndev++;
170 d = kzalloc(sizeof(*d), GFP_KERNEL);
171 if (!d) {
172 pci_dev_put(pdev);
173 return -ENOMEM;
174 }
175 pci_read_config_dword(pdev, 0xCC, &reg);
176 d->bus[0] = GET_BITFIELD(reg, 0, 7);
177 d->bus[1] = GET_BITFIELD(reg, 8, 15);
178 d->bus[2] = GET_BITFIELD(reg, 16, 23);
179 d->bus[3] = GET_BITFIELD(reg, 24, 31);
180 edac_dbg(2, "busses: %x, %x, %x, %x\n",
181 d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
182 list_add_tail(&d->list, &skx_edac_list);
183 skx_num_sockets++;
184 prev = pdev;
185 }
186
187 return ndev;
188 }
189
190 static int get_all_munits(const struct munit *m)
191 {
192 struct pci_dev *pdev, *prev;
193 struct skx_dev *d;
194 u32 reg;
195 int i = 0, ndev = 0;
196
197 prev = NULL;
198 for (;;) {
199 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev);
200 if (!pdev)
201 break;
202 ndev++;
203 if (m->per_socket == NUM_IMC) {
204 for (i = 0; i < NUM_IMC; i++)
205 if (m->devfn[i] == pdev->devfn)
206 break;
207 if (i == NUM_IMC)
208 goto fail;
209 }
210 d = get_skx_dev(pdev->bus->number, m->busidx);
211 if (!d)
212 goto fail;
213
214 /* Be sure that the device is enabled */
215 if (unlikely(pci_enable_device(pdev) < 0)) {
216 skx_printk(KERN_ERR,
217 "Couldn't enable %04x:%04x\n", PCI_VENDOR_ID_INTEL, m->did);
218 goto fail;
219 }
220
221 switch (m->mtype) {
222 case CHAN0: case CHAN1: case CHAN2:
223 pci_dev_get(pdev);
224 d->imc[i].chan[m->mtype].cdev = pdev;
225 break;
226 case SAD_ALL:
227 pci_dev_get(pdev);
228 d->sad_all = pdev;
229 break;
230 case UTIL_ALL:
231 pci_dev_get(pdev);
232 d->util_all = pdev;
233 break;
234 case SAD:
235 /*
236 * one of these devices per core, including cores
237 * that don't exist on this SKU. Ignore any that
238 * read a route table of zero, make sure all the
239 * non-zero values match.
240 */
241 pci_read_config_dword(pdev, 0xB4, &reg);
242 if (reg != 0) {
243 if (d->mcroute == 0)
244 d->mcroute = reg;
245 else if (d->mcroute != reg) {
246 skx_printk(KERN_ERR,
247 "mcroute mismatch\n");
248 goto fail;
249 }
250 }
251 ndev--;
252 break;
253 }
254
255 prev = pdev;
256 }
257
258 return ndev;
259 fail:
260 pci_dev_put(pdev);
261 return -ENODEV;
262 }
263
264 static const struct x86_cpu_id skx_cpuids[] = {
265 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X, 0, 0 },
266 { }
267 };
268 MODULE_DEVICE_TABLE(x86cpu, skx_cpuids);
269
270 static u8 get_src_id(struct skx_dev *d)
271 {
272 u32 reg;
273
274 pci_read_config_dword(d->util_all, 0xF0, &reg);
275
276 return GET_BITFIELD(reg, 12, 14);
277 }
278
279 static u8 skx_get_node_id(struct skx_dev *d)
280 {
281 u32 reg;
282
283 pci_read_config_dword(d->util_all, 0xF4, &reg);
284
285 return GET_BITFIELD(reg, 0, 2);
286 }
287
288 static int get_dimm_attr(u32 reg, int lobit, int hibit, int add, int minval,
289 int maxval, char *name)
290 {
291 u32 val = GET_BITFIELD(reg, lobit, hibit);
292
293 if (val < minval || val > maxval) {
294 edac_dbg(2, "bad %s = %d (raw=%x)\n", name, val, reg);
295 return -EINVAL;
296 }
297 return val + add;
298 }
299
300 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD((mtr), 15, 15)
301
302 #define numrank(reg) get_dimm_attr((reg), 12, 13, 0, 1, 2, "ranks")
303 #define numrow(reg) get_dimm_attr((reg), 2, 4, 12, 1, 6, "rows")
304 #define numcol(reg) get_dimm_attr((reg), 0, 1, 10, 0, 2, "cols")
305
306 static int get_width(u32 mtr)
307 {
308 switch (GET_BITFIELD(mtr, 8, 9)) {
309 case 0:
310 return DEV_X4;
311 case 1:
312 return DEV_X8;
313 case 2:
314 return DEV_X16;
315 }
316 return DEV_UNKNOWN;
317 }
318
319 static int skx_get_hi_lo(void)
320 {
321 struct pci_dev *pdev;
322 u32 reg;
323
324 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2034, NULL);
325 if (!pdev) {
326 edac_dbg(0, "Can't get tolm/tohm\n");
327 return -ENODEV;
328 }
329
330 pci_read_config_dword(pdev, 0xD0, &reg);
331 skx_tolm = reg;
332 pci_read_config_dword(pdev, 0xD4, &reg);
333 skx_tohm = reg;
334 pci_read_config_dword(pdev, 0xD8, &reg);
335 skx_tohm |= (u64)reg << 32;
336
337 pci_dev_put(pdev);
338 edac_dbg(2, "tolm=%llx tohm=%llx\n", skx_tolm, skx_tohm);
339
340 return 0;
341 }
342
343 static int get_dimm_info(u32 mtr, u32 amap, struct dimm_info *dimm,
344 struct skx_imc *imc, int chan, int dimmno)
345 {
346 int banks = 16, ranks, rows, cols, npages;
347 u64 size;
348
349 if (!IS_DIMM_PRESENT(mtr))
350 return 0;
351 ranks = numrank(mtr);
352 rows = numrow(mtr);
353 cols = numcol(mtr);
354
355 /*
356 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
357 */
358 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
359 npages = MiB_TO_PAGES(size);
360
361 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
362 imc->mc, chan, dimmno, size, npages,
363 banks, ranks, rows, cols);
364
365 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mtr, 0, 0);
366 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mtr, 9, 9);
367 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
368 imc->chan[chan].dimms[dimmno].rowbits = rows;
369 imc->chan[chan].dimms[dimmno].colbits = cols;
370
371 dimm->nr_pages = npages;
372 dimm->grain = 32;
373 dimm->dtype = get_width(mtr);
374 dimm->mtype = MEM_DDR4;
375 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
376 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
377 imc->src_id, imc->lmc, chan, dimmno);
378
379 return 1;
380 }
381
382 #define SKX_GET_MTMTR(dev, reg) \
383 pci_read_config_dword((dev), 0x87c, &reg)
384
385 static bool skx_check_ecc(struct pci_dev *pdev)
386 {
387 u32 mtmtr;
388
389 SKX_GET_MTMTR(pdev, mtmtr);
390
391 return !!GET_BITFIELD(mtmtr, 2, 2);
392 }
393
394 static int skx_get_dimm_config(struct mem_ctl_info *mci)
395 {
396 struct skx_pvt *pvt = mci->pvt_info;
397 struct skx_imc *imc = pvt->imc;
398 struct dimm_info *dimm;
399 int i, j;
400 u32 mtr, amap;
401 int ndimms;
402
403 for (i = 0; i < NUM_CHANNELS; i++) {
404 ndimms = 0;
405 pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap);
406 for (j = 0; j < NUM_DIMMS; j++) {
407 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
408 mci->n_layers, i, j, 0);
409 pci_read_config_dword(imc->chan[i].cdev,
410 0x80 + 4*j, &mtr);
411 ndimms += get_dimm_info(mtr, amap, dimm, imc, i, j);
412 }
413 if (ndimms && !skx_check_ecc(imc->chan[0].cdev)) {
414 skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc);
415 return -ENODEV;
416 }
417 }
418
419 return 0;
420 }
421
422 static void skx_unregister_mci(struct skx_imc *imc)
423 {
424 struct mem_ctl_info *mci = imc->mci;
425
426 if (!mci)
427 return;
428
429 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
430
431 /* Remove MC sysfs nodes */
432 edac_mc_del_mc(mci->pdev);
433
434 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
435 kfree(mci->ctl_name);
436 edac_mc_free(mci);
437 }
438
439 static int skx_register_mci(struct skx_imc *imc)
440 {
441 struct mem_ctl_info *mci;
442 struct edac_mc_layer layers[2];
443 struct pci_dev *pdev = imc->chan[0].cdev;
444 struct skx_pvt *pvt;
445 int rc;
446
447 /* allocate a new MC control structure */
448 layers[0].type = EDAC_MC_LAYER_CHANNEL;
449 layers[0].size = NUM_CHANNELS;
450 layers[0].is_virt_csrow = false;
451 layers[1].type = EDAC_MC_LAYER_SLOT;
452 layers[1].size = NUM_DIMMS;
453 layers[1].is_virt_csrow = true;
454 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
455 sizeof(struct skx_pvt));
456
457 if (unlikely(!mci))
458 return -ENOMEM;
459
460 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
461
462 /* Associate skx_dev and mci for future usage */
463 imc->mci = mci;
464 pvt = mci->pvt_info;
465 pvt->imc = imc;
466
467 mci->ctl_name = kasprintf(GFP_KERNEL, "Skylake Socket#%d IMC#%d",
468 imc->node_id, imc->lmc);
469 mci->mtype_cap = MEM_FLAG_DDR4;
470 mci->edac_ctl_cap = EDAC_FLAG_NONE;
471 mci->edac_cap = EDAC_FLAG_NONE;
472 mci->mod_name = "skx_edac.c";
473 mci->dev_name = pci_name(imc->chan[0].cdev);
474 mci->ctl_page_to_phys = NULL;
475
476 rc = skx_get_dimm_config(mci);
477 if (rc < 0)
478 goto fail;
479
480 /* record ptr to the generic device */
481 mci->pdev = &pdev->dev;
482
483 /* add this new MC control structure to EDAC's list of MCs */
484 if (unlikely(edac_mc_add_mc(mci))) {
485 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
486 rc = -EINVAL;
487 goto fail;
488 }
489
490 return 0;
491
492 fail:
493 kfree(mci->ctl_name);
494 edac_mc_free(mci);
495 imc->mci = NULL;
496 return rc;
497 }
498
499 #define SKX_MAX_SAD 24
500
501 #define SKX_GET_SAD(d, i, reg) \
502 pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &reg)
503 #define SKX_GET_ILV(d, i, reg) \
504 pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &reg)
505
506 #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31)
507 #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27)
508 #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)
509 #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)
510 #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4)
511 #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)
512 #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)
513
514 #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0)
515 #define SKX_ILV_TARGET(tgt) ((tgt) & 7)
516
517 static bool skx_sad_decode(struct decoded_addr *res)
518 {
519 struct skx_dev *d = list_first_entry(&skx_edac_list, typeof(*d), list);
520 u64 addr = res->addr;
521 int i, idx, tgt, lchan, shift;
522 u32 sad, ilv;
523 u64 limit, prev_limit;
524 int remote = 0;
525
526 /* Simple sanity check for I/O space or out of range */
527 if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) {
528 edac_dbg(0, "Address %llx out of range\n", addr);
529 return false;
530 }
531
532 restart:
533 prev_limit = 0;
534 for (i = 0; i < SKX_MAX_SAD; i++) {
535 SKX_GET_SAD(d, i, sad);
536 limit = SKX_SAD_LIMIT(sad);
537 if (SKX_SAD_ENABLE(sad)) {
538 if (addr >= prev_limit && addr <= limit)
539 goto sad_found;
540 }
541 prev_limit = limit + 1;
542 }
543 edac_dbg(0, "No SAD entry for %llx\n", addr);
544 return false;
545
546 sad_found:
547 SKX_GET_ILV(d, i, ilv);
548
549 switch (SKX_SAD_INTERLEAVE(sad)) {
550 case 0:
551 idx = GET_BITFIELD(addr, 6, 8);
552 break;
553 case 1:
554 idx = GET_BITFIELD(addr, 8, 10);
555 break;
556 case 2:
557 idx = GET_BITFIELD(addr, 12, 14);
558 break;
559 case 3:
560 idx = GET_BITFIELD(addr, 30, 32);
561 break;
562 }
563
564 tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3);
565
566 /* If point to another node, find it and start over */
567 if (SKX_ILV_REMOTE(tgt)) {
568 if (remote) {
569 edac_dbg(0, "Double remote!\n");
570 return false;
571 }
572 remote = 1;
573 list_for_each_entry(d, &skx_edac_list, list) {
574 if (d->imc[0].src_id == SKX_ILV_TARGET(tgt))
575 goto restart;
576 }
577 edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt));
578 return false;
579 }
580
581 if (SKX_SAD_MOD3(sad) == 0)
582 lchan = SKX_ILV_TARGET(tgt);
583 else {
584 switch (SKX_SAD_MOD3MODE(sad)) {
585 case 0:
586 shift = 6;
587 break;
588 case 1:
589 shift = 8;
590 break;
591 case 2:
592 shift = 12;
593 break;
594 default:
595 edac_dbg(0, "illegal mod3mode\n");
596 return false;
597 }
598 switch (SKX_SAD_MOD3ASMOD2(sad)) {
599 case 0:
600 lchan = (addr >> shift) % 3;
601 break;
602 case 1:
603 lchan = (addr >> shift) % 2;
604 break;
605 case 2:
606 lchan = (addr >> shift) % 2;
607 lchan = (lchan << 1) | ~lchan;
608 break;
609 case 3:
610 lchan = ((addr >> shift) % 2) << 1;
611 break;
612 }
613 lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1);
614 }
615
616 res->dev = d;
617 res->socket = d->imc[0].src_id;
618 res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2);
619 res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19);
620
621 edac_dbg(2, "%llx: socket=%d imc=%d channel=%d\n",
622 res->addr, res->socket, res->imc, res->channel);
623 return true;
624 }
625
626 #define SKX_MAX_TAD 8
627
628 #define SKX_GET_TADBASE(d, mc, i, reg) \
629 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &reg)
630 #define SKX_GET_TADWAYNESS(d, mc, i, reg) \
631 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &reg)
632 #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \
633 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &reg)
634
635 #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26)
636 #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5)
637 #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7)
638 #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26)
639 #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26)
640 #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11))
641 #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1)
642
643 /* which bit used for both socket and channel interleave */
644 static int skx_granularity[] = { 6, 8, 12, 30 };
645
646 static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits)
647 {
648 addr >>= shift;
649 addr /= ways;
650 addr <<= shift;
651
652 return addr | (lowbits & ((1ull << shift) - 1));
653 }
654
655 static bool skx_tad_decode(struct decoded_addr *res)
656 {
657 int i;
658 u32 base, wayness, chnilvoffset;
659 int skt_interleave_bit, chn_interleave_bit;
660 u64 channel_addr;
661
662 for (i = 0; i < SKX_MAX_TAD; i++) {
663 SKX_GET_TADBASE(res->dev, res->imc, i, base);
664 SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness);
665 if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness))
666 goto tad_found;
667 }
668 edac_dbg(0, "No TAD entry for %llx\n", res->addr);
669 return false;
670
671 tad_found:
672 res->sktways = SKX_TAD_SKTWAYS(wayness);
673 res->chanways = SKX_TAD_CHNWAYS(wayness);
674 skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)];
675 chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)];
676
677 SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset);
678 channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset);
679
680 if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) {
681 /* Must handle channel first, then socket */
682 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
683 res->chanways, channel_addr);
684 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
685 res->sktways, channel_addr);
686 } else {
687 /* Handle socket then channel. Preserve low bits from original address */
688 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
689 res->sktways, res->addr);
690 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
691 res->chanways, res->addr);
692 }
693
694 res->chan_addr = channel_addr;
695
696 edac_dbg(2, "%llx: chan_addr=%llx sktways=%d chanways=%d\n",
697 res->addr, res->chan_addr, res->sktways, res->chanways);
698 return true;
699 }
700
701 #define SKX_MAX_RIR 4
702
703 #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \
704 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
705 0x108 + 4 * (i), &reg)
706 #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \
707 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
708 0x120 + 16 * idx + 4 * (i), &reg)
709
710 #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31)
711 #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29)
712 #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29))
713 #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19)
714 #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26))
715
716 static bool skx_rir_decode(struct decoded_addr *res)
717 {
718 int i, idx, chan_rank;
719 int shift;
720 u32 rirway, rirlv;
721 u64 rank_addr, prev_limit = 0, limit;
722
723 if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg)
724 shift = 6;
725 else
726 shift = 13;
727
728 for (i = 0; i < SKX_MAX_RIR; i++) {
729 SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway);
730 limit = SKX_RIR_LIMIT(rirway);
731 if (SKX_RIR_VALID(rirway)) {
732 if (prev_limit <= res->chan_addr &&
733 res->chan_addr <= limit)
734 goto rir_found;
735 }
736 prev_limit = limit;
737 }
738 edac_dbg(0, "No RIR entry for %llx\n", res->addr);
739 return false;
740
741 rir_found:
742 rank_addr = res->chan_addr >> shift;
743 rank_addr /= SKX_RIR_WAYS(rirway);
744 rank_addr <<= shift;
745 rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0);
746
747 res->rank_address = rank_addr;
748 idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway);
749
750 SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv);
751 res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv);
752 chan_rank = SKX_RIR_CHAN_RANK(rirlv);
753 res->channel_rank = chan_rank;
754 res->dimm = chan_rank / 4;
755 res->rank = chan_rank % 4;
756
757 edac_dbg(2, "%llx: dimm=%d rank=%d chan_rank=%d rank_addr=%llx\n",
758 res->addr, res->dimm, res->rank,
759 res->channel_rank, res->rank_address);
760 return true;
761 }
762
763 static u8 skx_close_row[] = {
764 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33
765 };
766 static u8 skx_close_column[] = {
767 3, 4, 5, 14, 19, 23, 24, 25, 26, 27
768 };
769 static u8 skx_open_row[] = {
770 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33
771 };
772 static u8 skx_open_column[] = {
773 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
774 };
775 static u8 skx_open_fine_column[] = {
776 3, 4, 5, 7, 8, 9, 10, 11, 12, 13
777 };
778
779 static int skx_bits(u64 addr, int nbits, u8 *bits)
780 {
781 int i, res = 0;
782
783 for (i = 0; i < nbits; i++)
784 res |= ((addr >> bits[i]) & 1) << i;
785 return res;
786 }
787
788 static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)
789 {
790 int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);
791
792 if (do_xor)
793 ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);
794
795 return ret;
796 }
797
798 static bool skx_mad_decode(struct decoded_addr *r)
799 {
800 struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm];
801 int bg0 = dimm->fine_grain_bank ? 6 : 13;
802
803 if (dimm->close_pg) {
804 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row);
805 r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column);
806 r->column |= 0x400; /* C10 is autoprecharge, always set */
807 r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28);
808 r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21);
809 } else {
810 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row);
811 if (dimm->fine_grain_bank)
812 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column);
813 else
814 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column);
815 r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23);
816 r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21);
817 }
818 r->row &= (1u << dimm->rowbits) - 1;
819
820 edac_dbg(2, "%llx: row=%x col=%x bank_addr=%d bank_group=%d\n",
821 r->addr, r->row, r->column, r->bank_address,
822 r->bank_group);
823 return true;
824 }
825
826 static bool skx_decode(struct decoded_addr *res)
827 {
828
829 return skx_sad_decode(res) && skx_tad_decode(res) &&
830 skx_rir_decode(res) && skx_mad_decode(res);
831 }
832
833 #ifdef CONFIG_EDAC_DEBUG
834 /*
835 * Debug feature. Make /sys/kernel/debug/skx_edac_test/addr.
836 * Write an address to this file to exercise the address decode
837 * logic in this driver.
838 */
839 static struct dentry *skx_test;
840 static u64 skx_fake_addr;
841
842 static int debugfs_u64_set(void *data, u64 val)
843 {
844 struct decoded_addr res;
845
846 res.addr = val;
847 skx_decode(&res);
848
849 return 0;
850 }
851
852 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
853
854 static struct dentry *mydebugfs_create(const char *name, umode_t mode,
855 struct dentry *parent, u64 *value)
856 {
857 return debugfs_create_file(name, mode, parent, value, &fops_u64_wo);
858 }
859
860 static void setup_skx_debug(void)
861 {
862 skx_test = debugfs_create_dir("skx_edac_test", NULL);
863 mydebugfs_create("addr", S_IWUSR, skx_test, &skx_fake_addr);
864 }
865
866 static void teardown_skx_debug(void)
867 {
868 debugfs_remove_recursive(skx_test);
869 }
870 #else
871 static void setup_skx_debug(void)
872 {
873 }
874
875 static void teardown_skx_debug(void)
876 {
877 }
878 #endif /*CONFIG_EDAC_DEBUG*/
879
880 static void skx_mce_output_error(struct mem_ctl_info *mci,
881 const struct mce *m,
882 struct decoded_addr *res)
883 {
884 enum hw_event_mc_err_type tp_event;
885 char *type, *optype, msg[256];
886 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
887 bool overflow = GET_BITFIELD(m->status, 62, 62);
888 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
889 bool recoverable;
890 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
891 u32 mscod = GET_BITFIELD(m->status, 16, 31);
892 u32 errcode = GET_BITFIELD(m->status, 0, 15);
893 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
894
895 recoverable = GET_BITFIELD(m->status, 56, 56);
896
897 if (uncorrected_error) {
898 if (ripv) {
899 type = "FATAL";
900 tp_event = HW_EVENT_ERR_FATAL;
901 } else {
902 type = "NON_FATAL";
903 tp_event = HW_EVENT_ERR_UNCORRECTED;
904 }
905 } else {
906 type = "CORRECTED";
907 tp_event = HW_EVENT_ERR_CORRECTED;
908 }
909
910 /*
911 * According with Table 15-9 of the Intel Architecture spec vol 3A,
912 * memory errors should fit in this mask:
913 * 000f 0000 1mmm cccc (binary)
914 * where:
915 * f = Correction Report Filtering Bit. If 1, subsequent errors
916 * won't be shown
917 * mmm = error type
918 * cccc = channel
919 * If the mask doesn't match, report an error to the parsing logic
920 */
921 if (!((errcode & 0xef80) == 0x80)) {
922 optype = "Can't parse: it is not a mem";
923 } else {
924 switch (optypenum) {
925 case 0:
926 optype = "generic undef request error";
927 break;
928 case 1:
929 optype = "memory read error";
930 break;
931 case 2:
932 optype = "memory write error";
933 break;
934 case 3:
935 optype = "addr/cmd error";
936 break;
937 case 4:
938 optype = "memory scrubbing error";
939 break;
940 default:
941 optype = "reserved";
942 break;
943 }
944 }
945
946 snprintf(msg, sizeof(msg),
947 "%s%s err_code:%04x:%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:%x col:%x",
948 overflow ? " OVERFLOW" : "",
949 (uncorrected_error && recoverable) ? " recoverable" : "",
950 mscod, errcode,
951 res->socket, res->imc, res->rank,
952 res->bank_group, res->bank_address, res->row, res->column);
953
954 edac_dbg(0, "%s\n", msg);
955
956 /* Call the helper to output message */
957 edac_mc_handle_error(tp_event, mci, core_err_cnt,
958 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
959 res->channel, res->dimm, -1,
960 optype, msg);
961 }
962
963 static int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
964 void *data)
965 {
966 struct mce *mce = (struct mce *)data;
967 struct decoded_addr res;
968 struct mem_ctl_info *mci;
969 char *type;
970
971 if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
972 return NOTIFY_DONE;
973
974 /* ignore unless this is memory related with an address */
975 if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
976 return NOTIFY_DONE;
977
978 res.addr = mce->addr;
979 if (!skx_decode(&res))
980 return NOTIFY_DONE;
981 mci = res.dev->imc[res.imc].mci;
982
983 if (mce->mcgstatus & MCG_STATUS_MCIP)
984 type = "Exception";
985 else
986 type = "Event";
987
988 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
989
990 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
991 "Bank %d: %016Lx\n", mce->extcpu, type,
992 mce->mcgstatus, mce->bank, mce->status);
993 skx_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
994 skx_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
995 skx_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
996
997 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
998 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
999 mce->time, mce->socketid, mce->apicid);
1000
1001 skx_mce_output_error(mci, mce, &res);
1002
1003 return NOTIFY_DONE;
1004 }
1005
1006 static struct notifier_block skx_mce_dec = {
1007 .notifier_call = skx_mce_check_error,
1008 .priority = MCE_PRIO_EDAC,
1009 };
1010
1011 static void skx_remove(void)
1012 {
1013 int i, j;
1014 struct skx_dev *d, *tmp;
1015
1016 edac_dbg(0, "\n");
1017
1018 list_for_each_entry_safe(d, tmp, &skx_edac_list, list) {
1019 list_del(&d->list);
1020 for (i = 0; i < NUM_IMC; i++) {
1021 skx_unregister_mci(&d->imc[i]);
1022 for (j = 0; j < NUM_CHANNELS; j++)
1023 pci_dev_put(d->imc[i].chan[j].cdev);
1024 }
1025 pci_dev_put(d->util_all);
1026 pci_dev_put(d->sad_all);
1027
1028 kfree(d);
1029 }
1030 }
1031
1032 /*
1033 * skx_init:
1034 * make sure we are running on the correct cpu model
1035 * search for all the devices we need
1036 * check which DIMMs are present.
1037 */
1038 static int __init skx_init(void)
1039 {
1040 const struct x86_cpu_id *id;
1041 const struct munit *m;
1042 int rc = 0, i;
1043 u8 mc = 0, src_id, node_id;
1044 struct skx_dev *d;
1045
1046 edac_dbg(2, "\n");
1047
1048 id = x86_match_cpu(skx_cpuids);
1049 if (!id)
1050 return -ENODEV;
1051
1052 rc = skx_get_hi_lo();
1053 if (rc)
1054 return rc;
1055
1056 rc = get_all_bus_mappings();
1057 if (rc < 0)
1058 goto fail;
1059 if (rc == 0) {
1060 edac_dbg(2, "No memory controllers found\n");
1061 return -ENODEV;
1062 }
1063
1064 for (m = skx_all_munits; m->did; m++) {
1065 rc = get_all_munits(m);
1066 if (rc < 0)
1067 goto fail;
1068 if (rc != m->per_socket * skx_num_sockets) {
1069 edac_dbg(2, "Expected %d, got %d of %x\n",
1070 m->per_socket * skx_num_sockets, rc, m->did);
1071 rc = -ENODEV;
1072 goto fail;
1073 }
1074 }
1075
1076 list_for_each_entry(d, &skx_edac_list, list) {
1077 src_id = get_src_id(d);
1078 node_id = skx_get_node_id(d);
1079 edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id);
1080 for (i = 0; i < NUM_IMC; i++) {
1081 d->imc[i].mc = mc++;
1082 d->imc[i].lmc = i;
1083 d->imc[i].src_id = src_id;
1084 d->imc[i].node_id = node_id;
1085 rc = skx_register_mci(&d->imc[i]);
1086 if (rc < 0)
1087 goto fail;
1088 }
1089 }
1090
1091 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1092 opstate_init();
1093
1094 setup_skx_debug();
1095
1096 mce_register_decode_chain(&skx_mce_dec);
1097
1098 return 0;
1099 fail:
1100 skx_remove();
1101 return rc;
1102 }
1103
1104 static void __exit skx_exit(void)
1105 {
1106 edac_dbg(2, "\n");
1107 mce_unregister_decode_chain(&skx_mce_dec);
1108 skx_remove();
1109 teardown_skx_debug();
1110 }
1111
1112 module_init(skx_init);
1113 module_exit(skx_exit);
1114
1115 module_param(edac_op_state, int, 0444);
1116 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1117
1118 MODULE_LICENSE("GPL v2");
1119 MODULE_AUTHOR("Tony Luck");
1120 MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors");
Linux with added FPC-III support