Linux 4.14.51
[linux/fpc-iii.git] / drivers / pinctrl / freescale / pinctrl-imx.h
blob5aa22b52c1d4ac2d878a779ff2e3c94e10b5e88c
1 /*
2 * IMX pinmux core definitions
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #ifndef __DRIVERS_PINCTRL_IMX_H
16 #define __DRIVERS_PINCTRL_IMX_H
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinmux.h>
21 struct platform_device;
23 extern struct pinmux_ops imx_pmx_ops;
25 /**
26 * struct imx_pin - describes a single i.MX pin
27 * @pin: the pin_id of this pin
28 * @mux_mode: the mux mode for this pin.
29 * @input_reg: the select input register offset for this pin if any
30 * 0 if no select input setting needed.
31 * @input_val: the select input value for this pin.
32 * @configs: the config for this pin.
34 struct imx_pin {
35 unsigned int pin;
36 unsigned int mux_mode;
37 u16 input_reg;
38 unsigned int input_val;
39 unsigned long config;
42 /**
43 * struct imx_pin_reg - describe a pin reg map
44 * @mux_reg: mux register offset
45 * @conf_reg: config register offset
47 struct imx_pin_reg {
48 s16 mux_reg;
49 s16 conf_reg;
52 /* decode a generic config into raw register value */
53 struct imx_cfg_params_decode {
54 enum pin_config_param param;
55 u32 mask;
56 u8 shift;
57 bool invert;
60 struct imx_pinctrl_soc_info {
61 struct device *dev;
62 const struct pinctrl_pin_desc *pins;
63 unsigned int npins;
64 struct imx_pin_reg *pin_regs;
65 unsigned int group_index;
66 unsigned int flags;
67 const char *gpr_compatible;
68 struct mutex mutex;
70 /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
71 unsigned int mux_mask;
72 u8 mux_shift;
74 /* generic pinconf */
75 bool generic_pinconf;
76 const struct pinconf_generic_params *custom_params;
77 unsigned int num_custom_params;
78 struct imx_cfg_params_decode *decodes;
79 unsigned int num_decodes;
80 void (*fixup)(unsigned long *configs, unsigned int num_configs,
81 u32 *raw_config);
83 int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
84 struct pinctrl_gpio_range *range,
85 unsigned offset,
86 bool input);
89 /**
90 * @dev: a pointer back to containing device
91 * @base: the offset to the controller in virtual memory
93 struct imx_pinctrl {
94 struct device *dev;
95 struct pinctrl_dev *pctl;
96 void __iomem *base;
97 void __iomem *input_sel_base;
98 struct imx_pinctrl_soc_info *info;
101 #define IMX_CFG_PARAMS_DECODE(p, m, o) \
102 { .param = p, .mask = m, .shift = o, .invert = false, }
104 #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
105 { .param = p, .mask = m, .shift = o, .invert = true, }
107 #define SHARE_MUX_CONF_REG 0x1
108 #define ZERO_OFFSET_VALID 0x2
110 #define NO_MUX 0x0
111 #define NO_PAD 0x0
113 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
115 #define PAD_CTL_MASK(len) ((1 << len) - 1)
116 #define IMX_MUX_MASK 0x7
117 #define IOMUXC_CONFIG_SION (0x1 << 4)
119 int imx_pinctrl_probe(struct platform_device *pdev,
120 struct imx_pinctrl_soc_info *info);
121 #endif /* __DRIVERS_PINCTRL_IMX_H */